^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/net/phy/lxt.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Driver for Intel LXT PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Andy Fleming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2004 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/unistd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* The Level one LXT970 is used by many boards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MII_LXT970_IER 17 /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MII_LXT970_IER_IEN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MII_LXT970_ISR 18 /* Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MII_LXT970_CONFIG 19 /* Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* The Level one LXT971 is used on some of my custom boards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* register definitions for the 971 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MII_LXT971_IER 18 /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MII_LXT971_IER_IEN 0x00f2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MII_LXT971_ISR 19 /* Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* register definitions for the 973 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MII_LXT973_PCR 16 /* Port Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCR_FIBER_SELECT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MODULE_DESCRIPTION("Intel LXT PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MODULE_AUTHOR("Andy Fleming");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static int lxt970_ack_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) err = phy_read(phydev, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) err = phy_read(phydev, MII_LXT970_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int lxt970_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return phy_write(phydev, MII_LXT970_IER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int lxt970_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return phy_write(phydev, MII_LXT970_CONFIG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int lxt971_ack_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int err = phy_read(phydev, MII_LXT971_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int lxt971_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return phy_write(phydev, MII_LXT971_IER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * A2 version of LXT973 chip has an ERRATA: it randomly return the contents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * of the previous even register when you read a odd register regularly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int lxt973a2_update_link(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int retry = 8; /* we try 8 times */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Do a fake read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) status = phy_read(phydev, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) control = phy_read(phydev, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (control < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Read link and autonegotiation status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) status = phy_read(phydev, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) } while (status >= 0 && retry-- && status == control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if ((status & BMSR_LSTATUS) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) phydev->link = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) phydev->link = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int lxt973a2_read_status(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int adv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int lpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Update the link, but return if there was an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) err = lxt973a2_update_link(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (AUTONEG_ENABLE == phydev->autoneg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int retry = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) adv = phy_read(phydev, MII_ADVERTISE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (adv < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return adv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) lpa = phy_read(phydev, MII_LPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (lpa < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return lpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* If both registers are equal, it is suspect but not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * impossible, hence a new try
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) } while (lpa == adv && retry--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) mii_lpa_to_linkmode_lpa_t(phydev->lp_advertising, lpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) lpa &= adv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) phydev->speed = SPEED_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) phydev->duplex = DUPLEX_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) phydev->pause = phydev->asym_pause = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (lpa & (LPA_100FULL | LPA_100HALF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) phydev->speed = SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (lpa & LPA_100FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) phydev->duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (lpa & LPA_10FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) phydev->duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) phy_resolve_aneg_pause(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) err = genphy_read_status_fixed(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) phydev->pause = phydev->asym_pause = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) linkmode_zero(phydev->lp_advertising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int lxt973_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int val = phy_read(phydev, MII_LXT973_PCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (val & PCR_FIBER_SELECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * If fiber is selected, then the only correct setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * is 100Mbps, full duplex, and auto negotiation off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) val = phy_read(phydev, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) val &= ~BMCR_ANENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) phy_write(phydev, MII_BMCR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Remember that the port is in fiber mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) phydev->priv = lxt973_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) phydev->port = PORT_FIBRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) phydev->priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int lxt973_config_aneg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Do nothing if port is in fiber mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return phydev->priv ? 0 : genphy_config_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static struct phy_driver lxt97x_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .phy_id = 0x78100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .name = "LXT970",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* PHY_BASIC_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .config_init = lxt970_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .ack_interrupt = lxt970_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .config_intr = lxt970_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .phy_id = 0x001378e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .name = "LXT971",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* PHY_BASIC_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .ack_interrupt = lxt971_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .config_intr = lxt971_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .resume = genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .phy_id = 0x00137a10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .name = "LXT973-A2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .phy_id_mask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* PHY_BASIC_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .probe = lxt973_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .config_aneg = lxt973_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .read_status = lxt973a2_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .resume = genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .phy_id = 0x00137a10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .name = "LXT973",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* PHY_BASIC_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .probe = lxt973_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .config_aneg = lxt973_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .resume = genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) module_phy_driver(lxt97x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static struct mdio_device_id __maybe_unused lxt_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { 0x78100000, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { 0x001378e0, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { 0x00137a10, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MODULE_DEVICE_TABLE(mdio, lxt_tbl);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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