Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define XWAY_MDIO_IMASK			0x19	/* interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define XWAY_MDIO_ISTAT			0x1A	/* interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define XWAY_MDIO_LED			0x1B	/* led control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /* bit 15:12 are reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define XWAY_MDIO_LED_LED3_EN		BIT(11)	/* Enable the integrated function of LED3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define XWAY_MDIO_LED_LED2_EN		BIT(10)	/* Enable the integrated function of LED2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define XWAY_MDIO_LED_LED1_EN		BIT(9)	/* Enable the integrated function of LED1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define XWAY_MDIO_LED_LED0_EN		BIT(8)	/* Enable the integrated function of LED0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* bit 7:4 are reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define XWAY_MDIO_LED_LED3_DA		BIT(3)	/* Direct Access to LED3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define XWAY_MDIO_LED_LED2_DA		BIT(2)	/* Direct Access to LED2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define XWAY_MDIO_LED_LED1_DA		BIT(1)	/* Direct Access to LED1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define XWAY_MDIO_LED_LED0_DA		BIT(0)	/* Direct Access to LED0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define XWAY_MDIO_INIT_WOL		BIT(15)	/* Wake-On-LAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define XWAY_MDIO_INIT_MSRE		BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define XWAY_MDIO_INIT_NPRX		BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define XWAY_MDIO_INIT_NPTX		BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define XWAY_MDIO_INIT_ANE		BIT(11)	/* Auto-Neg error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define XWAY_MDIO_INIT_ANC		BIT(10)	/* Auto-Neg complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define XWAY_MDIO_INIT_ADSC		BIT(5)	/* Link auto-downspeed detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define XWAY_MDIO_INIT_MPIPC		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define XWAY_MDIO_INIT_MDIXC		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define XWAY_MDIO_INIT_DXMC		BIT(2)	/* Duplex mode change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define XWAY_MDIO_INIT_LSPC		BIT(1)	/* Link speed change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define XWAY_MDIO_INIT_LSTC		BIT(0)	/* Link state change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define XWAY_MDIO_INIT_MASK		(XWAY_MDIO_INIT_LSTC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 					 XWAY_MDIO_INIT_ADSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ADVERTISED_MPD			BIT(10)	/* Multi-port device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* LED Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define XWAY_MMD_LEDCH			0x01E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* Inverse of SCAN Function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define  XWAY_MMD_LEDCH_NACS_NONE	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define  XWAY_MMD_LEDCH_NACS_LINK	0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define  XWAY_MMD_LEDCH_NACS_PDOWN	0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define  XWAY_MMD_LEDCH_NACS_EEE	0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define  XWAY_MMD_LEDCH_NACS_ANEG	0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define  XWAY_MMD_LEDCH_NACS_ABIST	0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define  XWAY_MMD_LEDCH_NACS_CDIAG	0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define  XWAY_MMD_LEDCH_NACS_TEST	0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* Slow Blink Frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define  XWAY_MMD_LEDCH_SBF_F02HZ	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define  XWAY_MMD_LEDCH_SBF_F04HZ	0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define  XWAY_MMD_LEDCH_SBF_F08HZ	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define  XWAY_MMD_LEDCH_SBF_F16HZ	0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* Fast Blink Frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define  XWAY_MMD_LEDCH_FBF_F02HZ	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define  XWAY_MMD_LEDCH_FBF_F04HZ	0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define  XWAY_MMD_LEDCH_FBF_F08HZ	0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define  XWAY_MMD_LEDCH_FBF_F16HZ	0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* LED Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define XWAY_MMD_LEDCL			0x01E1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* Complex Blinking Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define  XWAY_MMD_LEDCH_CBLINK_NONE	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define  XWAY_MMD_LEDCH_CBLINK_LINK	0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define  XWAY_MMD_LEDCH_CBLINK_PDOWN	0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define  XWAY_MMD_LEDCH_CBLINK_EEE	0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define  XWAY_MMD_LEDCH_CBLINK_ANEG	0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define  XWAY_MMD_LEDCH_CBLINK_ABIST	0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define  XWAY_MMD_LEDCH_CBLINK_CDIAG	0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define  XWAY_MMD_LEDCH_CBLINK_TEST	0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /* Complex SCAN Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define  XWAY_MMD_LEDCH_SCAN_NONE	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define  XWAY_MMD_LEDCH_SCAN_LINK	0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define  XWAY_MMD_LEDCH_SCAN_PDOWN	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define  XWAY_MMD_LEDCH_SCAN_EEE	0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define  XWAY_MMD_LEDCH_SCAN_ANEG	0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define  XWAY_MMD_LEDCH_SCAN_ABIST	0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define  XWAY_MMD_LEDCH_SCAN_CDIAG	0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define  XWAY_MMD_LEDCH_SCAN_TEST	0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* Configuration for LED Pin x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define XWAY_MMD_LED0H			0x01E2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /* Fast Blinking Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define  XWAY_MMD_LEDxH_BLINKF_MASK	0x000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define  XWAY_MMD_LEDxH_BLINKF_NONE	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define  XWAY_MMD_LEDxH_BLINKF_LINK10	0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define  XWAY_MMD_LEDxH_BLINKF_LINK100	0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define  XWAY_MMD_LEDxH_BLINKF_LINK10X	0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define  XWAY_MMD_LEDxH_BLINKF_LINK1000	0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define  XWAY_MMD_LEDxH_BLINKF_LINK10_0	0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define  XWAY_MMD_LEDxH_BLINKF_LINK100X	0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define  XWAY_MMD_LEDxH_BLINKF_LINK10XX	0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define  XWAY_MMD_LEDxH_BLINKF_PDOWN	0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define  XWAY_MMD_LEDxH_BLINKF_EEE	0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define  XWAY_MMD_LEDxH_BLINKF_ANEG	0x000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define  XWAY_MMD_LEDxH_BLINKF_ABIST	0x000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define  XWAY_MMD_LEDxH_BLINKF_CDIAG	0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Constant On Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define  XWAY_MMD_LEDxH_CON_MASK	0x00F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define  XWAY_MMD_LEDxH_CON_NONE	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define  XWAY_MMD_LEDxH_CON_LINK10	0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define  XWAY_MMD_LEDxH_CON_LINK100	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define  XWAY_MMD_LEDxH_CON_LINK10X	0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define  XWAY_MMD_LEDxH_CON_LINK1000	0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define  XWAY_MMD_LEDxH_CON_LINK10_0	0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define  XWAY_MMD_LEDxH_CON_LINK100X	0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define  XWAY_MMD_LEDxH_CON_LINK10XX	0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define  XWAY_MMD_LEDxH_CON_PDOWN	0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define  XWAY_MMD_LEDxH_CON_EEE		0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define  XWAY_MMD_LEDxH_CON_ANEG	0x00A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define  XWAY_MMD_LEDxH_CON_ABIST	0x00B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define  XWAY_MMD_LEDxH_CON_CDIAG	0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define  XWAY_MMD_LEDxH_CON_COPPER	0x00D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define  XWAY_MMD_LEDxH_CON_FIBER	0x00E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Configuration for LED Pin x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define XWAY_MMD_LED0L			0x01E3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Pulsing Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define  XWAY_MMD_LEDxL_PULSE_MASK	0x000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define  XWAY_MMD_LEDxL_PULSE_NONE	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define  XWAY_MMD_LEDxL_PULSE_TXACT	0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define  XWAY_MMD_LEDxL_PULSE_RXACT	0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define  XWAY_MMD_LEDxL_PULSE_COL	0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Slow Blinking Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define  XWAY_MMD_LEDxL_BLINKS_MASK	0x00F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define  XWAY_MMD_LEDxL_BLINKS_NONE	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define  XWAY_MMD_LEDxL_BLINKS_LINK10	0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define  XWAY_MMD_LEDxL_BLINKS_LINK100	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define  XWAY_MMD_LEDxL_BLINKS_LINK10X	0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define  XWAY_MMD_LEDxL_BLINKS_LINK1000	0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define  XWAY_MMD_LEDxL_BLINKS_LINK10_0	0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define  XWAY_MMD_LEDxL_BLINKS_LINK100X	0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define  XWAY_MMD_LEDxL_BLINKS_LINK10XX	0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define  XWAY_MMD_LEDxL_BLINKS_PDOWN	0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define  XWAY_MMD_LEDxL_BLINKS_EEE	0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define  XWAY_MMD_LEDxL_BLINKS_ANEG	0x00A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define  XWAY_MMD_LEDxL_BLINKS_ABIST	0x00B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define  XWAY_MMD_LEDxL_BLINKS_CDIAG	0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define XWAY_MMD_LED1H			0x01E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define XWAY_MMD_LED1L			0x01E5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define XWAY_MMD_LED2H			0x01E6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define XWAY_MMD_LED2L			0x01E7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define XWAY_MMD_LED3H			0x01E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define XWAY_MMD_LED3L			0x01E9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PHY_ID_PHY11G_1_3		0x030260D1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PHY_ID_PHY22F_1_3		0x030260E1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PHY_ID_PHY11G_1_4		0xD565A400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PHY_ID_PHY22F_1_4		0xD565A410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PHY_ID_PHY11G_1_5		0xD565A401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PHY_ID_PHY22F_1_5		0xD565A411
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PHY_ID_PHY11G_VR9_1_1		0xD565A408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PHY_ID_PHY22F_VR9_1_1		0xD565A418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PHY_ID_PHY11G_VR9_1_2		0xD565A409
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PHY_ID_PHY22F_VR9_1_2		0xD565A419
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int xway_gphy_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	u32 ledxh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	u32 ledxl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	/* Mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	err = phy_write(phydev, XWAY_MDIO_IMASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	/* Clear all pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	phy_read(phydev, XWAY_MDIO_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* Ensure that integrated led function is enabled for all leds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	err = phy_write(phydev, XWAY_MDIO_LED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			XWAY_MDIO_LED_LED0_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			XWAY_MDIO_LED_LED1_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			XWAY_MDIO_LED_LED2_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			XWAY_MDIO_LED_LED3_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		      XWAY_MMD_LEDCH_NACS_NONE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		      XWAY_MMD_LEDCH_SBF_F02HZ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		      XWAY_MMD_LEDCH_FBF_F16HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		      XWAY_MMD_LEDCH_CBLINK_NONE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		      XWAY_MMD_LEDCH_SCAN_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 * In most cases only one LED is connected to this phy, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 * configure them all to constant on and pulse mode. LED3 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 * only available in some packages, leave it in its reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 * configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ledxh = XWAY_MMD_LEDxH_BLINKF_NONE | XWAY_MMD_LEDxH_CON_LINK10XX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	ledxl = XWAY_MMD_LEDxL_PULSE_TXACT | XWAY_MMD_LEDxL_PULSE_RXACT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		XWAY_MMD_LEDxL_BLINKS_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, ledxh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, ledxl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, ledxh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, ledxl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int xway_gphy14_config_aneg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	int reg, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	/* Advertise as multi-port device, see IEEE802.3-2002 40.5.1.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	/* This is a workaround for an errata in rev < 1.5 devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	reg = phy_read(phydev, MII_CTRL1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	reg |= ADVERTISED_MPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	err = phy_write(phydev, MII_CTRL1000, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	return genphy_config_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int xway_gphy_ack_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	reg = phy_read(phydev, XWAY_MDIO_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return (reg < 0) ? reg : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int xway_gphy_did_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	reg = phy_read(phydev, XWAY_MDIO_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return reg & XWAY_MDIO_INIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int xway_gphy_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	u16 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		mask = XWAY_MDIO_INIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return phy_write(phydev, XWAY_MDIO_IMASK, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct phy_driver xway_gphy[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		.phy_id		= PHY_ID_PHY11G_1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		.phy_id_mask	= 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		.name		= "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		/* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		.config_init	= xway_gphy_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		.config_aneg	= xway_gphy14_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		.ack_interrupt	= xway_gphy_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		.did_interrupt	= xway_gphy_did_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		.config_intr	= xway_gphy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		.suspend	= genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		.resume		= genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		.phy_id		= PHY_ID_PHY22F_1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		.phy_id_mask	= 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		.name		= "Intel XWAY PHY22F (PEF 7061) v1.3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		/* PHY_BASIC_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		.config_init	= xway_gphy_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		.config_aneg	= xway_gphy14_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		.ack_interrupt	= xway_gphy_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		.did_interrupt	= xway_gphy_did_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		.config_intr	= xway_gphy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		.suspend	= genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		.resume		= genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		.phy_id		= PHY_ID_PHY11G_1_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		.phy_id_mask	= 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		.name		= "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		/* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		.config_init	= xway_gphy_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		.config_aneg	= xway_gphy14_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		.ack_interrupt	= xway_gphy_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		.did_interrupt	= xway_gphy_did_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		.config_intr	= xway_gphy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		.suspend	= genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		.resume		= genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.phy_id		= PHY_ID_PHY22F_1_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		.phy_id_mask	= 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		.name		= "Intel XWAY PHY22F (PEF 7061) v1.4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		/* PHY_BASIC_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.config_init	= xway_gphy_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		.config_aneg	= xway_gphy14_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		.ack_interrupt	= xway_gphy_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		.did_interrupt	= xway_gphy_did_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		.config_intr	= xway_gphy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		.suspend	= genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		.resume		= genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		.phy_id		= PHY_ID_PHY11G_1_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		.phy_id_mask	= 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		.name		= "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.5 / v1.6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		/* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		.config_init	= xway_gphy_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		.ack_interrupt	= xway_gphy_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		.did_interrupt	= xway_gphy_did_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		.config_intr	= xway_gphy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		.suspend	= genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		.resume		= genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		.phy_id		= PHY_ID_PHY22F_1_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		.phy_id_mask	= 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		.name		= "Intel XWAY PHY22F (PEF 7061) v1.5 / v1.6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		/* PHY_BASIC_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		.config_init	= xway_gphy_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		.ack_interrupt	= xway_gphy_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		.did_interrupt	= xway_gphy_did_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		.config_intr	= xway_gphy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		.suspend	= genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		.resume		= genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		.phy_id		= PHY_ID_PHY11G_VR9_1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		.phy_id_mask	= 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		.name		= "Intel XWAY PHY11G (xRX v1.1 integrated)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		/* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		.config_init	= xway_gphy_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		.ack_interrupt	= xway_gphy_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		.did_interrupt	= xway_gphy_did_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		.config_intr	= xway_gphy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		.suspend	= genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		.resume		= genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		.phy_id		= PHY_ID_PHY22F_VR9_1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		.phy_id_mask	= 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		.name		= "Intel XWAY PHY22F (xRX v1.1 integrated)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		/* PHY_BASIC_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		.config_init	= xway_gphy_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		.ack_interrupt	= xway_gphy_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		.did_interrupt	= xway_gphy_did_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		.config_intr	= xway_gphy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		.suspend	= genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		.resume		= genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		.phy_id		= PHY_ID_PHY11G_VR9_1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		.phy_id_mask	= 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		.name		= "Intel XWAY PHY11G (xRX v1.2 integrated)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		/* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		.config_init	= xway_gphy_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.ack_interrupt	= xway_gphy_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.did_interrupt	= xway_gphy_did_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		.config_intr	= xway_gphy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		.suspend	= genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		.resume		= genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		.phy_id		= PHY_ID_PHY22F_VR9_1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		.phy_id_mask	= 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		.name		= "Intel XWAY PHY22F (xRX v1.2 integrated)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		/* PHY_BASIC_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		.config_init	= xway_gphy_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		.ack_interrupt	= xway_gphy_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		.did_interrupt	= xway_gphy_did_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		.config_intr	= xway_gphy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		.suspend	= genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		.resume		= genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) module_phy_driver(xway_gphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static struct mdio_device_id __maybe_unused xway_gphy_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	{ PHY_ID_PHY11G_1_3, 0xffffffff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	{ PHY_ID_PHY22F_1_3, 0xffffffff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	{ PHY_ID_PHY11G_1_4, 0xffffffff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	{ PHY_ID_PHY22F_1_4, 0xffffffff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	{ PHY_ID_PHY11G_1_5, 0xffffffff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	{ PHY_ID_PHY22F_1_5, 0xffffffff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	{ PHY_ID_PHY11G_VR9_1_1, 0xffffffff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	{ PHY_ID_PHY22F_VR9_1_1, 0xffffffff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	{ PHY_ID_PHY11G_VR9_1_2, 0xffffffff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	{ PHY_ID_PHY22F_VR9_1_2, 0xffffffff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MODULE_DEVICE_TABLE(mdio, xway_gphy_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MODULE_DESCRIPTION("Intel XWAY PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MODULE_LICENSE("GPL");