^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for ICPlus PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2007 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/unistd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IP101G/IC1001 PHY drivers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_AUTHOR("Michael Barkowski");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* IP101A/G - IP1001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IP1001_RXPHASE_SEL BIT(0) /* Add delay on RX_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IP1001_TXPHASE_SEL BIT(1) /* Add delay on TX_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IP101A_G_APS_ON BIT(1) /* IP101A/G APS Mode bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IP101A_G_IRQ_PIN_USED BIT(15) /* INTR pin used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IP101A_G_IRQ_ALL_MASK BIT(11) /* IRQ's inactive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IP101A_G_IRQ_SPEED_CHANGE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IP101A_G_IRQ_DUPLEX_CHANGE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IP101A_G_IRQ_LINK_CHANGE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IP101G_DIGITAL_IO_SPEC_CTRL 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* The 32-pin IP101GR package can re-configure the mode of the RXER/INTR_32 pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * (pin number 21). The hardware default is RXER (receive error) mode. But it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * can be configured to interrupt mode manually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) enum ip101gr_sel_intr32 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) IP101GR_SEL_INTR32_KEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) IP101GR_SEL_INTR32_INTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) IP101GR_SEL_INTR32_RXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct ip101a_g_phy_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum ip101gr_sel_intr32 sel_intr32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int ip175c_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int full_reset_performed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (full_reset_performed == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* master reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) err = mdiobus_write(phydev->mdio.bus, 30, 0, 0x175c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* ensure no bus delays overlap reset period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) err = mdiobus_read(phydev->mdio.bus, 30, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* data sheet specifies reset period is 2 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) mdelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* enable IP175C mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) err = mdiobus_write(phydev->mdio.bus, 29, 31, 0x175c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Set MII0 speed and duplex (in PHY mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) err = mdiobus_write(phydev->mdio.bus, 29, 22, 0x420);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* reset switch ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) err = mdiobus_write(phydev->mdio.bus, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MII_BMCR, BMCR_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) for (i = 0; i < 5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) err = mdiobus_read(phydev->mdio.bus, i, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mdelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) full_reset_performed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (phydev->mdio.addr != 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) phydev->state = PHY_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) phydev->speed = SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) phydev->duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) phydev->link = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) netif_carrier_on(phydev->attached_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int ip1xx_reset(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int bmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Software Reset PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) bmcr = phy_read(phydev, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (bmcr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return bmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) bmcr |= BMCR_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) bmcr = phy_write(phydev, MII_BMCR, bmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (bmcr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return bmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) bmcr = phy_read(phydev, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (bmcr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return bmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) } while (bmcr & BMCR_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int ip1001_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) c = ip1xx_reset(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (c < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Enable Auto Power Saving mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (c < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) c |= IP1001_APS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (c < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (phy_interface_is_rgmii(phydev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (c < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) c &= ~(IP1001_RXPHASE_SEL | IP1001_TXPHASE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) c |= (IP1001_RXPHASE_SEL | IP1001_TXPHASE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) c |= IP1001_RXPHASE_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) c |= IP1001_TXPHASE_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (c < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int ip175c_read_status(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (phydev->mdio.addr == 4) /* WAN port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) genphy_read_status(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Don't need to read status for switch ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) phydev->irq = PHY_IGNORE_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int ip175c_config_aneg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (phydev->mdio.addr == 4) /* WAN port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) genphy_config_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int ip101a_g_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct device *dev = &phydev->mdio.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct ip101a_g_phy_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Both functions (RX error and interrupt status) are sharing the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * pin on the 32-pin IP101GR, so this is an exclusive choice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (device_property_read_bool(dev, "icplus,select-rx-error") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) device_property_read_bool(dev, "icplus,select-interrupt")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "RXER and INTR mode cannot be selected together\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (device_property_read_bool(dev, "icplus,select-rx-error"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) priv->sel_intr32 = IP101GR_SEL_INTR32_RXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) else if (device_property_read_bool(dev, "icplus,select-interrupt"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) priv->sel_intr32 = IP101GR_SEL_INTR32_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) priv->sel_intr32 = IP101GR_SEL_INTR32_KEEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) phydev->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int ip101a_g_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct ip101a_g_phy_priv *priv = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int err, c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) c = ip1xx_reset(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (c < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* configure the RXER/INTR_32 pin of the 32-pin IP101GR if needed: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) switch (priv->sel_intr32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case IP101GR_SEL_INTR32_RXER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) err = phy_modify(phydev, IP101G_DIGITAL_IO_SPEC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case IP101GR_SEL_INTR32_INTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) err = phy_modify(phydev, IP101G_DIGITAL_IO_SPEC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Don't touch IP101G_DIGITAL_IO_SPEC_CTRL because it's not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * documented on IP101A and it's not clear whether this would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * cause problems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * For the 32-pin IP101GR we simply keep the SEL_INTR32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * configuration as set by the bootloader when not configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * to one of the special functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Enable Auto Power Saving mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) c |= IP101A_G_APS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int ip101a_g_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* INTR pin used: Speed/link/duplex will cause an interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) val = IP101A_G_IRQ_PIN_USED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) val = IP101A_G_IRQ_ALL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int ip101a_g_did_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int val = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return val & (IP101A_G_IRQ_SPEED_CHANGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) IP101A_G_IRQ_DUPLEX_CHANGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) IP101A_G_IRQ_LINK_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int ip101a_g_ack_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static struct phy_driver icplus_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .phy_id = 0x02430d80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .name = "ICPlus IP175C",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .phy_id_mask = 0x0ffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* PHY_BASIC_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .config_init = &ip175c_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .config_aneg = &ip175c_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .read_status = &ip175c_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .resume = genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .phy_id = 0x02430d90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .name = "ICPlus IP1001",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .phy_id_mask = 0x0ffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .config_init = &ip1001_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .resume = genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .phy_id = 0x02430c54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .name = "ICPlus IP101A/G",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .phy_id_mask = 0x0ffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* PHY_BASIC_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .probe = ip101a_g_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .config_intr = ip101a_g_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .did_interrupt = ip101a_g_did_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .ack_interrupt = ip101a_g_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .config_init = &ip101a_g_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .resume = genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) module_phy_driver(icplus_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static struct mdio_device_id __maybe_unused icplus_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { 0x02430d80, 0x0ffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { 0x02430d90, 0x0ffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { 0x02430c54, 0x0ffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) MODULE_DEVICE_TABLE(mdio, icplus_tbl);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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