Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Driver for the Texas Instruments DP83TC811 PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define DP83TC811_PHY_ID	0x2000a253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define DP83811_DEVADDR		0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MII_DP83811_SGMII_CTRL	0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MII_DP83811_INT_STAT1	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MII_DP83811_INT_STAT2	0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MII_DP83811_INT_STAT3	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MII_DP83811_RESET_CTRL	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define DP83811_HW_RESET	BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DP83811_SW_RESET	BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* INT_STAT1 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define DP83811_RX_ERR_HF_INT_EN	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define DP83811_MS_TRAINING_INT_EN	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define DP83811_ANEG_COMPLETE_INT_EN	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define DP83811_ESD_EVENT_INT_EN	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DP83811_WOL_INT_EN		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DP83811_LINK_STAT_INT_EN	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DP83811_ENERGY_DET_INT_EN	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DP83811_LINK_QUAL_INT_EN	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* INT_STAT2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define DP83811_JABBER_DET_INT_EN	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define DP83811_POLARITY_INT_EN		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DP83811_SLEEP_MODE_INT_EN	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define DP83811_OVERTEMP_INT_EN		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define DP83811_OVERVOLTAGE_INT_EN	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define DP83811_UNDERVOLTAGE_INT_EN	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* INT_STAT3 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define DP83811_LPS_INT_EN	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define DP83811_NO_FRAME_INT_EN	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define DP83811_POR_DONE_INT_EN	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MII_DP83811_RXSOP1	0x04a5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define MII_DP83811_RXSOP2	0x04a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MII_DP83811_RXSOP3	0x04a7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /* WoL Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define MII_DP83811_WOL_CFG	0x04a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define MII_DP83811_WOL_STAT	0x04a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MII_DP83811_WOL_DA1	0x04a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MII_DP83811_WOL_DA2	0x04a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MII_DP83811_WOL_DA3	0x04a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* WoL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define DP83811_WOL_MAGIC_EN	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define DP83811_WOL_SECURE_ON	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define DP83811_WOL_EN		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define DP83811_WOL_INDICATION_SEL BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define DP83811_WOL_CLR_INDICATION BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /* SGMII CTRL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define DP83811_TDR_AUTO		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define DP83811_SGMII_EN		BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define DP83811_SGMII_AUTO_NEG_EN	BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define DP83811_SGMII_TX_ERR_DIS	BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define DP83811_SGMII_SOFT_RESET	BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static int dp83811_ack_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	err = phy_read(phydev, MII_DP83811_INT_STAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	err = phy_read(phydev, MII_DP83811_INT_STAT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	err = phy_read(phydev, MII_DP83811_INT_STAT3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static int dp83811_set_wol(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			   struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct net_device *ndev = phydev->attached_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	const u8 *mac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		mac = (const u8 *)ndev->dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		if (!is_valid_ether_addr(mac))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		/* MAC addresses start with byte 5, but stored in mac[0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		 * 811 PHYs store bytes 4|5, 2|3, 0|1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			      (mac[1] << 8) | mac[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			      (mac[3] << 8) | mac[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			      (mac[5] << 8) | mac[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		value = phy_read_mmd(phydev, DP83811_DEVADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 				     MII_DP83811_WOL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		if (wol->wolopts & WAKE_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			value |= DP83811_WOL_MAGIC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			value &= ~DP83811_WOL_MAGIC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		if (wol->wolopts & WAKE_MAGICSECURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			phy_write_mmd(phydev, DP83811_DEVADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 				      MII_DP83811_RXSOP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 				      (wol->sopass[1] << 8) | wol->sopass[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			phy_write_mmd(phydev, DP83811_DEVADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 				      MII_DP83811_RXSOP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 				      (wol->sopass[3] << 8) | wol->sopass[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			phy_write_mmd(phydev, DP83811_DEVADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 				      MII_DP83811_RXSOP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 				      (wol->sopass[5] << 8) | wol->sopass[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			value |= DP83811_WOL_SECURE_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			value &= ~DP83811_WOL_SECURE_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		/* Clear any pending WoL interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		phy_read(phydev, MII_DP83811_INT_STAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		value |= DP83811_WOL_EN | DP83811_WOL_INDICATION_SEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			 DP83811_WOL_CLR_INDICATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return phy_write_mmd(phydev, DP83811_DEVADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 				     MII_DP83811_WOL_CFG, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		return phy_clear_bits_mmd(phydev, DP83811_DEVADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 					  MII_DP83811_WOL_CFG, DP83811_WOL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void dp83811_get_wol(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			    struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	u16 sopass_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	wol->wolopts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (value & DP83811_WOL_MAGIC_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		wol->wolopts |= WAKE_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (value & DP83811_WOL_SECURE_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 					  MII_DP83811_RXSOP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		wol->sopass[0] = (sopass_val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		wol->sopass[1] = (sopass_val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 					  MII_DP83811_RXSOP2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		wol->sopass[2] = (sopass_val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		wol->sopass[3] = (sopass_val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 					  MII_DP83811_RXSOP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		wol->sopass[4] = (sopass_val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		wol->sopass[5] = (sopass_val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		wol->wolopts |= WAKE_MAGICSECURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/* WoL is not enabled so set wolopts to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (!(value & DP83811_WOL_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		wol->wolopts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int dp83811_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	int misr_status, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		misr_status = phy_read(phydev, MII_DP83811_INT_STAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		if (misr_status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			return misr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		misr_status |= (DP83811_RX_ERR_HF_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 				DP83811_MS_TRAINING_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 				DP83811_ANEG_COMPLETE_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 				DP83811_ESD_EVENT_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				DP83811_WOL_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 				DP83811_LINK_STAT_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				DP83811_ENERGY_DET_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				DP83811_LINK_QUAL_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		err = phy_write(phydev, MII_DP83811_INT_STAT1, misr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		misr_status = phy_read(phydev, MII_DP83811_INT_STAT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		if (misr_status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			return misr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		misr_status |= (DP83811_JABBER_DET_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 				DP83811_POLARITY_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 				DP83811_SLEEP_MODE_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 				DP83811_OVERTEMP_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 				DP83811_OVERVOLTAGE_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 				DP83811_UNDERVOLTAGE_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		misr_status = phy_read(phydev, MII_DP83811_INT_STAT3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		if (misr_status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			return misr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		misr_status |= (DP83811_LPS_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 				DP83811_NO_FRAME_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				DP83811_POR_DONE_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		err = phy_write(phydev, MII_DP83811_INT_STAT3, misr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		err = phy_write(phydev, MII_DP83811_INT_STAT1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		err = phy_write(phydev, MII_DP83811_INT_STAT2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		err = phy_write(phydev, MII_DP83811_INT_STAT3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int dp83811_config_aneg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	int value, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		value = phy_read(phydev, MII_DP83811_SGMII_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		if (phydev->autoneg == AUTONEG_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 					(DP83811_SGMII_AUTO_NEG_EN | value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 				return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 					(~DP83811_SGMII_AUTO_NEG_EN & value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 				return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	return genphy_config_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int dp83811_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	int value, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	value = phy_read(phydev, MII_DP83811_SGMII_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 					(DP83811_SGMII_EN | value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 				(~DP83811_SGMII_EN & value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	value = DP83811_WOL_MAGIC_EN | DP83811_WOL_SECURE_ON | DP83811_WOL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	return phy_clear_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 				  value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int dp83811_phy_reset(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	err = phy_write(phydev, MII_DP83811_RESET_CTRL, DP83811_HW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int dp83811_suspend(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	if (!(value & DP83811_WOL_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		genphy_suspend(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int dp83811_resume(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	genphy_resume(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	phy_set_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			 DP83811_WOL_CLR_INDICATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static struct phy_driver dp83811_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		.phy_id = DP83TC811_PHY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		.phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		.name = "TI DP83TC811",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		/* PHY_BASIC_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		.config_init = dp83811_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		.config_aneg = dp83811_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		.soft_reset = dp83811_phy_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		.get_wol = dp83811_get_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		.set_wol = dp83811_set_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		.ack_interrupt = dp83811_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		.config_intr = dp83811_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		.suspend = dp83811_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		.resume = dp83811_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) module_phy_driver(dp83811_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static struct mdio_device_id __maybe_unused dp83811_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	{ DP83TC811_PHY_ID, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MODULE_DEVICE_TABLE(mdio, dp83811_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MODULE_DESCRIPTION("Texas Instruments DP83TC811 PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MODULE_LICENSE("GPL");