^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Driver for the Texas Instruments DP83867 PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2015 Texas Instruments Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/net/ti-dp83867.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DP83867_PHY_ID 0x2000a231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DP83867_DEVADDR 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MII_DP83867_PHYCTRL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MII_DP83867_PHYSTS 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MII_DP83867_MICR 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MII_DP83867_ISR 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DP83867_CFG2 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DP83867_CFG3 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DP83867_CTRL 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Extended Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DP83867_FLD_THR_CFG 0x002e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DP83867_CFG4 0x0031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DP83867_RGMIICTL 0x0032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DP83867_STRAP_STS1 0x006E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DP83867_STRAP_STS2 0x006f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DP83867_RGMIIDCTL 0x0086
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DP83867_RXFCFG 0x0134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DP83867_RXFPMD1 0x0136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DP83867_RXFPMD2 0x0137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DP83867_RXFPMD3 0x0138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DP83867_RXFSOP1 0x0139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DP83867_RXFSOP2 0x013A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DP83867_RXFSOP3 0x013B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DP83867_IO_MUX_CFG 0x0170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DP83867_SGMIICTL 0x00D3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DP83867_10M_SGMII_CFG 0x016F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DP83867_SW_RESET BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DP83867_SW_RESTART BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* MICR Interrupt bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* RGMIICTL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* SGMIICTL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DP83867_SGMII_TYPE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* RXFCFG bits*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DP83867_WOL_MAGIC_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DP83867_WOL_BCAST_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DP83867_WOL_UCAST_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DP83867_WOL_SEC_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DP83867_WOL_ENH_MAC BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* STRAP_STS1 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DP83867_STRAP_STS1_RESERVED BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* STRAP_STS2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DP83867_STRAP_STS2_STRAP_FLD BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* PHY CTRL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DP83867_PHYCR_RESERVED_MASK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* RGMIIDCTL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DP83867_RGMII_TX_CLK_DELAY_INV (DP83867_RGMII_TX_CLK_DELAY_MAX + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DP83867_RGMII_RX_CLK_DELAY_INV (DP83867_RGMII_RX_CLK_DELAY_MAX + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* IO_MUX_CFG bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* PHY STS bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DP83867_PHYSTS_1000 BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DP83867_PHYSTS_100 BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DP83867_PHYSTS_DUPLEX BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DP83867_PHYSTS_LINK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* CFG2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DP83867_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DP83867_DOWNSHIFT_1_COUNT_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DP83867_DOWNSHIFT_2_COUNT_VAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DP83867_DOWNSHIFT_4_COUNT_VAL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DP83867_DOWNSHIFT_8_COUNT_VAL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DP83867_DOWNSHIFT_1_COUNT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DP83867_DOWNSHIFT_2_COUNT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DP83867_DOWNSHIFT_4_COUNT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DP83867_DOWNSHIFT_8_COUNT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* CFG3 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DP83867_CFG3_INT_OE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* CFG4 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* FLD_THR_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DP83867_PORT_MIRROING_KEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DP83867_PORT_MIRROING_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DP83867_PORT_MIRROING_DIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct dp83867_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 rx_id_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 tx_id_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 tx_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 rx_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int io_impedance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int port_mirroring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bool rxctrl_strap_quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) bool set_clk_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 clk_output_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) bool sgmii_ref_clk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int dp83867_ack_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int err = phy_read(phydev, MII_DP83867_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int dp83867_set_wol(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct net_device *ndev = phydev->attached_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u16 val_rxcfg, val_micr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 *mac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) val_micr = phy_read(phydev, MII_DP83867_MICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) WAKE_BCAST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) val_rxcfg |= DP83867_WOL_ENH_MAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) val_micr |= MII_DP83867_MICR_WOL_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (wol->wolopts & WAKE_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) mac = (u8 *)ndev->dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (!is_valid_ether_addr(mac))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) (mac[1] << 8 | mac[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) (mac[3] << 8 | mac[2]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) (mac[5] << 8 | mac[4]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) val_rxcfg |= DP83867_WOL_MAGIC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (wol->wolopts & WAKE_MAGICSECURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) (wol->sopass[1] << 8) | wol->sopass[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) (wol->sopass[3] << 8) | wol->sopass[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) (wol->sopass[5] << 8) | wol->sopass[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) val_rxcfg |= DP83867_WOL_SEC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) val_rxcfg &= ~DP83867_WOL_SEC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (wol->wolopts & WAKE_UCAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) val_rxcfg |= DP83867_WOL_UCAST_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) val_rxcfg &= ~DP83867_WOL_UCAST_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (wol->wolopts & WAKE_BCAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) val_rxcfg |= DP83867_WOL_BCAST_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) val_rxcfg &= ~DP83867_WOL_BCAST_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) val_rxcfg &= ~DP83867_WOL_ENH_MAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) phy_write(phydev, MII_DP83867_MICR, val_micr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void dp83867_get_wol(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u16 value, sopass_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) WAKE_MAGICSECURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) wol->wolopts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (value & DP83867_WOL_UCAST_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) wol->wolopts |= WAKE_UCAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (value & DP83867_WOL_BCAST_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) wol->wolopts |= WAKE_BCAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (value & DP83867_WOL_MAGIC_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) wol->wolopts |= WAKE_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (value & DP83867_WOL_SEC_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) DP83867_RXFSOP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) wol->sopass[0] = (sopass_val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) wol->sopass[1] = (sopass_val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) DP83867_RXFSOP2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) wol->sopass[2] = (sopass_val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) wol->sopass[3] = (sopass_val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) DP83867_RXFSOP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) wol->sopass[4] = (sopass_val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) wol->sopass[5] = (sopass_val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) wol->wolopts |= WAKE_MAGICSECURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!(value & DP83867_WOL_ENH_MAC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) wol->wolopts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int dp83867_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int micr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) micr_status = phy_read(phydev, MII_DP83867_MICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (micr_status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return micr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) micr_status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) (MII_DP83867_MICR_AN_ERR_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MII_DP83867_MICR_SPEED_CHNG_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return phy_write(phydev, MII_DP83867_MICR, micr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) micr_status = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return phy_write(phydev, MII_DP83867_MICR, micr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int dp83867_read_status(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int status = phy_read(phydev, MII_DP83867_PHYSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = genphy_read_status(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (status & DP83867_PHYSTS_DUPLEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) phydev->duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) phydev->duplex = DUPLEX_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (status & DP83867_PHYSTS_1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) phydev->speed = SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) else if (status & DP83867_PHYSTS_100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) phydev->speed = SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) phydev->speed = SPEED_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int dp83867_get_downshift(struct phy_device *phydev, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int val, cnt, enable, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) val = phy_read(phydev, DP83867_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) switch (cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) case DP83867_DOWNSHIFT_1_COUNT_VAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) count = DP83867_DOWNSHIFT_1_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) case DP83867_DOWNSHIFT_2_COUNT_VAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) count = DP83867_DOWNSHIFT_2_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) case DP83867_DOWNSHIFT_4_COUNT_VAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) count = DP83867_DOWNSHIFT_4_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case DP83867_DOWNSHIFT_8_COUNT_VAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) count = DP83867_DOWNSHIFT_8_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int val, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (cnt > DP83867_DOWNSHIFT_8_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return -E2BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (!cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return phy_clear_bits(phydev, DP83867_CFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) DP83867_DOWNSHIFT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) switch (cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case DP83867_DOWNSHIFT_1_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) count = DP83867_DOWNSHIFT_1_COUNT_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case DP83867_DOWNSHIFT_2_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) count = DP83867_DOWNSHIFT_2_COUNT_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case DP83867_DOWNSHIFT_4_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) count = DP83867_DOWNSHIFT_4_COUNT_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case DP83867_DOWNSHIFT_8_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) count = DP83867_DOWNSHIFT_8_COUNT_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) phydev_err(phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) "Downshift count must be 1, 2, 4 or 8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) val = DP83867_DOWNSHIFT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return phy_modify(phydev, DP83867_CFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int dp83867_get_tunable(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct ethtool_tunable *tuna, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) switch (tuna->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case ETHTOOL_PHY_DOWNSHIFT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return dp83867_get_downshift(phydev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int dp83867_set_tunable(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct ethtool_tunable *tuna, const void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) switch (tuna->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case ETHTOOL_PHY_DOWNSHIFT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return dp83867_set_downshift(phydev, *(const u8 *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int dp83867_config_port_mirroring(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct dp83867_private *dp83867 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) (struct dp83867_private *)phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) DP83867_CFG4_PORT_MIRROR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) DP83867_CFG4_PORT_MIRROR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct dp83867_private *dp83867 = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Existing behavior was to use default pin strapping delay in rgmii
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * mode, but rgmii should have meant no delay. Warn existing users.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) DP83867_STRAP_STS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) phydev_warn(phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) txskew, rxskew);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* RX delay *must* be specified if internal delay of RX is used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* TX delay *must* be specified if internal delay of TX is used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #if IS_ENABLED(CONFIG_OF_MDIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int dp83867_of_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct dp83867_private *dp83867 = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct device *dev = &phydev->mdio.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct device_node *of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (!of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* Optional configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ret = of_property_read_u32(of_node, "ti,clk-output-sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) &dp83867->clk_output_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* If not set, keep default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dp83867->set_clk_output = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * DP83867_CLK_O_SEL_OFF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dp83867->clk_output_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (of_property_read_bool(of_node, "ti,max-output-impedance"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dp83867->io_impedance = -1; /* leave at default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) "ti,dp83867-rxctrl-strap-quirk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) "ti,sgmii-ref-clock-output-enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) &dp83867->rx_id_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) phydev_err(phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) "ti,rx-internal-delay value of %u out of range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dp83867->rx_id_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) &dp83867->tx_id_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) phydev_err(phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) "ti,tx-internal-delay value of %u out of range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dp83867->tx_id_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = of_property_read_u32(of_node, "ti,fifo-depth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) &dp83867->tx_fifo_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = of_property_read_u32(of_node, "tx-fifo-depth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) &dp83867->tx_fifo_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dp83867->tx_fifo_depth =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dp83867->tx_fifo_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ret = of_property_read_u32(of_node, "rx-fifo-depth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) &dp83867->rx_fifo_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dp83867->rx_fifo_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int dp83867_of_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #endif /* CONFIG_OF_MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static int dp83867_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct dp83867_private *dp83867;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (!dp83867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) phydev->priv = dp83867;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return dp83867_of_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static int dp83867_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct dp83867_private *dp83867 = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int ret, val, bs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u16 delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* Force speed optimization for the PHY even if it strapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) DP83867_DOWNSHIFT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ret = dp83867_verify_rgmii_cfg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (dp83867->rxctrl_strap_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) BIT(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (bs & DP83867_STRAP_STS2_STRAP_FLD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * be set to 0x2. This may causes the PHY link to be unstable -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * the default value 0x1 need to be restored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) DP83867_FLD_THR_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (phy_interface_is_rgmii(phydev) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) phydev->interface == PHY_INTERFACE_MODE_SGMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) val = phy_read(phydev, MII_DP83867_PHYCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) val |= (dp83867->tx_fifo_depth <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) val |= (dp83867->rx_fifo_depth <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (phy_interface_is_rgmii(phydev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) val = phy_read(phydev, MII_DP83867_PHYCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* The code below checks if "port mirroring" N/A MODE4 has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * enabled during power on bootstrap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * Such N/A mode enabled by mistake can put PHY IC in some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * internal testing mode and disable RGMII transmission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * In this particular case one needs to check STRAP_STS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * register's bit 11 (marked as RESERVED).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (bs & DP83867_STRAP_STS1_RESERVED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) val &= ~DP83867_PHYCR_RESERVED_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* If rgmii mode with no internal delay is selected, we do NOT use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * aligned mode as one might expect. Instead we use the PHY's default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * based on pin strapping. And the "mode 0" default is to *use*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * internal delay with a value of 7 (2.00 ns).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * Set up RGMII delays
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) val |= DP83867_RGMII_TX_CLK_DELAY_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) val |= DP83867_RGMII_RX_CLK_DELAY_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) delay |= dp83867->rx_id_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) delay |= dp83867->tx_id_delay <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) DP83867_RGMII_TX_CLK_DELAY_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* If specified, set io impedance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (dp83867->io_impedance >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dp83867->io_impedance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* For support SPEED_10 in SGMII mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * DP83867_10M_SGMII_RATE_ADAPT bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * has to be cleared by software. That
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * does not affect SPEED_100 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * SPEED_1000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) DP83867_10M_SGMII_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) DP83867_10M_SGMII_RATE_ADAPT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * are 01). That is not enough to finalize autoneg on some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * devices. Increase this timer duration to maximum 16ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) DP83867_CFG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) DP83867_CFG4_SGMII_ANEG_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* SGMII type is set to 4-wire mode by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * If we place appropriate property in dts (see above)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * switch on 6-wire mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (dp83867->sgmii_ref_clk_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) val |= DP83867_SGMII_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) val &= ~DP83867_SGMII_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) val = phy_read(phydev, DP83867_CFG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* Enable Interrupt output INT_OE in CFG3 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (phy_interrupt_is_valid(phydev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) val |= DP83867_CFG3_INT_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) phy_write(phydev, DP83867_CFG3, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dp83867_config_port_mirroring(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* Clock output selection if muxing property is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (dp83867->set_clk_output) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) val = dp83867->clk_output_sel <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static int dp83867_phy_reset(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return phy_modify(phydev, MII_DP83867_PHYCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) DP83867_PHYCR_FORCE_LINK_GOOD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static struct phy_driver dp83867_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .phy_id = DP83867_PHY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .name = "TI DP83867",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .probe = dp83867_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .config_init = dp83867_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .soft_reset = dp83867_phy_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .read_status = dp83867_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .get_tunable = dp83867_get_tunable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .set_tunable = dp83867_set_tunable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .get_wol = dp83867_get_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .set_wol = dp83867_set_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* IRQ related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .ack_interrupt = dp83867_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .config_intr = dp83867_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .resume = genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) module_phy_driver(dp83867_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) { DP83867_PHY_ID, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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