^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* dp83640_reg.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Generated by regen.tcl on Thu Feb 17 10:02:48 AM CET 2011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef HAVE_DP83640_REGISTERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define HAVE_DP83640_REGISTERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* #define PAGE0 0x0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define PHYCR2 0x001c /* PHY Control Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PAGE4 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PTP_CTL 0x0014 /* PTP Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PTP_TDR 0x0015 /* PTP Time Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PTP_STS 0x0016 /* PTP Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PTP_TSTS 0x0017 /* PTP Trigger Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PTP_RATEL 0x0018 /* PTP Rate Low Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PTP_RATEH 0x0019 /* PTP Rate High Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PTP_RDCKSUM 0x001a /* PTP Read Checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PTP_WRCKSUM 0x001b /* PTP Write Checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PTP_TXTS 0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PTP_RXTS 0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PTP_ESTS 0x001e /* PTP Event Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PTP_EDATA 0x001f /* PTP Event Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PAGE5 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PTP_TRIG 0x0014 /* PTP Trigger Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PTP_EVNT 0x0015 /* PTP Event Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PTP_TXCFG0 0x0016 /* PTP Transmit Configuration Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PTP_TXCFG1 0x0017 /* PTP Transmit Configuration Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PSF_CFG0 0x0018 /* PHY Status Frame Configuration Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PTP_RXCFG0 0x0019 /* PTP Receive Configuration Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PTP_RXCFG1 0x001a /* PTP Receive Configuration Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PTP_RXCFG2 0x001b /* PTP Receive Configuration Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PTP_RXCFG3 0x001c /* PTP Receive Configuration Register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PTP_RXCFG4 0x001d /* PTP Receive Configuration Register 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PTP_TRDL 0x001e /* PTP Temporary Rate Duration Low Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PTP_TRDH 0x001f /* PTP Temporary Rate Duration High Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PAGE6 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PTP_COC 0x0014 /* PTP Clock Output Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PSF_CFG1 0x0015 /* PHY Status Frame Configuration Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PSF_CFG2 0x0016 /* PHY Status Frame Configuration Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PSF_CFG3 0x0017 /* PHY Status Frame Configuration Register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PSF_CFG4 0x0018 /* PHY Status Frame Configuration Register 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PTP_SFDCFG 0x0019 /* PTP SFD Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PTP_INTCTL 0x001a /* PTP Interrupt Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PTP_CLKSRC 0x001b /* PTP Clock Source Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PTP_ETR 0x001c /* PTP Ethernet Type Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PTP_OFF 0x001d /* PTP Offset Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PTP_GPIOMON 0x001e /* PTP GPIO Monitor Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PTP_RXHASH 0x001f /* PTP Receive Hash Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Bit definitions for the PHYCR2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BC_WRITE (1<<11) /* Broadcast Write Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Bit definitions for the PTP_CTL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TRIG_SEL_SHIFT (10) /* PTP Trigger Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TRIG_SEL_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TRIG_DIS (1<<9) /* Disable PTP Trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TRIG_EN (1<<8) /* Enable PTP Trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TRIG_READ (1<<7) /* Read PTP Trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TRIG_LOAD (1<<6) /* Load PTP Trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PTP_RD_CLK (1<<5) /* Read PTP Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PTP_LOAD_CLK (1<<4) /* Load PTP Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PTP_STEP_CLK (1<<3) /* Step PTP Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PTP_ENABLE (1<<2) /* Enable PTP Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PTP_DISABLE (1<<1) /* Disable PTP Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PTP_RESET (1<<0) /* Reset PTP Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Bit definitions for the PTP_STS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TXTS_RDY (1<<11) /* Transmit Timestamp Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RXTS_RDY (1<<10) /* Receive Timestamp Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TRIG_DONE (1<<9) /* PTP Trigger Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define EVENT_RDY (1<<8) /* PTP Event Timestamp Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TXTS_IE (1<<3) /* Transmit Timestamp Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RXTS_IE (1<<2) /* Receive Timestamp Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TRIG_IE (1<<1) /* Trigger Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define EVENT_IE (1<<0) /* Event Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Bit definitions for the PTP_TSTS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TRIG7_ERROR (1<<15) /* Trigger 7 Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TRIG7_ACTIVE (1<<14) /* Trigger 7 Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TRIG6_ERROR (1<<13) /* Trigger 6 Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TRIG6_ACTIVE (1<<12) /* Trigger 6 Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TRIG5_ERROR (1<<11) /* Trigger 5 Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TRIG5_ACTIVE (1<<10) /* Trigger 5 Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TRIG4_ERROR (1<<9) /* Trigger 4 Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TRIG4_ACTIVE (1<<8) /* Trigger 4 Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TRIG3_ERROR (1<<7) /* Trigger 3 Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TRIG3_ACTIVE (1<<6) /* Trigger 3 Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TRIG2_ERROR (1<<5) /* Trigger 2 Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TRIG2_ACTIVE (1<<4) /* Trigger 2 Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TRIG1_ERROR (1<<3) /* Trigger 1 Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TRIG1_ACTIVE (1<<2) /* Trigger 1 Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TRIG0_ERROR (1<<1) /* Trigger 0 Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TRIG0_ACTIVE (1<<0) /* Trigger 0 Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Bit definitions for the PTP_RATEH register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PTP_RATE_DIR (1<<15) /* PTP Rate Direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PTP_TMP_RATE (1<<14) /* PTP Temporary Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PTP_RATE_HI_SHIFT (0) /* PTP Rate High 10-bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PTP_RATE_HI_MASK (0x3ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Bit definitions for the PTP_ESTS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define EVNTS_MISSED_SHIFT (8) /* Indicates number of events missed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define EVNTS_MISSED_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define EVNT_TS_LEN_SHIFT (6) /* Indicates length of the Timestamp field in 16-bit words minus 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define EVNT_TS_LEN_MASK (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define EVNT_RF (1<<5) /* Indicates whether the event is a rise or falling event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define EVNT_NUM_SHIFT (2) /* Indicates Event Timestamp Unit which detected an event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define EVNT_NUM_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MULT_EVNT (1<<1) /* Indicates multiple events were detected at the same time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define EVENT_DET (1<<0) /* PTP Event Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Bit definitions for the PTP_EDATA register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define E7_RISE (1<<15) /* Indicates direction of Event 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define E7_DET (1<<14) /* Indicates Event 7 detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define E6_RISE (1<<13) /* Indicates direction of Event 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define E6_DET (1<<12) /* Indicates Event 6 detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define E5_RISE (1<<11) /* Indicates direction of Event 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define E5_DET (1<<10) /* Indicates Event 5 detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define E4_RISE (1<<9) /* Indicates direction of Event 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define E4_DET (1<<8) /* Indicates Event 4 detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define E3_RISE (1<<7) /* Indicates direction of Event 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define E3_DET (1<<6) /* Indicates Event 3 detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define E2_RISE (1<<5) /* Indicates direction of Event 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define E2_DET (1<<4) /* Indicates Event 2 detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define E1_RISE (1<<3) /* Indicates direction of Event 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define E1_DET (1<<2) /* Indicates Event 1 detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define E0_RISE (1<<1) /* Indicates direction of Event 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define E0_DET (1<<0) /* Indicates Event 0 detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Bit definitions for the PTP_TRIG register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TRIG_PULSE (1<<15) /* generate a Pulse rather than a single edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TRIG_PER (1<<14) /* generate a periodic signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TRIG_IF_LATE (1<<13) /* trigger immediately if already past */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TRIG_NOTIFY (1<<12) /* Trigger Notification Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TRIG_GPIO_SHIFT (8) /* Trigger GPIO Connection, value 1-12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TRIG_GPIO_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TRIG_TOGGLE (1<<7) /* Trigger Toggle Mode Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TRIG_CSEL_SHIFT (1) /* Trigger Configuration Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TRIG_CSEL_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TRIG_WR (1<<0) /* Trigger Configuration Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Bit definitions for the PTP_EVNT register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define EVNT_RISE (1<<14) /* Event Rise Detect Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define EVNT_FALL (1<<13) /* Event Fall Detect Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define EVNT_SINGLE (1<<12) /* enable single event capture operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define EVNT_GPIO_SHIFT (8) /* Event GPIO Connection, value 1-12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define EVNT_GPIO_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define EVNT_SEL_SHIFT (1) /* Event Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define EVNT_SEL_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define EVNT_WR (1<<0) /* Event Configuration Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Bit definitions for the PTP_TXCFG0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SYNC_1STEP (1<<15) /* insert timestamp into transmit Sync Messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DR_INSERT (1<<13) /* Insert Delay_Req Timestamp in Delay_Resp (dangerous) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define NTP_TS_EN (1<<12) /* Enable Timestamping of NTP Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IGNORE_2STEP (1<<11) /* Ignore Two_Step flag for One-Step operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CRC_1STEP (1<<10) /* Disable checking of CRC for One-Step operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CHK_1STEP (1<<9) /* Enable UDP Checksum correction for One-Step Operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IP1588_EN (1<<8) /* Enable IEEE 1588 defined IP address filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TX_L2_EN (1<<7) /* Layer2 Timestamp Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TX_PTP_VER_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TX_TS_EN (1<<0) /* Transmit Timestamp Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Bit definitions for the PTP_TXCFG1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define BYTE0_MASK_MASK (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define BYTE0_DATA_MASK (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Bit definitions for the PSF_CFG0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MAC_SRC_ADD_SHIFT (11) /* Status Frame Mac Source Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MAC_SRC_ADD_MASK (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MIN_PRE_SHIFT (8) /* Status Frame Minimum Preamble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MIN_PRE_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PSF_ENDIAN (1<<7) /* Status Frame Endian Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PSF_IPV4 (1<<6) /* Status Frame IPv4 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PSF_PCF_RD (1<<5) /* Control Frame Read PHY Status Frame Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PSF_ERR_EN (1<<4) /* Error PHY Status Frame Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PSF_TXTS_EN (1<<3) /* Transmit Timestamp PHY Status Frame Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PSF_RXTS_EN (1<<2) /* Receive Timestamp PHY Status Frame Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PSF_TRIG_EN (1<<1) /* Trigger PHY Status Frame Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PSF_EVNT_EN (1<<0) /* Event PHY Status Frame Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Bit definitions for the PTP_RXCFG0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DOMAIN_EN (1<<15) /* Domain Match Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ALT_MAST_DIS (1<<14) /* Alternate Master Timestamp Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define USER_IP_SEL (1<<13) /* Selects portion of IP address accessible thru PTP_RXCFG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define USER_IP_EN (1<<12) /* Enable User-programmed IP address filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define RX_SLAVE (1<<11) /* Receive Slave Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IP1588_EN_SHIFT (8) /* Enable IEEE 1588 defined IP address filters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IP1588_EN_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define RX_L2_EN (1<<7) /* Layer2 Timestamp Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define RX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define RX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define RX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define RX_PTP_VER_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define RX_TS_EN (1<<0) /* Receive Timestamp Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Bit definitions for the PTP_RXCFG1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define BYTE0_MASK_MASK (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define BYTE0_DATA_MASK (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Bit definitions for the PTP_RXCFG3 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TS_MIN_IFG_SHIFT (12) /* Minimum Inter-frame Gap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TS_MIN_IFG_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define ACC_UDP (1<<11) /* Record Timestamp if UDP Checksum Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define ACC_CRC (1<<10) /* Record Timestamp if CRC Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TS_APPEND (1<<9) /* Append Timestamp for L2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TS_INSERT (1<<8) /* Enable Timestamp Insertion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define PTP_DOMAIN_SHIFT (0) /* PTP Message domainNumber field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define PTP_DOMAIN_MASK (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Bit definitions for the PTP_RXCFG4 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IPV4_UDP_MOD (1<<15) /* Enable IPV4 UDP Modification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TS_SEC_EN (1<<14) /* Enable Timestamp Seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TS_SEC_LEN_SHIFT (12) /* Inserted Timestamp Seconds Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TS_SEC_LEN_MASK (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define RXTS_NS_OFF_SHIFT (6) /* Receive Timestamp Nanoseconds offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define RXTS_NS_OFF_MASK (0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define RXTS_SEC_OFF_SHIFT (0) /* Receive Timestamp Seconds offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define RXTS_SEC_OFF_MASK (0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Bit definitions for the PTP_COC register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define PTP_CLKOUT_EN (1<<15) /* PTP Clock Output Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PTP_CLKOUT_SEL (1<<14) /* PTP Clock Output Source Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PTP_CLKOUT_SPEEDSEL (1<<13) /* PTP Clock Output I/O Speed Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PTP_CLKDIV_SHIFT (0) /* PTP Clock Divide-by Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PTP_CLKDIV_MASK (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Bit definitions for the PSF_CFG1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define PTPRESERVED_SHIFT (12) /* PTP v2 reserved field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define PTPRESERVED_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define VERSIONPTP_SHIFT (8) /* PTP v2 versionPTP field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define VERSIONPTP_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define TRANSPORT_SPECIFIC_SHIFT (4) /* PTP v2 Header transportSpecific field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TRANSPORT_SPECIFIC_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MESSAGETYPE_SHIFT (0) /* PTP v2 messageType field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MESSAGETYPE_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Bit definitions for the PTP_SFDCFG register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define TX_SFD_GPIO_SHIFT (4) /* TX SFD GPIO Select, value 1-12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TX_SFD_GPIO_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define RX_SFD_GPIO_SHIFT (0) /* RX SFD GPIO Select, value 1-12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define RX_SFD_GPIO_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Bit definitions for the PTP_INTCTL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define PTP_INT_GPIO_SHIFT (0) /* PTP Interrupt GPIO Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define PTP_INT_GPIO_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Bit definitions for the PTP_CLKSRC register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CLK_SRC_SHIFT (14) /* PTP Clock Source Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CLK_SRC_MASK (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CLK_SRC_PER_SHIFT (0) /* PTP Clock Source Period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CLK_SRC_PER_MASK (0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Bit definitions for the PTP_OFF register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define PTP_OFFSET_SHIFT (0) /* PTP Message offset from preceding header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define PTP_OFFSET_MASK (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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