^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the National Semiconductor DP83640 PHYTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 OMICRON electronics GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/net_tstamp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/if_vlan.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/ptp_classify.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/ptp_clock_kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "dp83640_reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DP83640_PHY_ID 0x20005ce1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PAGESEL 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MAX_RXTS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define N_EXT_TS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define N_PER_OUT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PSF_PTPVER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PSF_EVNT 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PSF_RX 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PSF_TX 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EXT_EVENT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CAL_EVENT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CAL_TRIGGER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DP83640_N_PINS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MII_DP83640_MICR 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MII_DP83640_MISR 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MII_DP83640_MICR_OE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MII_DP83640_MICR_IE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MII_DP83640_MISR_RHF_INT_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MII_DP83640_MISR_FHF_INT_EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MII_DP83640_MISR_ANC_INT_EN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MII_DP83640_MISR_DUP_INT_EN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MII_DP83640_MISR_SPD_INT_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MII_DP83640_MISR_LINK_INT_EN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MII_DP83640_MISR_ED_INT_EN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MII_DP83640_MISR_LQ_INT_EN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* phyter seems to miss the mark by 16 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ADJTIME_FIX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SKB_TIMESTAMP_TIMEOUT 2 /* jiffies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #if defined(__BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ENDIAN_FLAG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #elif defined(__LITTLE_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ENDIAN_FLAG PSF_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct dp83640_skb_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int ptp_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct phy_rxts {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u16 ns_lo; /* ns[15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u16 ns_hi; /* overflow[1:0], ns[29:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u16 sec_lo; /* sec[15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u16 sec_hi; /* sec[31:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u16 seqid; /* sequenceId[15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u16 msgtype; /* messageType[3:0], hash[11:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct phy_txts {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u16 ns_lo; /* ns[15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u16 ns_hi; /* overflow[1:0], ns[29:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u16 sec_lo; /* sec[15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u16 sec_hi; /* sec[31:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct rxts {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned long tmo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u64 ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u16 seqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 msgtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u16 hash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct dp83640_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct dp83640_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct dp83640_clock *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct phy_device *phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct mii_timestamper mii_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct delayed_work ts_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int hwts_tx_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int hwts_rx_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int layer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* remember state of cfg0 during calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int cfg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* remember the last event time stamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct phy_txts edata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* list of rx timestamps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct list_head rxts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct list_head rxpool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct rxts rx_pool_data[MAX_RXTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* protects above three fields from concurrent access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) spinlock_t rx_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* queues of incoming and outgoing packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct sk_buff_head rx_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct sk_buff_head tx_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct dp83640_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* keeps the instance in the 'phyter_clocks' list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* we create one clock instance per MII bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct mii_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* protects extended registers from concurrent access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct mutex extreg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* remembers which page was last selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* our advertised capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct ptp_clock_info caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* protects the three fields below from concurrent access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct mutex clock_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* the one phyter from which we shall read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct dp83640_private *chosen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* list of the other attached phyters, not chosen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct list_head phylist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* reference to our PTP hardware clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct ptp_clock *ptp_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* globals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) CALIBRATE_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PEROUT_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) EXTTS0_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) EXTTS1_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) EXTTS2_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) EXTTS3_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) EXTTS4_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) EXTTS5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) GPIO_TABLE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int chosen_phy = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static ushort gpio_tab[GPIO_TABLE_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 1, 2, 3, 4, 8, 9, 10, 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) module_param(chosen_phy, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) module_param_array(gpio_tab, ushort, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MODULE_PARM_DESC(chosen_phy, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "The address of the PHY to use for the ancillary clock features");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MODULE_PARM_DESC(gpio_tab, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int i, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) for (i = 0; i < DP83640_N_PINS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pd[i].index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) for (i = 0; i < GPIO_TABLE_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) index = gpio_tab[CALIBRATE_GPIO] - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pd[index].func = PTP_PF_PHYSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pd[index].chan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) index = gpio_tab[PEROUT_GPIO] - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pd[index].func = PTP_PF_PEROUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pd[index].chan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) index = gpio_tab[i] - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pd[index].func = PTP_PF_EXTTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pd[index].chan = i - EXTTS0_GPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* a list of clocks and a mutex to protect it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static LIST_HEAD(phyter_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static DEFINE_MUTEX(phyter_clocks_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void rx_timestamp_work(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* extended register access functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define BROADCAST_ADDR 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static inline int broadcast_write(struct phy_device *phydev, u32 regnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Caller must hold extreg_lock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int ext_read(struct phy_device *phydev, int page, u32 regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct dp83640_private *dp83640 = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (dp83640->clock->page != page) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) broadcast_write(phydev, PAGESEL, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dp83640->clock->page = page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) val = phy_read(phydev, regnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Caller must hold extreg_lock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void ext_write(int broadcast, struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int page, u32 regnum, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct dp83640_private *dp83640 = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (dp83640->clock->page != page) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) broadcast_write(phydev, PAGESEL, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dp83640->clock->page = page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (broadcast)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) broadcast_write(phydev, regnum, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) phy_write(phydev, regnum, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Caller must hold extreg_lock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int tdr_write(int bc, struct phy_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) const struct timespec64 *ts, u16 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* convert phy timestamps into driver timestamps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) sec = p->sec_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) sec |= p->sec_hi << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) rxts->ns = p->ns_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) rxts->ns |= (p->ns_hi & 0x3fff) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) rxts->ns += ((u64)sec) * 1000000000ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) rxts->seqid = p->seqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) rxts->msgtype = (p->msgtype >> 12) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) rxts->hash = p->msgtype & 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static u64 phy2txts(struct phy_txts *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u64 ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) sec = p->sec_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) sec |= p->sec_hi << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ns = p->ns_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ns |= (p->ns_hi & 0x3fff) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ns += ((u64)sec) * 1000000000ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int periodic_output(struct dp83640_clock *clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct ptp_clock_request *clkreq, bool on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct dp83640_private *dp83640 = clock->chosen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct phy_device *phydev = dp83640->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 sec, nsec, pwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u16 gpio, ptp_trig, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (gpio < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) gpio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ptp_trig = TRIG_WR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) TRIG_PER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) TRIG_PULSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) val |= TRIG_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) mutex_lock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ext_write(0, phydev, PAGE4, PTP_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) mutex_unlock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) sec = clkreq->perout.start.sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) nsec = clkreq->perout.start.nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pwidth = clkreq->perout.period.sec * 1000000000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pwidth += clkreq->perout.period.nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pwidth /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) mutex_lock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /*load trigger*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) val |= TRIG_LOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ext_write(0, phydev, PAGE4, PTP_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* Triggers 0 and 1 has programmable pulsewidth2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (trigger < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*enable trigger*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) val &= ~TRIG_LOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) val |= TRIG_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ext_write(0, phydev, PAGE4, PTP_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) mutex_unlock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* ptp clock methods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static int ptp_dp83640_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct dp83640_clock *clock =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) container_of(ptp, struct dp83640_clock, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct phy_device *phydev = clock->chosen->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u64 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int neg_adj = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u16 hi, lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (scaled_ppm < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) neg_adj = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) scaled_ppm = -scaled_ppm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) rate = scaled_ppm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) rate <<= 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) rate = div_u64(rate, 15625);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) hi = (rate >> 16) & PTP_RATE_HI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (neg_adj)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) hi |= PTP_RATE_DIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) lo = rate & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) mutex_lock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) mutex_unlock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct dp83640_clock *clock =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) container_of(ptp, struct dp83640_clock, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct phy_device *phydev = clock->chosen->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct timespec64 ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) delta += ADJTIME_FIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ts = ns_to_timespec64(delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mutex_lock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) mutex_unlock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int ptp_dp83640_gettime(struct ptp_clock_info *ptp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct timespec64 *ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct dp83640_clock *clock =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) container_of(ptp, struct dp83640_clock, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct phy_device *phydev = clock->chosen->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned int val[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) mutex_lock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mutex_unlock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ts->tv_nsec = val[0] | (val[1] << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ts->tv_sec = val[2] | (val[3] << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) const struct timespec64 *ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct dp83640_clock *clock =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) container_of(ptp, struct dp83640_clock, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct phy_device *phydev = clock->chosen->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) mutex_lock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) mutex_unlock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct ptp_clock_request *rq, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct dp83640_clock *clock =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) container_of(ptp, struct dp83640_clock, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct phy_device *phydev = clock->chosen->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u16 evnt, event_num, gpio_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) switch (rq->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case PTP_CLK_REQ_EXTTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Reject requests with unsupported flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PTP_RISING_EDGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) PTP_FALLING_EDGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PTP_STRICT_FLAGS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Reject requests to enable time stamping on both edges. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) (rq->extts.flags & PTP_ENABLE_FEATURE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) (rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) index = rq->extts.index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (index >= N_EXT_TS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) event_num = EXT_EVENT + index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) gpio_num = 1 + ptp_find_pin(clock->ptp_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) PTP_PF_EXTTS, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (gpio_num < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (rq->extts.flags & PTP_FALLING_EDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) evnt |= EVNT_FALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) evnt |= EVNT_RISE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) mutex_lock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) mutex_unlock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) case PTP_CLK_REQ_PEROUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Reject requests with unsupported flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (rq->perout.flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (rq->perout.index >= N_PER_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return periodic_output(clock, rq, on, rq->perout.index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) enum ptp_pin_function func, unsigned int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct dp83640_clock *clock =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) container_of(ptp, struct dp83640_clock, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) !list_empty(&clock->phylist))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (func == PTP_PF_PHYSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static void enable_status_frames(struct phy_device *phydev, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct dp83640_private *dp83640 = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct dp83640_clock *clock = dp83640->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u16 cfg0 = 0, ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) mutex_lock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mutex_unlock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (!phydev->attached_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) phydev_warn(phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) "expected to find an attached netdevice\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (dev_mc_add(phydev->attached_dev, status_frame_dst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) phydev_warn(phydev, "failed to add mc address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (dev_mc_del(phydev->attached_dev, status_frame_dst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) phydev_warn(phydev, "failed to delete mc address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static bool is_status_frame(struct sk_buff *skb, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct ethhdr *h = eth_hdr(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (PTP_CLASS_V2_L2 == type &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int expired(struct rxts *rxts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return time_after(jiffies, rxts->tmo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* Caller must hold rx_lock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static void prune_rx_ts(struct dp83640_private *dp83640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct list_head *this, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct rxts *rxts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) list_for_each_safe(this, next, &dp83640->rxts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) rxts = list_entry(this, struct rxts, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (expired(rxts)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) list_del_init(&rxts->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) list_add(&rxts->list, &dp83640->rxpool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* synchronize the phyters so they act as one clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) phy_write(phydev, PAGESEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) val = phy_read(phydev, PHYCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) val |= BC_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) val &= ~BC_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) phy_write(phydev, PHYCR2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) phy_write(phydev, PAGESEL, init_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static void recalibrate(struct dp83640_clock *clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) s64 now, diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct phy_txts event_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct timespec64 ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct list_head *this;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct dp83640_private *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct phy_device *master = clock->chosen->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) trigger = CAL_TRIGGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) cal_gpio = 1 + ptp_find_pin_unlocked(clock->ptp_clock, PTP_PF_PHYSYNC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (cal_gpio < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) pr_err("PHY calibration pin not available - PHY is not calibrated.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) mutex_lock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * enable broadcast, disable status frames, enable ptp clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) list_for_each(this, &clock->phylist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) tmp = list_entry(this, struct dp83640_private, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) enable_broadcast(tmp->phydev, clock->page, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) enable_broadcast(master, clock->page, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) cfg0 = ext_read(master, PAGE5, PSF_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ext_write(0, master, PAGE5, PSF_CFG0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * enable an event timestamp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) list_for_each(this, &clock->phylist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) tmp = list_entry(this, struct dp83640_private, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ext_write(0, master, PAGE5, PTP_EVNT, evnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * configure a trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* load trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) val |= TRIG_LOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ext_write(0, master, PAGE4, PTP_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* enable trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) val &= ~TRIG_LOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) val |= TRIG_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ext_write(0, master, PAGE4, PTP_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* disable trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) val |= TRIG_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ext_write(0, master, PAGE4, PTP_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * read out and correct offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) val = ext_read(master, PAGE4, PTP_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) phydev_info(master, "master PTP_STS 0x%04hx\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) val = ext_read(master, PAGE4, PTP_ESTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) phydev_info(master, "master PTP_ESTS 0x%04hx\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) now = phy2txts(&event_ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) list_for_each(this, &clock->phylist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) tmp = list_entry(this, struct dp83640_private, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) val = ext_read(tmp->phydev, PAGE4, PTP_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) phydev_info(tmp->phydev, "slave PTP_STS 0x%04hx\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) phydev_info(tmp->phydev, "slave PTP_ESTS 0x%04hx\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) diff = now - (s64) phy2txts(&event_ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) diff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) diff += ADJTIME_FIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ts = ns_to_timespec64(diff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * restore status frames
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) list_for_each(this, &clock->phylist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) tmp = list_entry(this, struct dp83640_private, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) mutex_unlock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* time stamping methods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static inline u16 exts_chan_to_edata(int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return 1 << ((ch + EXT_EVENT) * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static int decode_evnt(struct dp83640_private *dp83640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) void *data, int len, u16 ests)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct phy_txts *phy_txts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct ptp_clock_event event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) int i, parsed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) u16 ext_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* calculate length of the event timestamp status message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (ests & MULT_EVNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) parsed = (words + 2) * sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) parsed = (words + 1) * sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* check if enough data is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (len < parsed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (ests & MULT_EVNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ext_status = *(u16 *) data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) data += sizeof(ext_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) phy_txts = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) switch (words) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dp83640->edata.sec_hi = phy_txts->sec_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) dp83640->edata.sec_lo = phy_txts->sec_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dp83640->edata.ns_hi = phy_txts->ns_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) dp83640->edata.ns_lo = phy_txts->ns_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (!ext_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ext_status = exts_chan_to_edata(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) event.type = PTP_CLOCK_EXTTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) event.timestamp = phy2txts(&dp83640->edata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* Compensate for input path and synchronization delays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) event.timestamp -= 35;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) for (i = 0; i < N_EXT_TS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (ext_status & exts_chan_to_edata(i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) event.index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ptp_clock_event(dp83640->clock->ptp_clock, &event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return parsed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define DP83640_PACKET_HASH_LEN 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct ptp_header *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u8 msgtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) u16 seqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) u16 hash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) hdr = ptp_parse_header(skb, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (!hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) msgtype = ptp_get_msgtype(hdr, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (rxts->msgtype != (msgtype & 0xf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) seqid = be16_to_cpu(hdr->sequence_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (rxts->seqid != seqid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) hash = ether_crc(DP83640_PACKET_HASH_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) (unsigned char *)&hdr->source_port_identity) >> 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (rxts->hash != hash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static void decode_rxts(struct dp83640_private *dp83640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct phy_rxts *phy_rxts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct rxts *rxts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct skb_shared_hwtstamps *shhwtstamps = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) u8 overflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) overflow = (phy_rxts->ns_hi >> 14) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (overflow)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) pr_debug("rx timestamp queue overflow, count %d\n", overflow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) spin_lock_irqsave(&dp83640->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) prune_rx_ts(dp83640);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (list_empty(&dp83640->rxpool)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) pr_debug("rx timestamp pool is empty\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) list_del_init(&rxts->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) phy2rxts(phy_rxts, rxts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) spin_lock(&dp83640->rx_queue.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) skb_queue_walk(&dp83640->rx_queue, skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct dp83640_skb_info *skb_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) skb_info = (struct dp83640_skb_info *)skb->cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (match(skb, skb_info->ptp_type, rxts)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) __skb_unlink(skb, &dp83640->rx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) shhwtstamps = skb_hwtstamps(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) memset(shhwtstamps, 0, sizeof(*shhwtstamps));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) list_add(&rxts->list, &dp83640->rxpool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) spin_unlock(&dp83640->rx_queue.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (!shhwtstamps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) list_add_tail(&rxts->list, &dp83640->rxts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) spin_unlock_irqrestore(&dp83640->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (shhwtstamps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) netif_rx_ni(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static void decode_txts(struct dp83640_private *dp83640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct phy_txts *phy_txts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct skb_shared_hwtstamps shhwtstamps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct dp83640_skb_info *skb_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) u8 overflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) u64 ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* We must already have the skb that triggered this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) again:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) skb = skb_dequeue(&dp83640->tx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) pr_debug("have timestamp but tx_queue empty\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) overflow = (phy_txts->ns_hi >> 14) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (overflow) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) pr_debug("tx timestamp queue overflow, count %d\n", overflow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) while (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) skb = skb_dequeue(&dp83640->tx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) skb_info = (struct dp83640_skb_info *)skb->cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (time_after(jiffies, skb_info->tmo)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) goto again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ns = phy2txts(phy_txts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) memset(&shhwtstamps, 0, sizeof(shhwtstamps));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) shhwtstamps.hwtstamp = ns_to_ktime(ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) skb_complete_tx_timestamp(skb, &shhwtstamps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static void decode_status_frame(struct dp83640_private *dp83640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct phy_rxts *phy_rxts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct phy_txts *phy_txts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) u8 *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) int len, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) u16 ests, type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ptr = skb->data + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) type = *(u16 *)ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ests = type & 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) type = type & 0xf000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) len -= sizeof(type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) ptr += sizeof(type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) phy_rxts = (struct phy_rxts *) ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) decode_rxts(dp83640, phy_rxts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) size = sizeof(*phy_rxts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) phy_txts = (struct phy_txts *) ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) decode_txts(dp83640, phy_txts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) size = sizeof(*phy_txts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) } else if (PSF_EVNT == type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) size = decode_evnt(dp83640, ptr, len, ests);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ptr += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static int is_sync(struct sk_buff *skb, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct ptp_header *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) u8 msgtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) hdr = ptp_parse_header(skb, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (!hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) msgtype = ptp_get_msgtype(hdr, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return (msgtype & 0xf) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static void dp83640_free_clocks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct dp83640_clock *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct list_head *this, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) mutex_lock(&phyter_clocks_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) list_for_each_safe(this, next, &phyter_clocks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) clock = list_entry(this, struct dp83640_clock, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (!list_empty(&clock->phylist)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) pr_warn("phy list non-empty while unloading\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) list_del(&clock->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) mutex_destroy(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) mutex_destroy(&clock->clock_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) put_device(&clock->bus->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) kfree(clock->caps.pin_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) kfree(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) mutex_unlock(&phyter_clocks_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) INIT_LIST_HEAD(&clock->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) clock->bus = bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) mutex_init(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) mutex_init(&clock->clock_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) INIT_LIST_HEAD(&clock->phylist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) clock->caps.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) sprintf(clock->caps.name, "dp83640 timer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) clock->caps.max_adj = 1953124;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) clock->caps.n_alarm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) clock->caps.n_ext_ts = N_EXT_TS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) clock->caps.n_per_out = N_PER_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) clock->caps.n_pins = DP83640_N_PINS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) clock->caps.pps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) clock->caps.adjfine = ptp_dp83640_adjfine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) clock->caps.adjtime = ptp_dp83640_adjtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) clock->caps.gettime64 = ptp_dp83640_gettime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) clock->caps.settime64 = ptp_dp83640_settime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) clock->caps.enable = ptp_dp83640_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) clock->caps.verify = ptp_dp83640_verify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * Convert the module param defaults into a dynamic pin configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) dp83640_gpio_defaults(clock->caps.pin_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * Get a reference to this bus instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) get_device(&bus->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static int choose_this_phy(struct dp83640_clock *clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (chosen_phy == -1 && !clock->chosen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (chosen_phy == phydev->mdio.addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) mutex_lock(&clock->clock_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * Look up and lock a clock by bus instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * If there is no clock for this bus, then create it first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct dp83640_clock *clock = NULL, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct list_head *this;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) mutex_lock(&phyter_clocks_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) list_for_each(this, &phyter_clocks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) tmp = list_entry(this, struct dp83640_clock, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (tmp->bus == bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) clock = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (!clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) clock->caps.pin_config = kcalloc(DP83640_N_PINS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) sizeof(struct ptp_pin_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (!clock->caps.pin_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) kfree(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) clock = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) dp83640_clock_init(clock, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) list_add_tail(&clock->list, &phyter_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) mutex_unlock(&phyter_clocks_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return dp83640_clock_get(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static void dp83640_clock_put(struct dp83640_clock *clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) mutex_unlock(&clock->clock_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static int dp83640_soft_reset(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) ret = genphy_soft_reset(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /* From DP83640 datasheet: "Software driver code must wait 3 us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * following a software reset before allowing further serial MII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * operations with the DP83640."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) udelay(10); /* Taking udelay inaccuracy into account */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static int dp83640_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct dp83640_private *dp83640 = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct dp83640_clock *clock = dp83640->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (clock->chosen && !list_empty(&clock->phylist))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) recalibrate(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) mutex_lock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) enable_broadcast(phydev, clock->page, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) mutex_unlock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) enable_status_frames(phydev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) mutex_lock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) mutex_unlock(&clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static int dp83640_ack_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) int err = phy_read(phydev, MII_DP83640_MISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static int dp83640_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) int micr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) int misr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) misr = phy_read(phydev, MII_DP83640_MISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (misr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) return misr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) misr |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) (MII_DP83640_MISR_ANC_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) MII_DP83640_MISR_DUP_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) MII_DP83640_MISR_SPD_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) MII_DP83640_MISR_LINK_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) err = phy_write(phydev, MII_DP83640_MISR, misr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) micr = phy_read(phydev, MII_DP83640_MICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (micr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return micr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) micr |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) (MII_DP83640_MICR_OE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) MII_DP83640_MICR_IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return phy_write(phydev, MII_DP83640_MICR, micr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) micr = phy_read(phydev, MII_DP83640_MICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (micr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return micr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) micr &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ~(MII_DP83640_MICR_OE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) MII_DP83640_MICR_IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) err = phy_write(phydev, MII_DP83640_MICR, micr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) misr = phy_read(phydev, MII_DP83640_MISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (misr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) return misr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) misr &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) ~(MII_DP83640_MISR_ANC_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) MII_DP83640_MISR_DUP_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) MII_DP83640_MISR_SPD_INT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) MII_DP83640_MISR_LINK_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return phy_write(phydev, MII_DP83640_MISR, misr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static int dp83640_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct dp83640_private *dp83640 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) container_of(mii_ts, struct dp83640_private, mii_ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct hwtstamp_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) u16 txcfg0, rxcfg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (cfg.flags) /* reserved for future extensions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) dp83640->hwts_tx_en = cfg.tx_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) switch (cfg.rx_filter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) case HWTSTAMP_FILTER_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) dp83640->hwts_rx_en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) dp83640->layer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) dp83640->version = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) dp83640->hwts_rx_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) dp83640->layer = PTP_CLASS_L4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) dp83640->version = PTP_CLASS_V1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) dp83640->hwts_rx_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) dp83640->layer = PTP_CLASS_L4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) dp83640->version = PTP_CLASS_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) dp83640->hwts_rx_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) dp83640->layer = PTP_CLASS_L2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) dp83640->version = PTP_CLASS_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) case HWTSTAMP_FILTER_PTP_V2_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) case HWTSTAMP_FILTER_PTP_V2_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) dp83640->hwts_rx_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) dp83640->version = PTP_CLASS_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (dp83640->layer & PTP_CLASS_L2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) txcfg0 |= TX_L2_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) rxcfg0 |= RX_L2_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (dp83640->layer & PTP_CLASS_L4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (dp83640->hwts_tx_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) txcfg0 |= TX_TS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) txcfg0 |= SYNC_1STEP | CHK_1STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (dp83640->hwts_rx_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) rxcfg0 |= RX_TS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) mutex_lock(&dp83640->clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) ext_write(0, dp83640->phydev, PAGE5, PTP_TXCFG0, txcfg0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) ext_write(0, dp83640->phydev, PAGE5, PTP_RXCFG0, rxcfg0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) mutex_unlock(&dp83640->clock->extreg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) static void rx_timestamp_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) struct dp83640_private *dp83640 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) container_of(work, struct dp83640_private, ts_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) /* Deliver expired packets. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) while ((skb = skb_dequeue(&dp83640->rx_queue))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) struct dp83640_skb_info *skb_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) skb_info = (struct dp83640_skb_info *)skb->cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (!time_after(jiffies, skb_info->tmo)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) skb_queue_head(&dp83640->rx_queue, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) netif_rx_ni(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (!skb_queue_empty(&dp83640->rx_queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) static bool dp83640_rxtstamp(struct mii_timestamper *mii_ts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct sk_buff *skb, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) struct dp83640_private *dp83640 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) container_of(mii_ts, struct dp83640_private, mii_ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) struct list_head *this, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) struct rxts *rxts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) struct skb_shared_hwtstamps *shhwtstamps = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (is_status_frame(skb, type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) decode_status_frame(dp83640, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (!dp83640->hwts_rx_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) spin_lock_irqsave(&dp83640->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) prune_rx_ts(dp83640);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) list_for_each_safe(this, next, &dp83640->rxts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) rxts = list_entry(this, struct rxts, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (match(skb, type, rxts)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) shhwtstamps = skb_hwtstamps(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) memset(shhwtstamps, 0, sizeof(*shhwtstamps));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) list_del_init(&rxts->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) list_add(&rxts->list, &dp83640->rxpool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) spin_unlock_irqrestore(&dp83640->rx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (!shhwtstamps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) skb_info->ptp_type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) skb_queue_tail(&dp83640->rx_queue, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) netif_rx_ni(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) static void dp83640_txtstamp(struct mii_timestamper *mii_ts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) struct sk_buff *skb, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) struct dp83640_private *dp83640 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) container_of(mii_ts, struct dp83640_private, mii_ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) switch (dp83640->hwts_tx_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) case HWTSTAMP_TX_ONESTEP_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (is_sync(skb, type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) case HWTSTAMP_TX_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) skb_queue_tail(&dp83640->tx_queue, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) case HWTSTAMP_TX_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) static int dp83640_ts_info(struct mii_timestamper *mii_ts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) struct ethtool_ts_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) struct dp83640_private *dp83640 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) container_of(mii_ts, struct dp83640_private, mii_ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) info->so_timestamping =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) SOF_TIMESTAMPING_TX_HARDWARE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) SOF_TIMESTAMPING_RX_HARDWARE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) SOF_TIMESTAMPING_RAW_HARDWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) info->tx_types =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) (1 << HWTSTAMP_TX_OFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) (1 << HWTSTAMP_TX_ON) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) (1 << HWTSTAMP_TX_ONESTEP_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) info->rx_filters =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) (1 << HWTSTAMP_FILTER_NONE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) static int dp83640_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) struct dp83640_clock *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) struct dp83640_private *dp83640;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) int err = -ENOMEM, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (phydev->mdio.addr == BROADCAST_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) clock = dp83640_clock_get_bus(phydev->mdio.bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (!clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) goto no_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (!dp83640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) goto no_memory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) dp83640->phydev = phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) dp83640->mii_ts.rxtstamp = dp83640_rxtstamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) dp83640->mii_ts.txtstamp = dp83640_txtstamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) dp83640->mii_ts.hwtstamp = dp83640_hwtstamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) dp83640->mii_ts.ts_info = dp83640_ts_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) INIT_LIST_HEAD(&dp83640->rxts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) INIT_LIST_HEAD(&dp83640->rxpool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) for (i = 0; i < MAX_RXTS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) phydev->mii_ts = &dp83640->mii_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) phydev->priv = dp83640;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) spin_lock_init(&dp83640->rx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) skb_queue_head_init(&dp83640->rx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) skb_queue_head_init(&dp83640->tx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) dp83640->clock = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (choose_this_phy(clock, phydev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) clock->chosen = dp83640;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) clock->ptp_clock = ptp_clock_register(&clock->caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) &phydev->mdio.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (IS_ERR(clock->ptp_clock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) err = PTR_ERR(clock->ptp_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) goto no_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) list_add_tail(&dp83640->list, &clock->phylist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) dp83640_clock_put(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) no_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) clock->chosen = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) kfree(dp83640);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) no_memory:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) dp83640_clock_put(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) no_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static void dp83640_remove(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) struct dp83640_clock *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) struct list_head *this, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) struct dp83640_private *tmp, *dp83640 = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (phydev->mdio.addr == BROADCAST_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) phydev->mii_ts = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) enable_status_frames(phydev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) cancel_delayed_work_sync(&dp83640->ts_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) skb_queue_purge(&dp83640->rx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) skb_queue_purge(&dp83640->tx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) clock = dp83640_clock_get(dp83640->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) if (dp83640 == clock->chosen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) ptp_clock_unregister(clock->ptp_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) clock->chosen = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) list_for_each_safe(this, next, &clock->phylist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) tmp = list_entry(this, struct dp83640_private, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (tmp == dp83640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) list_del_init(&tmp->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) dp83640_clock_put(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) kfree(dp83640);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) static struct phy_driver dp83640_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .phy_id = DP83640_PHY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .name = "NatSemi DP83640",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) /* PHY_BASIC_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .probe = dp83640_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .remove = dp83640_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .soft_reset = dp83640_soft_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .config_init = dp83640_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .ack_interrupt = dp83640_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .config_intr = dp83640_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) static int __init dp83640_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) return phy_driver_register(&dp83640_driver, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) static void __exit dp83640_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) dp83640_free_clocks();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) phy_driver_unregister(&dp83640_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) module_init(dp83640_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) module_exit(dp83640_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) { DP83640_PHY_ID, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) MODULE_DEVICE_TABLE(mdio, dp83640_tbl);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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