^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/net/phy/cicada.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Driver for Cicada PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Andy Fleming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2004 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/unistd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Cicada Extended Control Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MII_CIS8201_EXT_CON1 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MII_CIS8201_EXTCON1_INIT 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Cicada Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MII_CIS8201_IMASK 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MII_CIS8201_IMASK_IEN 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MII_CIS8201_IMASK_SPEED 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MII_CIS8201_IMASK_LINK 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MII_CIS8201_IMASK_DUPLEX 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MII_CIS8201_IMASK_MASK 0xf000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Cicada Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MII_CIS8201_ISTAT 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MII_CIS8201_ISTAT_STATUS 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MII_CIS8201_ISTAT_SPEED 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MII_CIS8201_ISTAT_LINK 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MII_CIS8201_ISTAT_DUPLEX 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Cicada Auxiliary Control/Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MII_CIS8201_AUX_CONSTAT 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MII_CIS8201_AUXCONSTAT_INIT 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MII_CIS8201_AUXCONSTAT_SPEED 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MII_CIS8201_AUXCONSTAT_GBIT 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MII_CIS8201_AUXCONSTAT_100 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MODULE_DESCRIPTION("Cicadia PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MODULE_AUTHOR("Andy Fleming");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int cis820x_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) err = phy_write(phydev, MII_CIS8201_AUX_CONSTAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MII_CIS8201_AUXCONSTAT_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) err = phy_write(phydev, MII_CIS8201_EXT_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MII_CIS8201_EXTCON1_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int cis820x_ack_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int err = phy_read(phydev, MII_CIS8201_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return (err < 0) ? err : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int cis820x_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) err = phy_write(phydev, MII_CIS8201_IMASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MII_CIS8201_IMASK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) err = phy_write(phydev, MII_CIS8201_IMASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Cicada 8201, a.k.a Vitesse VSC8201 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct phy_driver cis820x_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .phy_id = 0x000fc410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .name = "Cicada Cis8201",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .phy_id_mask = 0x000ffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .config_init = &cis820x_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .ack_interrupt = &cis820x_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .config_intr = &cis820x_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .phy_id = 0x000fc440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .name = "Cicada Cis8204",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .phy_id_mask = 0x000fffc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .config_init = &cis820x_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .ack_interrupt = &cis820x_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .config_intr = &cis820x_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) module_phy_driver(cis820x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static struct mdio_device_id __maybe_unused cicada_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { 0x000fc410, 0x000ffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { 0x000fc440, 0x000fffc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MODULE_DEVICE_TABLE(mdio, cicada_tbl);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags