^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/net/phy/broadcom.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * transceivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2006 Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Inspired by code written by Amy Fong.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "bcm-phy-lib.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/brcmphy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BRCM_PHY_MODEL(phydev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BRCM_PHY_REV(phydev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MODULE_DESCRIPTION("Broadcom PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MODULE_AUTHOR("Maciej W. Rozycki");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int bcm54xx_config_clock_delay(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int rc, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* handling PHY's internal RX clock delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) val |= MII_BCM54XX_AUXCTL_MISC_WREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Disable RGMII RXC-RXD skew */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Enable RGMII RXC-RXD skew */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* handling PHY's internal TX clock delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Disable internal TX clock delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Enable internal TX clock delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int bcm54210e_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) bcm54xx_config_clock_delay(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) val = phy_read(phydev, MII_CTRL1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) phy_write(phydev, MII_CTRL1000, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int bcm54612e_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) bcm54xx_config_clock_delay(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) BCM54612E_LED4_CLK125OUT_EN | reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int bcm54616s_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int rc, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) phydev->interface != PHY_INTERFACE_MODE_1000BASEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Ensure proper interface mode is selected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Disable RGMII mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) val |= MII_BCM54XX_AUXCTL_MISC_WREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Select 1000BASE-X register set (primary SerDes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) val |= BCM54XX_SHD_MODE_1000BX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Power down SerDes interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Select proper interface mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) val &= ~BCM54XX_SHD_INTF_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) val |= phydev->interface == PHY_INTERFACE_MODE_SGMII ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) BCM54XX_SHD_INTF_SEL_SGMII :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) BCM54XX_SHD_INTF_SEL_GBIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Power up SerDes interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Select copper register set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) val &= ~BCM54XX_SHD_MODE_1000BX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Power up copper interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int bcm50610_a0_workaround(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MII_BCM54XX_EXP_EXP75_VDACCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MII_BCM54XX_EXP_EXP96_MYST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MII_BCM54XX_EXP_EXP97_MYST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int bcm54xx_phydsp_config(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int err, err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Enable the SMDSP clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) err = bcm54xx_auxctl_write(phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Clear bit 9 to fix a phy interop issue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (phydev->drv->phy_id == PHY_ID_BCM50610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) err = bcm50610_a0_workaround(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Disable the SMDSP clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) err2 = bcm54xx_auxctl_write(phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Return the first error reported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return err ? err : err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) bool clk125en = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Abort if we are using an untested phy. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54810 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) orig = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) BRCM_PHY_REV(phydev) >= 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * Here, bit 0 _disables_ CLK125 when set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * This bit is set by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) clk125en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Here, bit 0 _enables_ CLK125 when set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) clk125en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) val |= BCM54810_SHD_SCR3_TRDDAPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) val |= BCM54XX_SHD_SCR3_TRDDAPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (orig != val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) orig = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) val |= BCM54XX_SHD_APD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) val &= ~BCM54XX_SHD_APD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (orig != val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int bcm54xx_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int reg, err, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) reg = phy_read(phydev, MII_BCM54XX_ECR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Mask interrupts globally. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) reg |= MII_BCM54XX_ECR_IM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) err = phy_write(phydev, MII_BCM54XX_ECR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Unmask events we are interested in. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) reg = ~(MII_BCM54XX_INT_DUPLEX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MII_BCM54XX_INT_SPEED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) MII_BCM54XX_INT_LINK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) err = phy_write(phydev, MII_BCM54XX_IMR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bcm54xx_adjust_rxrefclk(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) switch (BRCM_PHY_MODEL(phydev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) case PHY_ID_BCM50610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case PHY_ID_BCM50610M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) err = bcm54xx_config_clock_delay(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case PHY_ID_BCM54210E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) err = bcm54210e_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case PHY_ID_BCM54612E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) err = bcm54612e_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case PHY_ID_BCM54616S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) err = bcm54616s_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case PHY_ID_BCM54810:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* For BCM54810, we need to disable BroadR-Reach function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) val = bcm_phy_read_exp(phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) err = bcm_phy_write_exp(phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) bcm54xx_phydsp_config(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Encode link speed into LED1 and LED3 pair (green/amber).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * Also flash these two LEDs on activity. This means configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * them for MULTICOLOR and encoding link/activity into them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) val = BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_MULTICOLOR1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_MULTICOLOR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) val = BCM_LED_MULTICOLOR_IN_PHASE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) BCM5482_SHD_LEDS1_LED1(BCM_LED_MULTICOLOR_LINK_ACT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) BCM5482_SHD_LEDS1_LED3(BCM_LED_MULTICOLOR_LINK_ACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int bcm54xx_resume(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Writes to register other than BMCR would be ignored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * unless we clear the PDOWN bit first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ret = genphy_resume(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Upon exiting power down, the PHY remains in an internal reset state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * for 40us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) fsleep(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return bcm54xx_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int bcm54811_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int err, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Disable BroadR-Reach function. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) reg = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) reg &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) err = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) err = bcm54xx_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) BCM54612E_LED4_CLK125OUT_EN | reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int bcm5482_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int err, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) err = bcm54xx_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * Enable secondary SerDes and its use as an LED source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_SSD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) bcm_phy_write_shadow(phydev, BCM5482_SHD_SSD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) reg |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) BCM5482_SHD_SSD_LEDM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) BCM5482_SHD_SSD_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * Enable SGMII slave mode and auto-detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) err = bcm_phy_read_exp(phydev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) err = bcm_phy_write_exp(phydev, reg, err |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) BCM5482_SSD_SGMII_SLAVE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) BCM5482_SSD_SGMII_SLAVE_AD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * Disable secondary SerDes powerdown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) err = bcm_phy_read_exp(phydev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) err = bcm_phy_write_exp(phydev, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) err & ~BCM5482_SSD_1000BX_CTL_PWRDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * Select 1000BASE-X register set (primary SerDes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) reg = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) reg | BCM54XX_SHD_MODE_1000BX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * LED1=ACTIVITYLED, LED3=LINKSPD[2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * (Use LED1 as secondary SerDes ACTIVITY LED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * Auto-negotiation doesn't seem to work quite right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * in this mode, so we disable it and force it to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * right speed/duplex setting. Only 'link status'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * is important.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) phydev->autoneg = AUTONEG_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) phydev->speed = SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) phydev->duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static int bcm5482_read_status(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) err = genphy_read_status(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * Only link status matters for 1000Base-X mode, so force
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * 1000 Mbit/s full-duplex status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (phydev->link) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) phydev->speed = SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) phydev->duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int bcm5481_config_aneg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct device_node *np = phydev->mdio.dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Aneg firstly. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ret = genphy_config_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* Then we can set up the delay. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) bcm54xx_config_clock_delay(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (of_property_read_bool(np, "enet-phy-lane-swap")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Lane Swap - Undocumented register...magic! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 0x11B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int bcm54616s_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* The PHY is strapped in RGMII-fiber mode when INTERF_SEL[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * is 01b, and the link between PHY and its link partner can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * either 1000Base-X or 100Base-FX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * RGMII-1000Base-X is properly supported, but RGMII-100Base-FX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * support is still missing as of now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if ((val & BCM54XX_SHD_INTF_SEL_MASK) == BCM54XX_SHD_INTF_SEL_RGMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* Bit 0 of the SerDes 100-FX Control register, when set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * to 1, sets the MII/RGMII -> 100BASE-FX configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * When this bit is set to 0, it sets the GMII/RGMII ->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * 1000BASE-X configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (!(val & BCM54616S_100FX_MODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) phydev->dev_flags |= PHY_BCM_FLAGS_MODE_1000BX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) phydev->port = PORT_FIBRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int bcm54616s_config_aneg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* Aneg firstly. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = genphy_c37_config_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret = genphy_config_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* Then we can set up the delay. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) bcm54xx_config_clock_delay(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static int bcm54616s_read_status(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) err = genphy_c37_read_status(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) err = genphy_read_status(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) val = phy_read(phydev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return phy_write(phydev, reg, val | set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int brcm_fet_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int reg, err, err2, brcmtest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Reset the PHY to bring it to a known state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) err = phy_write(phydev, MII_BMCR, BMCR_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* The datasheet indicates the PHY needs up to 1us to complete a reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * build some slack here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* The PHY requires 65 MDC clock cycles to complete a write operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * and turnaround the line properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * We ignore -EIO here as the MDIO controller (e.g.: mdio-bcm-unimac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * may flag the lack of turn-around as a read failure. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * particularly true with this combination since the MDIO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * only used 64 MDC cycles. This is not a critical failure in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * specific case and it has no functional impact otherwise, so we let
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * that one go through. If there is a genuine bus error, the next read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * of MII_BRCM_FET_INTREG will error out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) err = phy_read(phydev, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (err < 0 && err != -EIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) reg = phy_read(phydev, MII_BRCM_FET_INTREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Unmask events we are interested in and mask interrupts globally. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) reg = MII_BRCM_FET_IR_DUPLEX_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) MII_BRCM_FET_IR_SPEED_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) MII_BRCM_FET_IR_LINK_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) MII_BRCM_FET_IR_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) MII_BRCM_FET_IR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* Enable shadow register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (brcmtest < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return brcmtest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) reg = brcmtest | MII_BRCM_FET_BT_SRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Set the LED mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (reg < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) err = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* Enable auto MDIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) MII_BRCM_FET_SHDW_MC_FAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* Enable auto power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) MII_BRCM_FET_SHDW_AS2_APDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Disable shadow register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) err = err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static int brcm_fet_ack_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* Clear pending interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) reg = phy_read(phydev, MII_BRCM_FET_INTREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static int brcm_fet_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) int reg, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) reg = phy_read(phydev, MII_BRCM_FET_INTREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) reg &= ~MII_BRCM_FET_IR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) reg |= MII_BRCM_FET_IR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct bcm53xx_phy_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) u64 *stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static int bcm53xx_phy_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct bcm53xx_phy_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) phydev->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) priv->stats = devm_kcalloc(&phydev->mdio.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) bcm_phy_get_sset_count(phydev), sizeof(u64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (!priv->stats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static void bcm53xx_phy_get_stats(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct ethtool_stats *stats, u64 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct bcm53xx_phy_priv *priv = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) bcm_phy_get_stats(phydev, priv->stats, stats, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static struct phy_driver broadcom_drivers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .phy_id = PHY_ID_BCM5411,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .name = "Broadcom BCM5411",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .config_init = bcm54xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .ack_interrupt = bcm_phy_ack_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .config_intr = bcm_phy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .phy_id = PHY_ID_BCM5421,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .name = "Broadcom BCM5421",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .config_init = bcm54xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .ack_interrupt = bcm_phy_ack_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .config_intr = bcm_phy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .phy_id = PHY_ID_BCM54210E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .name = "Broadcom BCM54210E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .config_init = bcm54xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .ack_interrupt = bcm_phy_ack_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .config_intr = bcm_phy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .phy_id = PHY_ID_BCM5461,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .name = "Broadcom BCM5461",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .config_init = bcm54xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .ack_interrupt = bcm_phy_ack_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .config_intr = bcm_phy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .phy_id = PHY_ID_BCM54612E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .name = "Broadcom BCM54612E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .config_init = bcm54xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .ack_interrupt = bcm_phy_ack_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .config_intr = bcm_phy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .phy_id = PHY_ID_BCM54616S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .name = "Broadcom BCM54616S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .soft_reset = genphy_soft_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .config_init = bcm54xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .config_aneg = bcm54616s_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .ack_interrupt = bcm_phy_ack_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .config_intr = bcm_phy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .read_status = bcm54616s_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .probe = bcm54616s_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .phy_id = PHY_ID_BCM5464,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .name = "Broadcom BCM5464",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .config_init = bcm54xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .ack_interrupt = bcm_phy_ack_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .config_intr = bcm_phy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .resume = genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .phy_id = PHY_ID_BCM5481,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .name = "Broadcom BCM5481",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .config_init = bcm54xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .config_aneg = bcm5481_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .ack_interrupt = bcm_phy_ack_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .config_intr = bcm_phy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .phy_id = PHY_ID_BCM54810,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .name = "Broadcom BCM54810",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .config_init = bcm54xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .config_aneg = bcm5481_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .ack_interrupt = bcm_phy_ack_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .config_intr = bcm_phy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .resume = bcm54xx_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .phy_id = PHY_ID_BCM54811,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .name = "Broadcom BCM54811",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .config_init = bcm54811_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .config_aneg = bcm5481_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .ack_interrupt = bcm_phy_ack_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .config_intr = bcm_phy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .resume = bcm54xx_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .phy_id = PHY_ID_BCM5482,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .name = "Broadcom BCM5482",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .config_init = bcm5482_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .read_status = bcm5482_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .ack_interrupt = bcm_phy_ack_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .config_intr = bcm_phy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .phy_id = PHY_ID_BCM50610,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .name = "Broadcom BCM50610",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .config_init = bcm54xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .ack_interrupt = bcm_phy_ack_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .config_intr = bcm_phy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .phy_id = PHY_ID_BCM50610M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .name = "Broadcom BCM50610M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .config_init = bcm54xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .ack_interrupt = bcm_phy_ack_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .config_intr = bcm_phy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .phy_id = PHY_ID_BCM57780,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .name = "Broadcom BCM57780",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .config_init = bcm54xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .ack_interrupt = bcm_phy_ack_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .config_intr = bcm_phy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .phy_id = PHY_ID_BCMAC131,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .name = "Broadcom BCMAC131",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* PHY_BASIC_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .config_init = brcm_fet_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .ack_interrupt = brcm_fet_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .config_intr = brcm_fet_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .phy_id = PHY_ID_BCM5241,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .name = "Broadcom BCM5241",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* PHY_BASIC_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .config_init = brcm_fet_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .ack_interrupt = brcm_fet_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .config_intr = brcm_fet_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .phy_id = PHY_ID_BCM5395,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .name = "Broadcom BCM5395",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .flags = PHY_IS_INTERNAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .get_sset_count = bcm_phy_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .get_strings = bcm_phy_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .get_stats = bcm53xx_phy_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .probe = bcm53xx_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .phy_id = PHY_ID_BCM53125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .name = "Broadcom BCM53125",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .flags = PHY_IS_INTERNAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .get_sset_count = bcm_phy_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .get_strings = bcm_phy_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .get_stats = bcm53xx_phy_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .probe = bcm53xx_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .config_init = bcm54xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .ack_interrupt = bcm_phy_ack_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .config_intr = bcm_phy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .phy_id = PHY_ID_BCM89610,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .name = "Broadcom BCM89610",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .config_init = bcm54xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .ack_interrupt = bcm_phy_ack_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .config_intr = bcm_phy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) module_phy_driver(broadcom_drivers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) { PHY_ID_BCM5411, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) { PHY_ID_BCM5421, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) { PHY_ID_BCM54210E, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) { PHY_ID_BCM5461, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) { PHY_ID_BCM54612E, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) { PHY_ID_BCM54616S, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) { PHY_ID_BCM5464, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) { PHY_ID_BCM5481, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) { PHY_ID_BCM54810, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) { PHY_ID_BCM54811, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) { PHY_ID_BCM5482, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) { PHY_ID_BCM50610, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) { PHY_ID_BCM50610M, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) { PHY_ID_BCM57780, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) { PHY_ID_BCMAC131, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) { PHY_ID_BCM5241, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) { PHY_ID_BCM5395, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) { PHY_ID_BCM53125, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) { PHY_ID_BCM89610, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) MODULE_DEVICE_TABLE(mdio, broadcom_tbl);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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