^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2011 - 2012 Cavium, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PHY_ID_BCM8706 0x0143bdc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PHY_ID_BCM8727 0x0143bff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define BCM87XX_PMD_RX_SIGNAL_DETECT (MII_ADDR_C45 | 0x1000a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define BCM87XX_10GBASER_PCS_STATUS (MII_ADDR_C45 | 0x30020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define BCM87XX_XGXS_LANE_STATUS (MII_ADDR_C45 | 0x40018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BCM87XX_LASI_CONTROL (MII_ADDR_C45 | 0x39002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BCM87XX_LASI_STATUS (MII_ADDR_C45 | 0x39005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #if IS_ENABLED(CONFIG_OF_MDIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Set and/or override some configuration registers based on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * broadcom,c45-reg-init property stored in the of_node for the phydev.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * broadcom,c45-reg-init = <devid reg mask value>,...;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * There may be one or more sets of <devid reg mask value>:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * devid: which sub-device to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * reg: the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * mask: if non-zero, ANDed with existing register value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * value: ORed with the masked value and written to the regiser.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static int bcm87xx_of_reg_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) const __be32 *paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) const __be32 *paddr_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int len, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (!phydev->mdio.dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) paddr = of_get_property(phydev->mdio.dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "broadcom,c45-reg-init", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (!paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) paddr_end = paddr + (len /= sizeof(*paddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) while (paddr + 3 < paddr_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u16 devid = be32_to_cpup(paddr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u16 reg = be32_to_cpup(paddr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u16 mask = be32_to_cpup(paddr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u16 val_bits = be32_to_cpup(paddr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 regnum = mdiobus_c45_addr(devid, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) val = phy_read(phydev, regnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (val < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ret = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) val &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) val |= val_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ret = phy_write(phydev, regnum, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int bcm87xx_of_reg_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif /* CONFIG_OF_MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int bcm87xx_get_features(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) phydev->supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int bcm87xx_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return bcm87xx_of_reg_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int bcm87xx_config_aneg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int bcm87xx_read_status(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int rx_signal_detect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int pcs_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int xgxs_lane_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) rx_signal_detect = phy_read(phydev, BCM87XX_PMD_RX_SIGNAL_DETECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (rx_signal_detect < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return rx_signal_detect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if ((rx_signal_detect & 1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) goto no_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pcs_status = phy_read(phydev, BCM87XX_10GBASER_PCS_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (pcs_status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return pcs_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if ((pcs_status & 1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) goto no_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) xgxs_lane_status = phy_read(phydev, BCM87XX_XGXS_LANE_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (xgxs_lane_status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return xgxs_lane_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if ((xgxs_lane_status & 0x1000) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) goto no_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) phydev->speed = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) phydev->link = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) phydev->duplex = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) no_link:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) phydev->link = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int bcm87xx_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int reg, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) reg = phy_read(phydev, BCM87XX_LASI_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) reg |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) reg &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) err = phy_write(phydev, BCM87XX_LASI_CONTROL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int bcm87xx_did_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) reg = phy_read(phydev, BCM87XX_LASI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (reg < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) phydev_err(phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "Error: Read of BCM87XX_LASI_STATUS failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return (reg & 1) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int bcm87xx_ack_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Reading the LASI status clears it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) bcm87xx_did_interrupt(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int bcm8706_match_phy_device(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8706;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int bcm8727_match_phy_device(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8727;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct phy_driver bcm87xx_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .phy_id = PHY_ID_BCM8706,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .phy_id_mask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .name = "Broadcom BCM8706",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .get_features = bcm87xx_get_features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .config_init = bcm87xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .config_aneg = bcm87xx_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .read_status = bcm87xx_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .ack_interrupt = bcm87xx_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .config_intr = bcm87xx_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .did_interrupt = bcm87xx_did_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .match_phy_device = bcm8706_match_phy_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .phy_id = PHY_ID_BCM8727,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .phy_id_mask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .name = "Broadcom BCM8727",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .get_features = bcm87xx_get_features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .config_init = bcm87xx_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .config_aneg = bcm87xx_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .read_status = bcm87xx_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .ack_interrupt = bcm87xx_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .config_intr = bcm87xx_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .did_interrupt = bcm87xx_did_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .match_phy_device = bcm8727_match_phy_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) module_phy_driver(bcm87xx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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