Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) // Broadcom BCM84881 NBASE-T PHY driver, as found on a SFP+ module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (C) 2019 Russell King, Deep Blue Solutions Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Like the Marvell 88x3310, the Broadcom 84881 changes its host-side
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // interface according to the operating speed between 10GBASE-R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) // 2500BASE-X and SGMII (but unlike the 88x3310, without the control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) // word).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) // This driver only supports those aspects of the PHY that I'm able to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) // observe and test with the SFP+ module, which is an incomplete subset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) // of what this PHY is able to support. For example, I only assume it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) // supports a single lane Serdes connection, but it may be that the PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) // is able to support more than that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	MDIO_AN_C22 = 0xffe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static int bcm84881_wait_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 					 val, !(val & MDIO_CTRL1_RESET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 					 100000, 2000000, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static int bcm84881_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	switch (phydev->interface) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	case PHY_INTERFACE_MODE_SGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	case PHY_INTERFACE_MODE_2500BASEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	case PHY_INTERFACE_MODE_10GBASER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static int bcm84881_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	/* This driver requires PMAPMD and AN blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	const u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	if (!phydev->is_c45 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	    (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static int bcm84881_get_features(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	ret = genphy_c45_pma_read_abilities(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	/* Although the PHY sets bit 1.11.8, it does not support 10M modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			   phydev->supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			   phydev->supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int bcm84881_config_aneg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	bool changed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u32 adv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	/* Wait for the PHY to finish initialising, otherwise our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	 * advertisement may be overwritten.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	ret = bcm84881_wait_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	/* We don't support manual MDI control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	/* disabled autoneg doesn't seem to work with this PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if (phydev->autoneg == AUTONEG_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	ret = genphy_c45_an_config_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 				     MDIO_AN_C22 + MII_CTRL1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 				     ADVERTISE_1000FULL | ADVERTISE_1000HALF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 				     adv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	return genphy_c45_check_and_restart_aneg(phydev, changed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int bcm84881_aneg_done(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	int bmsr, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (bmsr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	return !!(val & MDIO_AN_STAT1_COMPLETE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	       !!(bmsr & BMSR_ANEGCOMPLETE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int bcm84881_read_status(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	int bmsr, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (val & MDIO_AN_CTRL1_RESTART) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		phydev->link = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (bmsr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	phydev->autoneg_complete = !!(val & MDIO_AN_STAT1_COMPLETE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 				   !!(bmsr & BMSR_ANEGCOMPLETE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	phydev->link = !!(val & MDIO_STAT1_LSTATUS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		       !!(bmsr & BMSR_LSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (phydev->autoneg == AUTONEG_ENABLE && !phydev->autoneg_complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		phydev->link = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	linkmode_zero(phydev->lp_advertising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	phydev->speed = SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	phydev->duplex = DUPLEX_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	phydev->pause = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	phydev->asym_pause = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	phydev->mdix = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (!phydev->link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (phydev->autoneg_complete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		val = genphy_c45_read_lpa(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		val = phy_read_mmd(phydev, MDIO_MMD_AN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 				   MDIO_AN_C22 + MII_STAT1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		if (phydev->autoneg == AUTONEG_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			phy_resolve_aneg_linkmode(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (phydev->autoneg == AUTONEG_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		/* disabled autoneg doesn't seem to work, so force the link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		 * down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		phydev->link = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* Set the host link mode - we set the phy interface mode and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 * the speed according to this register so that downshift works.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 * We leave the duplex setting as per the resolution from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 * above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x4011);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	mode = (val & 0x1e) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (mode == 1 || mode == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		phydev->interface = PHY_INTERFACE_MODE_SGMII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	else if (mode == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		phydev->interface = PHY_INTERFACE_MODE_10GBASER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	else if (mode == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	switch (mode & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		phydev->speed = SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		phydev->speed = SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		phydev->speed = SPEED_10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		phydev->speed = SPEED_2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		phydev->speed = SPEED_5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	return genphy_c45_read_mdix(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static struct phy_driver bcm84881_drivers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		.phy_id		= 0xae025150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		.phy_id_mask	= 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		.name		= "Broadcom BCM84881",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		.config_init	= bcm84881_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		.probe		= bcm84881_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		.get_features	= bcm84881_get_features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		.config_aneg	= bcm84881_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.aneg_done	= bcm84881_aneg_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.read_status	= bcm84881_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) module_phy_driver(bcm84881_drivers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* FIXME: module auto-loading for Clause 45 PHYs seems non-functional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static struct mdio_device_id __maybe_unused bcm84881_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	{ 0xae025150, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MODULE_AUTHOR("Russell King");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MODULE_DESCRIPTION("Broadcom BCM84881 PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MODULE_DEVICE_TABLE(mdio, bcm84881_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MODULE_LICENSE("GPL");