^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Broadcom BCM7xxx internal transceivers support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014-2017 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "bcm-phy-lib.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/brcmphy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Broadcom BCM7xxx internal PHY registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* EPHY only register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MII_BCM7XXX_100TX_AUX_CTL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MII_BCM7XXX_100TX_FALSE_CAR 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MII_BCM7XXX_100TX_DISC 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MII_BCM7XXX_AUX_MODE 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MII_BCM7XXX_64CLK_MDIO BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MII_BCM7XXX_TEST 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MII_BCM7XXX_SHD_MODE_2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MII_BCM7XXX_SHD_2_ADDR_CTRL 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MII_BCM7XXX_SHD_2_CTRL_STAT 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MII_BCM7XXX_SHD_2_BIAS_TRIM 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MII_BCM7XXX_SHD_3_PCS_CTRL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MII_BCM7XXX_SHD_3_PCS_STATUS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MII_BCM7XXX_SHD_3_EEE_CAP 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MII_BCM7XXX_SHD_3_AN_EEE_ADV 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MII_BCM7XXX_SHD_3_EEE_LP 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MII_BCM7XXX_SHD_3_EEE_WK_ERR 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MII_BCM7XXX_SHD_3_PCS_CTRL_2 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MII_BCM7XXX_PCS_CTRL_2_DEF 0x4400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MII_BCM7XXX_SHD_3_AN_STAT 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MII_BCM7XXX_AN_NULL_MSG_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MII_BCM7XXX_AN_EEE_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MII_BCM7XXX_SHD_3_EEE_THRESH 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MII_BCM7XXX_EEE_THRESH_DEF 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MII_BCM7XXX_SHD_3_TL4 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MII_BCM7XXX_TL4_RST_MSK (BIT(2) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct bcm7xxx_phy_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u64 *stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* AFE_RXCONFIG_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* AFE_RXCONFIG_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * offset for HT=0 code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Reset R_CAL/RC_CAL engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) bcm_phy_r_rc_cal_reset(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * offset for HT=0 code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Reset R_CAL/RC_CAL engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) bcm_phy_r_rc_cal_reset(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* +1 RC_CAL codes for RL centering for both LT and HT conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Cut master bias current by 2% to compensate for RC_CAL offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Improve hybrid leakage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Change rx_on_tune 8 to 0xf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Change 100Tx EEE bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Enable ffe zero detection for Vitesse interoperability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) bcm_phy_r_rc_cal_reset(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Newer devices have moved the revision information back into a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * standard location in MII_PHYS_ID[23]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (rev == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) phydev_name(phydev), phydev->drv->name, rev, patch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Dummy read to a register to workaround an issue upon reset where the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * internal inverter may not allow the first MDIO transaction to pass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * the MDIO management controller and make us return 0xffff for such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * reads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) phy_read(phydev, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case 0xa0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case 0xb0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ret = bcm_phy_28nm_a0b0_afe_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case 0xd0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = bcm7xxx_28nm_d0_afe_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case 0xe0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) case 0xf0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Rev G0 introduces a roll over */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case 0x10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ret = bcm_phy_enable_jumbo(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = bcm_phy_downshift_get(phydev, &count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Only enable EEE if Wirespeed/downshift is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return bcm_phy_enable_apd(phydev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int bcm7xxx_28nm_resume(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Re-apply workarounds coming out suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ret = bcm7xxx_28nm_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* 28nm Gigabit PHYs come out of reset without any half-duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * or "hub" compliant advertised mode, fix that. This does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * cause any problems with the PHY library since genphy_config_aneg()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * gracefully handles auto-negotiated and forced modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return genphy_config_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int __phy_set_clr_bits(struct phy_device *dev, int location,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int set_mask, int clr_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int v, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) v = __phy_read(dev, location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (v < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) v &= ~clr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) v |= set_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = __phy_write(dev, location, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int phy_set_clr_bits(struct phy_device *dev, int location,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int set_mask, int clr_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) mutex_lock(&dev->mdio.bus->mdio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret = __phy_set_clr_bits(dev, location, set_mask, clr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mutex_unlock(&dev->mdio.bus->mdio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int bcm7xxx_28nm_ephy_01_afe_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* set shadow mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MII_BCM7XXX_SHD_MODE_2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Set current trim values INT_trim = -1, Ext_trim =0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) goto reset_shadow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Cal reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MII_BCM7XXX_SHD_3_TL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) goto reset_shadow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MII_BCM7XXX_TL4_RST_MSK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) goto reset_shadow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Cal reset disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MII_BCM7XXX_SHD_3_TL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) goto reset_shadow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 0, MII_BCM7XXX_TL4_RST_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) goto reset_shadow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) reset_shadow_mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* reset shadow mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MII_BCM7XXX_SHD_MODE_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* The 28nm EPHY does not support Clause 45 (MMD) used by bcm-phy-lib */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int bcm7xxx_28nm_ephy_apd_enable(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* set shadow mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MII_BRCM_FET_BT_SRE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Enable auto-power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = phy_set_clr_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MII_BRCM_FET_SHDW_AS2_APDE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* reset shadow mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MII_BRCM_FET_BT_SRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int bcm7xxx_28nm_ephy_eee_enable(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* set shadow mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) MII_BCM7XXX_SHD_MODE_2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Advertise supported modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MII_BCM7XXX_SHD_3_AN_EEE_ADV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) goto reset_shadow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MDIO_EEE_100TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) goto reset_shadow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Restore Defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) MII_BCM7XXX_SHD_3_PCS_CTRL_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) goto reset_shadow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MII_BCM7XXX_PCS_CTRL_2_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) goto reset_shadow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MII_BCM7XXX_SHD_3_EEE_THRESH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) goto reset_shadow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MII_BCM7XXX_EEE_THRESH_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) goto reset_shadow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Enable EEE autonegotiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MII_BCM7XXX_SHD_3_AN_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) goto reset_shadow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) (MII_BCM7XXX_AN_NULL_MSG_EN | MII_BCM7XXX_AN_EEE_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) goto reset_shadow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) reset_shadow_mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* reset shadow mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MII_BCM7XXX_SHD_MODE_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Restart autoneg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) phy_write(phydev, MII_BMCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) (BMCR_SPEED100 | BMCR_ANENABLE | BMCR_ANRESTART));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int bcm7xxx_28nm_ephy_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u8 rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pr_info_once("%s: %s PHY revision: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) phydev_name(phydev), phydev->drv->name, rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Dummy read to a register to workaround a possible issue upon reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * where the internal inverter may not allow the first MDIO transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * to pass the MDIO management controller and make us return 0xffff for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * such reads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) phy_read(phydev, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Apply AFE software work-around if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (rev == 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ret = bcm7xxx_28nm_ephy_01_afe_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ret = bcm7xxx_28nm_ephy_eee_enable(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return bcm7xxx_28nm_ephy_apd_enable(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define MII_BCM7XXX_REG_INVALID 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static u8 bcm7xxx_28nm_ephy_regnum_to_shd(u16 regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) switch (regnum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case MDIO_CTRL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return MII_BCM7XXX_SHD_3_PCS_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case MDIO_STAT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return MII_BCM7XXX_SHD_3_PCS_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case MDIO_PCS_EEE_ABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return MII_BCM7XXX_SHD_3_EEE_CAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case MDIO_AN_EEE_ADV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return MII_BCM7XXX_SHD_3_AN_EEE_ADV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case MDIO_AN_EEE_LPABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return MII_BCM7XXX_SHD_3_EEE_LP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case MDIO_PCS_EEE_WK_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return MII_BCM7XXX_SHD_3_EEE_WK_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return MII_BCM7XXX_REG_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static bool bcm7xxx_28nm_ephy_dev_valid(int devnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return devnum == MDIO_MMD_AN || devnum == MDIO_MMD_PCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int bcm7xxx_28nm_ephy_read_mmd(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int devnum, u16 regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u8 shd = bcm7xxx_28nm_ephy_regnum_to_shd(regnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (!bcm7xxx_28nm_ephy_dev_valid(devnum) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) shd == MII_BCM7XXX_REG_INVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* set shadow mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MII_BCM7XXX_SHD_MODE_2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Access the desired shadow register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ret = __phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, shd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) goto reset_shadow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = __phy_read(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) reset_shadow_mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* reset shadow mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) MII_BCM7XXX_SHD_MODE_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int bcm7xxx_28nm_ephy_write_mmd(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) int devnum, u16 regnum, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u8 shd = bcm7xxx_28nm_ephy_regnum_to_shd(regnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (!bcm7xxx_28nm_ephy_dev_valid(devnum) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) shd == MII_BCM7XXX_REG_INVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* set shadow mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MII_BCM7XXX_SHD_MODE_2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Access the desired shadow register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ret = __phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, shd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) goto reset_shadow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Write the desired value in the shadow register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) __phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) reset_shadow_mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* reset shadow mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) MII_BCM7XXX_SHD_MODE_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int bcm7xxx_28nm_ephy_resume(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Re-apply workarounds coming out suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ret = bcm7xxx_28nm_ephy_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return genphy_config_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static int bcm7xxx_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* Enable 64 clock MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) phy_read(phydev, MII_BCM7XXX_AUX_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* set shadow mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* set iddq_clkbias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* reset iddq_clkbias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* reset shadow mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* Workaround for putting the PHY in IDDQ mode, required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * for all BCM7XXX 40nm and 65nm PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int bcm7xxx_suspend(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static const struct bcm7xxx_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) } bcm7xxx_suspend_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) { MII_BCM7XXX_TEST, 0x008b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) { MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) { MII_BCM7XXX_100TX_DISC, 0x7000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) { MII_BCM7XXX_TEST, 0x000f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) { MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) { MII_BCM7XXX_TEST, 0x000b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ret = phy_write(phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) bcm7xxx_suspend_cfg[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) bcm7xxx_suspend_cfg[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int bcm7xxx_28nm_get_tunable(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct ethtool_tunable *tuna,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) switch (tuna->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) case ETHTOOL_PHY_DOWNSHIFT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return bcm_phy_downshift_get(phydev, (u8 *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int bcm7xxx_28nm_set_tunable(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct ethtool_tunable *tuna,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) const void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u8 count = *(u8 *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) switch (tuna->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case ETHTOOL_PHY_DOWNSHIFT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ret = bcm_phy_downshift_set(phydev, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* Disable EEE advertisement since this prevents the PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * from successfully linking up, trigger auto-negotiation restart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * to let the MAC decide what to do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return genphy_restart_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static void bcm7xxx_28nm_get_phy_stats(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct ethtool_stats *stats, u64 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct bcm7xxx_phy_priv *priv = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) bcm_phy_get_stats(phydev, priv->stats, stats, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static int bcm7xxx_28nm_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct bcm7xxx_phy_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) phydev->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) priv->stats = devm_kcalloc(&phydev->mdio.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) bcm_phy_get_sset_count(phydev), sizeof(u64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (!priv->stats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) priv->clk = devm_clk_get_optional(&phydev->mdio.dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (IS_ERR(priv->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Dummy read to a register to workaround an issue upon reset where the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * internal inverter may not allow the first MDIO transaction to pass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * the MDIO management controller and make us return 0xffff for such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * reads. This is needed to ensure that any subsequent reads to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * PHY will succeed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) phy_read(phydev, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static void bcm7xxx_28nm_remove(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct bcm7xxx_phy_priv *priv = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define BCM7XXX_28NM_GPHY(_oui, _name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .phy_id = (_oui), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .phy_id_mask = 0xfffffff0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* PHY_GBIT_FEATURES */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .flags = PHY_IS_INTERNAL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .config_init = bcm7xxx_28nm_config_init, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .resume = bcm7xxx_28nm_resume, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .get_tunable = bcm7xxx_28nm_get_tunable, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .set_tunable = bcm7xxx_28nm_set_tunable, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .get_sset_count = bcm_phy_get_sset_count, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .get_strings = bcm_phy_get_strings, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .get_stats = bcm7xxx_28nm_get_phy_stats, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .probe = bcm7xxx_28nm_probe, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .remove = bcm7xxx_28nm_remove, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define BCM7XXX_28NM_EPHY(_oui, _name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .phy_id = (_oui), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .phy_id_mask = 0xfffffff0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* PHY_BASIC_FEATURES */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .flags = PHY_IS_INTERNAL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .config_init = bcm7xxx_28nm_ephy_config_init, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .resume = bcm7xxx_28nm_ephy_resume, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .get_sset_count = bcm_phy_get_sset_count, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .get_strings = bcm_phy_get_strings, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .get_stats = bcm7xxx_28nm_get_phy_stats, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .probe = bcm7xxx_28nm_probe, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .remove = bcm7xxx_28nm_remove, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .read_mmd = bcm7xxx_28nm_ephy_read_mmd, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .write_mmd = bcm7xxx_28nm_ephy_write_mmd, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define BCM7XXX_40NM_EPHY(_oui, _name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .phy_id = (_oui), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .phy_id_mask = 0xfffffff0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* PHY_BASIC_FEATURES */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .flags = PHY_IS_INTERNAL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .soft_reset = genphy_soft_reset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .config_init = bcm7xxx_config_init, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .suspend = bcm7xxx_suspend, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .resume = bcm7xxx_config_init, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static struct phy_driver bcm7xxx_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) BCM7XXX_28NM_EPHY(PHY_ID_BCM72113, "Broadcom BCM72113"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) BCM7XXX_28NM_EPHY(PHY_ID_BCM7255, "Broadcom BCM7255"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) BCM7XXX_28NM_EPHY(PHY_ID_BCM7260, "Broadcom BCM7260"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) BCM7XXX_28NM_EPHY(PHY_ID_BCM7268, "Broadcom BCM7268"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) BCM7XXX_28NM_EPHY(PHY_ID_BCM7271, "Broadcom BCM7271"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) BCM7XXX_28NM_GPHY(PHY_ID_BCM7278, "Broadcom BCM7278"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) BCM7XXX_28NM_GPHY(PHY_ID_BCM74371, "Broadcom BCM74371"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) BCM7XXX_40NM_EPHY(PHY_ID_BCM7346, "Broadcom BCM7346"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) BCM7XXX_40NM_EPHY(PHY_ID_BCM7362, "Broadcom BCM7362"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) BCM7XXX_40NM_EPHY(PHY_ID_BCM7425, "Broadcom BCM7425"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) BCM7XXX_40NM_EPHY(PHY_ID_BCM7429, "Broadcom BCM7429"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) BCM7XXX_40NM_EPHY(PHY_ID_BCM7435, "Broadcom BCM7435"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) { PHY_ID_BCM72113, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) { PHY_ID_BCM7250, 0xfffffff0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) { PHY_ID_BCM7255, 0xfffffff0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) { PHY_ID_BCM7260, 0xfffffff0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) { PHY_ID_BCM7268, 0xfffffff0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) { PHY_ID_BCM7271, 0xfffffff0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) { PHY_ID_BCM7278, 0xfffffff0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) { PHY_ID_BCM7364, 0xfffffff0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) { PHY_ID_BCM7366, 0xfffffff0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) { PHY_ID_BCM7346, 0xfffffff0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) { PHY_ID_BCM7362, 0xfffffff0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) { PHY_ID_BCM7425, 0xfffffff0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) { PHY_ID_BCM7429, 0xfffffff0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) { PHY_ID_BCM74371, 0xfffffff0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) { PHY_ID_BCM7439, 0xfffffff0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) { PHY_ID_BCM7435, 0xfffffff0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) { PHY_ID_BCM7445, 0xfffffff0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) module_phy_driver(bcm7xxx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) MODULE_AUTHOR("Broadcom Corporation");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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