^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Broadcom BCM54140 Quad SGMII/QSGMII Copper/Fiber Gigabit PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2020 Michael Walle <michael@walle.cc>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/brcmphy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "bcm-phy-lib.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* RDB per-port registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BCM54140_RDB_ISR 0x00a /* interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BCM54140_RDB_IMR 0x00b /* interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BCM54140_RDB_INT_LINK BIT(1) /* link status changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BCM54140_RDB_INT_SPEED BIT(2) /* link speed change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BCM54140_RDB_INT_DUPLEX BIT(3) /* duplex mode changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BCM54140_RDB_SPARE1 0x012 /* spare control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BCM54140_RDB_SPARE1_LSLM BIT(2) /* link speed LED mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BCM54140_RDB_SPARE2 0x014 /* spare control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BCM54140_RDB_SPARE2_WS_RTRY_DIS BIT(8) /* wirespeed retry disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BCM54140_RDB_SPARE2_WS_RTRY_LIMIT GENMASK(4, 2) /* retry limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BCM54140_RDB_SPARE3 0x015 /* spare control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BCM54140_RDB_SPARE3_BIT0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BCM54140_RDB_LED_CTRL 0x019 /* LED control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BCM54140_RDB_LED_CTRL_ACTLINK0 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BCM54140_RDB_LED_CTRL_ACTLINK1 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BCM54140_RDB_C_APWR 0x01a /* auto power down control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BCM54140_RDB_C_APWR_SINGLE_PULSE BIT(8) /* single pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BCM54140_RDB_C_APWR_APD_MODE_DIS 0 /* ADP disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BCM54140_RDB_C_APWR_APD_MODE_EN 1 /* ADP enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BCM54140_RDB_C_APWR_APD_MODE_DIS2 2 /* ADP disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG 3 /* ADP enable w/ aneg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BCM54140_RDB_C_APWR_APD_MODE_MASK GENMASK(6, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BCM54140_RDB_C_APWR_SLP_TIM_MASK BIT(4)/* sleep timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BCM54140_RDB_C_APWR_SLP_TIM_2_7 0 /* 2.7s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BCM54140_RDB_C_APWR_SLP_TIM_5_4 1 /* 5.4s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BCM54140_RDB_C_PWR 0x02a /* copper power control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BCM54140_RDB_C_PWR_ISOLATE BIT(5) /* super isolate mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BCM54140_RDB_C_MISC_CTRL 0x02f /* misc copper control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BCM54140_RDB_C_MISC_CTRL_WS_EN BIT(4) /* wirespeed enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* RDB global registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BCM54140_RDB_TOP_IMR 0x82d /* interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BCM54140_RDB_TOP_IMR_PORT0 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BCM54140_RDB_TOP_IMR_PORT1 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BCM54140_RDB_TOP_IMR_PORT2 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BCM54140_RDB_TOP_IMR_PORT3 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BCM54140_RDB_MON_CTRL 0x831 /* monitor control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BCM54140_RDB_MON_CTRL_V_MODE BIT(3) /* voltage mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BCM54140_RDB_MON_CTRL_SEL_MASK GENMASK(2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BCM54140_RDB_MON_CTRL_SEL_TEMP 0 /* meassure temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BCM54140_RDB_MON_CTRL_SEL_1V0 1 /* meassure AVDDL 1.0V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BCM54140_RDB_MON_CTRL_SEL_3V3 2 /* meassure AVDDH 3.3V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BCM54140_RDB_MON_CTRL_SEL_RR 3 /* meassure all round-robin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BCM54140_RDB_MON_CTRL_PWR_DOWN BIT(0) /* power-down monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BCM54140_RDB_MON_TEMP_VAL 0x832 /* temperature value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BCM54140_RDB_MON_TEMP_MAX 0x833 /* temperature high thresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define BCM54140_RDB_MON_TEMP_MIN 0x834 /* temperature low thresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BCM54140_RDB_MON_TEMP_DATA_MASK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define BCM54140_RDB_MON_1V0_VAL 0x835 /* AVDDL 1.0V value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define BCM54140_RDB_MON_1V0_MAX 0x836 /* AVDDL 1.0V high thresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BCM54140_RDB_MON_1V0_MIN 0x837 /* AVDDL 1.0V low thresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BCM54140_RDB_MON_1V0_DATA_MASK GENMASK(10, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BCM54140_RDB_MON_3V3_VAL 0x838 /* AVDDH 3.3V value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BCM54140_RDB_MON_3V3_MAX 0x839 /* AVDDH 3.3V high thresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BCM54140_RDB_MON_3V3_MIN 0x83a /* AVDDH 3.3V low thresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BCM54140_RDB_MON_3V3_DATA_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define BCM54140_RDB_MON_ISR 0x83b /* interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BCM54140_RDB_MON_ISR_3V3 BIT(2) /* AVDDH 3.3V alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define BCM54140_RDB_MON_ISR_1V0 BIT(1) /* AVDDL 1.0V alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define BCM54140_RDB_MON_ISR_TEMP BIT(0) /* temperature alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* According to the datasheet the formula is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * T = 413.35 - (0.49055 * bits[9:0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BCM54140_HWMON_TO_TEMP(v) (413350L - (v) * 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BCM54140_HWMON_FROM_TEMP(v) DIV_ROUND_CLOSEST_ULL(413350L - (v), 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* According to the datasheet the formula is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * U = bits[11:0] / 1024 * 220 / 0.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Normalized:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * U = bits[11:0] / 4096 * 2514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define BCM54140_HWMON_TO_IN_1V0(v) ((v) * 2514 >> 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define BCM54140_HWMON_FROM_IN_1V0(v) DIV_ROUND_CLOSEST_ULL(((v) << 11), 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* According to the datasheet the formula is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * U = bits[10:0] / 1024 * 880 / 0.7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Normalized:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * U = bits[10:0] / 2048 * 4400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define BCM54140_HWMON_TO_IN_3V3(v) ((v) * 4400 >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BCM54140_HWMON_FROM_IN_3V3(v) DIV_ROUND_CLOSEST_ULL(((v) << 12), 4400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BCM54140_HWMON_TO_IN(ch, v) ((ch) ? BCM54140_HWMON_TO_IN_3V3(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) : BCM54140_HWMON_TO_IN_1V0(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BCM54140_HWMON_FROM_IN(ch, v) ((ch) ? BCM54140_HWMON_FROM_IN_3V3(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) : BCM54140_HWMON_FROM_IN_1V0(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BCM54140_HWMON_IN_MASK(ch) ((ch) ? BCM54140_RDB_MON_3V3_DATA_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) : BCM54140_RDB_MON_1V0_DATA_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BCM54140_HWMON_IN_VAL_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_VAL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) : BCM54140_RDB_MON_1V0_VAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define BCM54140_HWMON_IN_MIN_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_MIN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) : BCM54140_RDB_MON_1V0_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BCM54140_HWMON_IN_MAX_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_MAX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) : BCM54140_RDB_MON_1V0_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BCM54140_HWMON_IN_ALARM_BIT(ch) ((ch) ? BCM54140_RDB_MON_ISR_3V3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) : BCM54140_RDB_MON_ISR_1V0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* This PHY has two different PHY IDs depening on its MODE_SEL pin. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * pin choses between 4x SGMII and QSGMII mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * AE02_5009 4x SGMII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * AE02_5019 QSGMII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define BCM54140_PHY_ID_MASK 0xffffffe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define BCM54140_PHY_ID_REV(phy_id) ((phy_id) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define BCM54140_REV_B0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define BCM54140_DEFAULT_DOWNSHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BCM54140_MAX_DOWNSHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct bcm54140_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #if IS_ENABLED(CONFIG_HWMON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* protect the alarm bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct mutex alarm_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u16 alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #if IS_ENABLED(CONFIG_HWMON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static umode_t bcm54140_hwmon_is_visible(const void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case hwmon_in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case hwmon_in_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) case hwmon_in_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case hwmon_in_label:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case hwmon_in_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) case hwmon_in_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case hwmon_temp_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int bcm54140_hwmon_read_alarm(struct device *dev, unsigned int bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct phy_device *phydev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct bcm54140_priv *priv = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int tmp, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) mutex_lock(&priv->alarm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* latch any alarm bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) tmp = bcm_phy_read_rdb(phydev, BCM54140_RDB_MON_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (tmp < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ret = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) priv->alarm |= tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) *val = !!(priv->alarm & bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) priv->alarm &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) mutex_unlock(&priv->alarm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int bcm54140_hwmon_read_temp(struct device *dev, u32 attr, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct phy_device *phydev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) reg = BCM54140_RDB_MON_TEMP_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) reg = BCM54140_RDB_MON_TEMP_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) reg = BCM54140_RDB_MON_TEMP_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case hwmon_temp_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return bcm54140_hwmon_read_alarm(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) BCM54140_RDB_MON_ISR_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) tmp = bcm_phy_read_rdb(phydev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (tmp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) *val = BCM54140_HWMON_TO_TEMP(tmp & BCM54140_RDB_MON_TEMP_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int bcm54140_hwmon_read_in(struct device *dev, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct phy_device *phydev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u16 bit, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case hwmon_in_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) reg = BCM54140_HWMON_IN_VAL_REG(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case hwmon_in_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) reg = BCM54140_HWMON_IN_MIN_REG(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case hwmon_in_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) reg = BCM54140_HWMON_IN_MAX_REG(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case hwmon_in_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) bit = BCM54140_HWMON_IN_ALARM_BIT(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return bcm54140_hwmon_read_alarm(dev, bit, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) tmp = bcm_phy_read_rdb(phydev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (tmp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) tmp &= BCM54140_HWMON_IN_MASK(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) *val = BCM54140_HWMON_TO_IN(channel, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int bcm54140_hwmon_read(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) enum hwmon_sensor_types type, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return bcm54140_hwmon_read_temp(dev, attr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case hwmon_in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return bcm54140_hwmon_read_in(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const char *const bcm54140_hwmon_in_labels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "AVDDL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "AVDDH",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int bcm54140_hwmon_read_string(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) enum hwmon_sensor_types type, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int channel, const char **str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case hwmon_in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) case hwmon_in_label:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) *str = bcm54140_hwmon_in_labels[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int bcm54140_hwmon_write_temp(struct device *dev, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int channel, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct phy_device *phydev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u16 mask = BCM54140_RDB_MON_TEMP_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) val = clamp_val(val, BCM54140_HWMON_TO_TEMP(mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) BCM54140_HWMON_TO_TEMP(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) reg = BCM54140_RDB_MON_TEMP_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) reg = BCM54140_RDB_MON_TEMP_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return bcm_phy_modify_rdb(phydev, reg, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) BCM54140_HWMON_FROM_TEMP(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int bcm54140_hwmon_write_in(struct device *dev, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int channel, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct phy_device *phydev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u16 mask = BCM54140_HWMON_IN_MASK(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) val = clamp_val(val, 0, BCM54140_HWMON_TO_IN(channel, mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case hwmon_in_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) reg = BCM54140_HWMON_IN_MIN_REG(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case hwmon_in_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) reg = BCM54140_HWMON_IN_MAX_REG(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return bcm_phy_modify_rdb(phydev, reg, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) BCM54140_HWMON_FROM_IN(channel, val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static int bcm54140_hwmon_write(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) enum hwmon_sensor_types type, u32 attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int channel, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) case hwmon_temp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return bcm54140_hwmon_write_temp(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case hwmon_in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return bcm54140_hwmon_write_in(dev, attr, channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct hwmon_channel_info *bcm54140_hwmon_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) HWMON_CHANNEL_INFO(temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) HWMON_T_ALARM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) HWMON_CHANNEL_INFO(in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) HWMON_I_ALARM | HWMON_I_LABEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) HWMON_I_ALARM | HWMON_I_LABEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const struct hwmon_ops bcm54140_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .is_visible = bcm54140_hwmon_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .read = bcm54140_hwmon_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .read_string = bcm54140_hwmon_read_string,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .write = bcm54140_hwmon_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const struct hwmon_chip_info bcm54140_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .ops = &bcm54140_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .info = bcm54140_hwmon_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int bcm54140_enable_monitoring(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u16 mask, set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* 3.3V voltage mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) set = BCM54140_RDB_MON_CTRL_V_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* select round-robin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) mask = BCM54140_RDB_MON_CTRL_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) set |= FIELD_PREP(BCM54140_RDB_MON_CTRL_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) BCM54140_RDB_MON_CTRL_SEL_RR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* remove power-down bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) mask |= BCM54140_RDB_MON_CTRL_PWR_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return bcm_phy_modify_rdb(phydev, BCM54140_RDB_MON_CTRL, mask, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int bcm54140_probe_once(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct device *hwmon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* enable hardware monitoring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ret = bcm54140_enable_monitoring(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) hwmon = devm_hwmon_device_register_with_info(&phydev->mdio.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) "BCM54140", phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) &bcm54140_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return PTR_ERR_OR_ZERO(hwmon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int bcm54140_base_read_rdb(struct phy_device *phydev, u16 rdb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) phy_lock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = __phy_package_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = __phy_package_read(phydev, MII_BCM54XX_RDB_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) phy_unlock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int bcm54140_base_write_rdb(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u16 rdb, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) phy_lock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ret = __phy_package_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ret = __phy_package_write(phydev, MII_BCM54XX_RDB_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) phy_unlock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Under some circumstances a core PLL may not lock, this will then prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * a successful link establishment. Restart the PLL after the voltages are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * stable to workaround this issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int bcm54140_b0_workaround(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int spare3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) spare3 = bcm_phy_read_rdb(phydev, BCM54140_RDB_SPARE3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (spare3 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return spare3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) spare3 &= ~BCM54140_RDB_SPARE3_BIT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = bcm_phy_write_rdb(phydev, BCM54140_RDB_SPARE3, spare3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ret = phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) spare3 |= BCM54140_RDB_SPARE3_BIT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return bcm_phy_write_rdb(phydev, BCM54140_RDB_SPARE3, spare3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* The BCM54140 is a quad PHY where only the first port has access to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * global register. Thus we need to find out its PHY address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static int bcm54140_get_base_addr_and_port(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct bcm54140_priv *priv = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct mii_bus *bus = phydev->mdio.bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int addr, min_addr, max_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int step = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u32 phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) min_addr = phydev->mdio.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) max_addr = phydev->mdio.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) addr = phydev->mdio.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* We scan forward and backwards and look for PHYs which have the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * same phy_id like we do. Step 1 will scan forward, step 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * backwards. Once we are finished, we have a min_addr and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * max_addr which resembles the range of PHY addresses of the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * type of PHY. There is one caveat; there may be many PHYs of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * the same type, but we know that each PHY takes exactly 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * consecutive addresses. Therefore we can deduce our offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * to the base address of this quad PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (step == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) } else if (step == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) max_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) addr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) min_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) addr--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (addr < 0 || addr >= PHY_MAX_ADDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) addr = phydev->mdio.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) step++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* read the PHY id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) tmp = mdiobus_read(bus, addr, MII_PHYSID1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (tmp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) phy_id = tmp << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) tmp = mdiobus_read(bus, addr, MII_PHYSID2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (tmp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) phy_id |= tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* see if it is still the same PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if ((phy_id & phydev->drv->phy_id_mask) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) (phydev->drv->phy_id & phydev->drv->phy_id_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) addr = phydev->mdio.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) step++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* The range we get should be a multiple of four. Please note that both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * the min_addr and max_addr are inclusive. So we have to add one if we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * subtract them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if ((max_addr - min_addr + 1) % 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dev_err(&phydev->mdio.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) "Detected Quad PHY IDs %d..%d doesn't make sense.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) min_addr, max_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) priv->port = (phydev->mdio.addr - min_addr) % 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) priv->base_addr = phydev->mdio.addr - priv->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static int bcm54140_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct bcm54140_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) phydev->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ret = bcm54140_get_base_addr_and_port(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) devm_phy_package_join(&phydev->mdio.dev, phydev, priv->base_addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #if IS_ENABLED(CONFIG_HWMON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) mutex_init(&priv->alarm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (phy_package_init_once(phydev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ret = bcm54140_probe_once(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) phydev_dbg(phydev, "probed (port %d, base PHY address %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) priv->port, priv->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static int bcm54140_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u16 reg = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* Apply hardware errata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (BCM54140_PHY_ID_REV(phydev->phy_id) == BCM54140_REV_B0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ret = bcm54140_b0_workaround(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* Unmask events we are interested in. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) reg &= ~(BCM54140_RDB_INT_DUPLEX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) BCM54140_RDB_INT_SPEED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) BCM54140_RDB_INT_LINK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ret = bcm_phy_write_rdb(phydev, BCM54140_RDB_IMR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* LED1=LINKSPD[1], LED2=LINKSPD[2], LED3=LINK/ACTIVITY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_SPARE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 0, BCM54140_RDB_SPARE1_LSLM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_LED_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 0, BCM54140_RDB_LED_CTRL_ACTLINK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* disable super isolate mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_PWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) BCM54140_RDB_C_PWR_ISOLATE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int bcm54140_did_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ret = bcm_phy_read_rdb(phydev, BCM54140_RDB_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return (ret < 0) ? 0 : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static int bcm54140_ack_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* clear pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) reg = bcm_phy_read_rdb(phydev, BCM54140_RDB_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static int bcm54140_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct bcm54140_priv *priv = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static const u16 port_to_imr_bit[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) BCM54140_RDB_TOP_IMR_PORT0, BCM54140_RDB_TOP_IMR_PORT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) BCM54140_RDB_TOP_IMR_PORT2, BCM54140_RDB_TOP_IMR_PORT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (priv->port >= ARRAY_SIZE(port_to_imr_bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) reg = bcm54140_base_read_rdb(phydev, BCM54140_RDB_TOP_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) reg &= ~port_to_imr_bit[priv->port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) reg |= port_to_imr_bit[priv->port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return bcm54140_base_write_rdb(phydev, BCM54140_RDB_TOP_IMR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static int bcm54140_get_downshift(struct phy_device *phydev, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) val = bcm_phy_read_rdb(phydev, BCM54140_RDB_C_MISC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (!(val & BCM54140_RDB_C_MISC_CTRL_WS_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) *data = DOWNSHIFT_DEV_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) val = bcm_phy_read_rdb(phydev, BCM54140_RDB_SPARE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (val & BCM54140_RDB_SPARE2_WS_RTRY_DIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) *data = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) *data = FIELD_GET(BCM54140_RDB_SPARE2_WS_RTRY_LIMIT, val) + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static int bcm54140_set_downshift(struct phy_device *phydev, u8 cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u16 mask, set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (cnt > BCM54140_MAX_DOWNSHIFT && cnt != DOWNSHIFT_DEV_DEFAULT_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (!cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_MISC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) BCM54140_RDB_C_MISC_CTRL_WS_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (cnt == DOWNSHIFT_DEV_DEFAULT_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) cnt = BCM54140_DEFAULT_DOWNSHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (cnt == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) set = BCM54140_RDB_SPARE2_WS_RTRY_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) mask = BCM54140_RDB_SPARE2_WS_RTRY_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) mask |= BCM54140_RDB_SPARE2_WS_RTRY_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) set = FIELD_PREP(BCM54140_RDB_SPARE2_WS_RTRY_LIMIT, cnt - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_SPARE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) mask, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_MISC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 0, BCM54140_RDB_C_MISC_CTRL_WS_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static int bcm54140_get_edpd(struct phy_device *phydev, u16 *tx_interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) val = bcm_phy_read_rdb(phydev, BCM54140_RDB_C_APWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) switch (FIELD_GET(BCM54140_RDB_C_APWR_APD_MODE_MASK, val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) case BCM54140_RDB_C_APWR_APD_MODE_DIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) case BCM54140_RDB_C_APWR_APD_MODE_DIS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) *tx_interval = ETHTOOL_PHY_EDPD_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) case BCM54140_RDB_C_APWR_APD_MODE_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) case BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) switch (FIELD_GET(BCM54140_RDB_C_APWR_SLP_TIM_MASK, val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) case BCM54140_RDB_C_APWR_SLP_TIM_2_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) *tx_interval = 2700;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) case BCM54140_RDB_C_APWR_SLP_TIM_5_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) *tx_interval = 5400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int bcm54140_set_edpd(struct phy_device *phydev, u16 tx_interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) u16 mask, set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) mask = BCM54140_RDB_C_APWR_APD_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (tx_interval == ETHTOOL_PHY_EDPD_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) set = FIELD_PREP(BCM54140_RDB_C_APWR_APD_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) BCM54140_RDB_C_APWR_APD_MODE_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) set = FIELD_PREP(BCM54140_RDB_C_APWR_APD_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* enable single pulse mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) set |= BCM54140_RDB_C_APWR_SINGLE_PULSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* set sleep timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) mask |= BCM54140_RDB_C_APWR_SLP_TIM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) switch (tx_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) case ETHTOOL_PHY_EDPD_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) case 2700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) set |= BCM54140_RDB_C_APWR_SLP_TIM_2_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) case 5400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) set |= BCM54140_RDB_C_APWR_SLP_TIM_5_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_APWR, mask, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static int bcm54140_get_tunable(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct ethtool_tunable *tuna, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) switch (tuna->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) case ETHTOOL_PHY_DOWNSHIFT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return bcm54140_get_downshift(phydev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) case ETHTOOL_PHY_EDPD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return bcm54140_get_edpd(phydev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static int bcm54140_set_tunable(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct ethtool_tunable *tuna, const void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) switch (tuna->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) case ETHTOOL_PHY_DOWNSHIFT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return bcm54140_set_downshift(phydev, *(const u8 *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) case ETHTOOL_PHY_EDPD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return bcm54140_set_edpd(phydev, *(const u16 *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static struct phy_driver bcm54140_drivers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .phy_id = PHY_ID_BCM54140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .phy_id_mask = BCM54140_PHY_ID_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .name = "Broadcom BCM54140",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .flags = PHY_POLL_CABLE_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .features = PHY_GBIT_FEATURES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .config_init = bcm54140_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .did_interrupt = bcm54140_did_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .ack_interrupt = bcm54140_ack_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .config_intr = bcm54140_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .probe = bcm54140_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .resume = genphy_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .soft_reset = genphy_soft_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .get_tunable = bcm54140_get_tunable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .set_tunable = bcm54140_set_tunable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .cable_test_start = bcm_phy_cable_test_start_rdb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .cable_test_get_status = bcm_phy_cable_test_get_status_rdb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) module_phy_driver(bcm54140_drivers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static struct mdio_device_id __maybe_unused bcm54140_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) { PHY_ID_BCM54140, BCM54140_PHY_ID_MASK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) MODULE_AUTHOR("Michael Walle");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) MODULE_DESCRIPTION("Broadcom BCM54140 PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) MODULE_DEVICE_TABLE(mdio, bcm54140_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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