Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2015 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _LINUX_BCM_PHY_LIB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _LINUX_BCM_PHY_LIB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/brcmphy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* 28nm only register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MISC_ADDR(base, channel)	base, channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DSP_TAP10			MISC_ADDR(0x0a, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PLL_PLLCTRL_1			MISC_ADDR(0x32, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PLL_PLLCTRL_2			MISC_ADDR(0x32, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PLL_PLLCTRL_4			MISC_ADDR(0x33, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AFE_RXCONFIG_0			MISC_ADDR(0x38, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AFE_RXCONFIG_1			MISC_ADDR(0x38, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AFE_RXCONFIG_2			MISC_ADDR(0x38, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AFE_RX_LP_COUNTER		MISC_ADDR(0x38, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AFE_TX_CONFIG			MISC_ADDR(0x39, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AFE_VDCA_ICTRL_0		MISC_ADDR(0x39, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AFE_VDAC_OTHERS_0		MISC_ADDR(0x39, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AFE_HPF_TRIM_OTHERS		MISC_ADDR(0x3a, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int __bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int __bcm_phy_read_exp(struct phy_device *phydev, u16 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int __bcm_phy_modify_exp(struct phy_device *phydev, u16 reg, u16 mask, u16 set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int bcm_phy_read_exp(struct phy_device *phydev, u16 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int bcm_phy_modify_exp(struct phy_device *phydev, u16 reg, u16 mask, u16 set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static inline int bcm_phy_write_exp_sel(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 					u16 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	return bcm_phy_write_exp(phydev, reg | MII_BCM54XX_EXP_SEL_ER, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int bcm_phy_write_misc(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		       u16 reg, u16 chl, u16 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int bcm_phy_read_misc(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		      u16 reg, u16 chl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int bcm_phy_write_shadow(struct phy_device *phydev, u16 shadow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			 u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int bcm_phy_read_shadow(struct phy_device *phydev, u16 shadow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int __bcm_phy_write_rdb(struct phy_device *phydev, u16 rdb, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int bcm_phy_write_rdb(struct phy_device *phydev, u16 rdb, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int __bcm_phy_read_rdb(struct phy_device *phydev, u16 rdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int bcm_phy_read_rdb(struct phy_device *phydev, u16 rdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int __bcm_phy_modify_rdb(struct phy_device *phydev, u16 rdb, u16 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 			 u16 set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int bcm_phy_modify_rdb(struct phy_device *phydev, u16 rdb, u16 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		       u16 set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int bcm_phy_ack_intr(struct phy_device *phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int bcm_phy_config_intr(struct phy_device *phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int bcm_phy_enable_apd(struct phy_device *phydev, bool dll_pwr_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int bcm_phy_set_eee(struct phy_device *phydev, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int bcm_phy_downshift_get(struct phy_device *phydev, u8 *count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int bcm_phy_downshift_set(struct phy_device *phydev, u8 count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int bcm_phy_get_sset_count(struct phy_device *phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void bcm_phy_get_strings(struct phy_device *phydev, u8 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) void bcm_phy_get_stats(struct phy_device *phydev, u64 *shadow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 		       struct ethtool_stats *stats, u64 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void bcm_phy_r_rc_cal_reset(struct phy_device *phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int bcm_phy_28nm_a0b0_afe_config_init(struct phy_device *phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int bcm_phy_enable_jumbo(struct phy_device *phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int bcm_phy_cable_test_get_status_rdb(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 				      bool *finished);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int bcm_phy_cable_test_start_rdb(struct phy_device *phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int bcm_phy_cable_test_start(struct phy_device *phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int bcm_phy_cable_test_get_status(struct phy_device *phydev, bool *finished);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #endif /* _LINUX_BCM_PHY_LIB_H */