^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015-2017 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include "bcm-phy-lib.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/brcmphy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/ethtool_netlink.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MII_BCM_CHANNEL_WIDTH 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BCM_CL45VEN_EEE_ADV 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) int __bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) rc = __phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) return __phy_write(phydev, MII_BCM54XX_EXP_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) EXPORT_SYMBOL_GPL(__bcm_phy_write_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) phy_lock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) rc = __bcm_phy_write_exp(phydev, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) phy_unlock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) EXPORT_SYMBOL_GPL(bcm_phy_write_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int __bcm_phy_read_exp(struct phy_device *phydev, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) val = __phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) val = __phy_read(phydev, MII_BCM54XX_EXP_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Restore default value. It's O.K. if this write fails. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) __phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) EXPORT_SYMBOL_GPL(__bcm_phy_read_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int bcm_phy_read_exp(struct phy_device *phydev, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) phy_lock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) rc = __bcm_phy_read_exp(phydev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) phy_unlock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) EXPORT_SYMBOL_GPL(bcm_phy_read_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int __bcm_phy_modify_exp(struct phy_device *phydev, u16 reg, u16 mask, u16 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int new, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ret = __phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ret = __phy_read(phydev, MII_BCM54XX_EXP_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) new = (ret & ~mask) | set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (new == ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return __phy_write(phydev, MII_BCM54XX_EXP_DATA, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) EXPORT_SYMBOL_GPL(__bcm_phy_modify_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int bcm_phy_modify_exp(struct phy_device *phydev, u16 reg, u16 mask, u16 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) phy_lock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ret = __bcm_phy_modify_exp(phydev, reg, mask, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) phy_unlock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) EXPORT_SYMBOL_GPL(bcm_phy_modify_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* The register must be written to both the Shadow Register Select and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * the Shadow Read Register Selector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return phy_read(phydev, MII_BCM54XX_AUX_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) EXPORT_SYMBOL_GPL(bcm54xx_auxctl_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) EXPORT_SYMBOL(bcm54xx_auxctl_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int bcm_phy_write_misc(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u16 reg, u16 chl, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) rc = bcm_phy_write_exp(phydev, tmp, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) EXPORT_SYMBOL_GPL(bcm_phy_write_misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int bcm_phy_read_misc(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u16 reg, u16 chl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) rc = bcm_phy_read_exp(phydev, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) EXPORT_SYMBOL_GPL(bcm_phy_read_misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int bcm_phy_ack_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Clear pending interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) reg = phy_read(phydev, MII_BCM54XX_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) EXPORT_SYMBOL_GPL(bcm_phy_ack_intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int bcm_phy_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) reg = phy_read(phydev, MII_BCM54XX_ECR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) reg &= ~MII_BCM54XX_ECR_IM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) reg |= MII_BCM54XX_ECR_IM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return phy_write(phydev, MII_BCM54XX_ECR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) EXPORT_SYMBOL_GPL(bcm_phy_config_intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int bcm_phy_read_shadow(struct phy_device *phydev, u16 shadow)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) EXPORT_SYMBOL_GPL(bcm_phy_read_shadow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int bcm_phy_write_shadow(struct phy_device *phydev, u16 shadow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return phy_write(phydev, MII_BCM54XX_SHD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MII_BCM54XX_SHD_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MII_BCM54XX_SHD_VAL(shadow) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MII_BCM54XX_SHD_DATA(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) EXPORT_SYMBOL_GPL(bcm_phy_write_shadow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int __bcm_phy_read_rdb(struct phy_device *phydev, u16 rdb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) val = __phy_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return __phy_read(phydev, MII_BCM54XX_RDB_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) EXPORT_SYMBOL_GPL(__bcm_phy_read_rdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int bcm_phy_read_rdb(struct phy_device *phydev, u16 rdb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) phy_lock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = __bcm_phy_read_rdb(phydev, rdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) phy_unlock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) EXPORT_SYMBOL_GPL(bcm_phy_read_rdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int __bcm_phy_write_rdb(struct phy_device *phydev, u16 rdb, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ret = __phy_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return __phy_write(phydev, MII_BCM54XX_RDB_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) EXPORT_SYMBOL_GPL(__bcm_phy_write_rdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int bcm_phy_write_rdb(struct phy_device *phydev, u16 rdb, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) phy_lock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ret = __bcm_phy_write_rdb(phydev, rdb, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) phy_unlock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) EXPORT_SYMBOL_GPL(bcm_phy_write_rdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int __bcm_phy_modify_rdb(struct phy_device *phydev, u16 rdb, u16 mask, u16 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int new, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ret = __phy_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ret = __phy_read(phydev, MII_BCM54XX_RDB_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) new = (ret & ~mask) | set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (new == ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return __phy_write(phydev, MII_BCM54XX_RDB_DATA, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) EXPORT_SYMBOL_GPL(__bcm_phy_modify_rdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int bcm_phy_modify_rdb(struct phy_device *phydev, u16 rdb, u16 mask, u16 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) phy_lock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = __bcm_phy_modify_rdb(phydev, rdb, mask, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) phy_unlock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) EXPORT_SYMBOL_GPL(bcm_phy_modify_rdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int bcm_phy_enable_apd(struct phy_device *phydev, bool dll_pwr_down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (dll_pwr_down) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Clear APD bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) val &= BCM_APD_CLR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (phydev->autoneg == AUTONEG_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) val |= BCM54XX_SHD_APD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) val |= BCM_NO_ANEG_APD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Enable energy detect single link pulse for easy wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) val |= BCM_APD_SINGLELP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Enable Auto Power-Down (APD) for the PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) EXPORT_SYMBOL_GPL(bcm_phy_enable_apd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int bcm_phy_set_eee(struct phy_device *phydev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int val, mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Enable EEE at PHY level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) val = phy_read_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) val |= LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) val &= ~(LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) phy_write_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL, (u32)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Advertise EEE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) val = phy_read_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) phydev->supported))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) mask |= MDIO_EEE_1000T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) phydev->supported))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mask |= MDIO_EEE_100TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) phy_write_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV, (u32)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) EXPORT_SYMBOL_GPL(bcm_phy_set_eee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int bcm_phy_downshift_get(struct phy_device *phydev, u8 *count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Check if wirespeed is enabled or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (!(val & MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) *count = DOWNSHIFT_DEV_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Downgrade after one link attempt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (val & BCM54XX_SHD_SCR2_WSPD_RTRY_DIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) *count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Downgrade after configured retry count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) val >>= BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) val &= BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) *count = val + BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) EXPORT_SYMBOL_GPL(bcm_phy_downshift_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int bcm_phy_downshift_set(struct phy_device *phydev, u8 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int val = 0, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Range check the number given */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (count - BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) count != DOWNSHIFT_DEV_DEFAULT_COUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Se the write enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) val |= MII_BCM54XX_AUXCTL_MISC_WREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (count == DOWNSHIFT_DEV_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return bcm54xx_auxctl_write(phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = bcm54xx_auxctl_write(phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) val &= ~(BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) BCM54XX_SHD_SCR2_WSPD_RTRY_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) switch (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) val |= BCM54XX_SHD_SCR2_WSPD_RTRY_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case DOWNSHIFT_DEV_DEFAULT_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) val |= 1 << BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) val |= (count - BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) EXPORT_SYMBOL_GPL(bcm_phy_downshift_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct bcm_phy_hw_stat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) const char *string;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u8 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Counters freeze at either 0xffff or 0xff, better than nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const struct bcm_phy_hw_stat bcm_phy_hw_stats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) { "phy_receive_errors", MII_BRCM_CORE_BASE12, 0, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { "phy_serdes_ber_errors", MII_BRCM_CORE_BASE13, 8, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) { "phy_false_carrier_sense_errors", MII_BRCM_CORE_BASE13, 0, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { "phy_local_rcvr_nok", MII_BRCM_CORE_BASE14, 8, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { "phy_remote_rcv_nok", MII_BRCM_CORE_BASE14, 0, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int bcm_phy_get_sset_count(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ARRAY_SIZE(bcm_phy_hw_stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) EXPORT_SYMBOL_GPL(bcm_phy_get_sset_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) void bcm_phy_get_strings(struct phy_device *phydev, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) for (i = 0; i < ARRAY_SIZE(bcm_phy_hw_stats); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) strlcpy(data + i * ETH_GSTRING_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) bcm_phy_hw_stats[i].string, ETH_GSTRING_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) EXPORT_SYMBOL_GPL(bcm_phy_get_strings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* Caller is supposed to provide appropriate storage for the library code to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * access the shadow copy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static u64 bcm_phy_get_stat(struct phy_device *phydev, u64 *shadow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) unsigned int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct bcm_phy_hw_stat stat = bcm_phy_hw_stats[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u64 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) val = phy_read(phydev, stat.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (val < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ret = U64_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) val >>= stat.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) val = val & ((1 << stat.bits) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) shadow[i] += val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ret = shadow[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) void bcm_phy_get_stats(struct phy_device *phydev, u64 *shadow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct ethtool_stats *stats, u64 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) for (i = 0; i < ARRAY_SIZE(bcm_phy_hw_stats); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) data[i] = bcm_phy_get_stat(phydev, shadow, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) EXPORT_SYMBOL_GPL(bcm_phy_get_stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) void bcm_phy_r_rc_cal_reset(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* Reset R_CAL/RC_CAL Engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* Disable Reset R_AL/RC_CAL Engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) EXPORT_SYMBOL_GPL(bcm_phy_r_rc_cal_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int bcm_phy_28nm_a0b0_afe_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* Increase VCO range to prevent unlocking problem of PLL at low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * temp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Change Ki to 011 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* Disable loading of TVCO buffer to bandgap, set bandgap trim
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * to 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* Adjust bias current trim by -3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* Switch to CORE_BASE1E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) bcm_phy_r_rc_cal_reset(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* write AFE_RXCONFIG_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* write AFE_RXCONFIG_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* write AFE_RX_LP_COUNTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* write AFE_HPF_TRIM_OTHERS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* write AFTE_TX_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) EXPORT_SYMBOL_GPL(bcm_phy_28nm_a0b0_afe_config_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int bcm_phy_enable_jumbo(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Enable extended length packet reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ret = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret | MII_BCM54XX_AUXCTL_ACTL_EXT_PKT_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Enable the elastic FIFO for raising the transmission limit from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * 4.5KB to 10KB, at the expense of an additional 16 ns in propagation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * latency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return phy_set_bits(phydev, MII_BCM54XX_ECR, MII_BCM54XX_ECR_FIFOE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) EXPORT_SYMBOL_GPL(bcm_phy_enable_jumbo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static int __bcm_phy_enable_rdb_access(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return __bcm_phy_write_exp(phydev, BCM54XX_EXP_REG7E, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int __bcm_phy_enable_legacy_access(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return __bcm_phy_write_rdb(phydev, BCM54XX_RDB_REG0087,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) BCM54XX_ACCESS_MODE_LEGACY_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static int _bcm_phy_cable_test_start(struct phy_device *phydev, bool is_rdb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u16 mask, set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* Auto-negotiation must be enabled for cable diagnostics to work, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * don't advertise any capabilities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) phy_write(phydev, MII_CTRL1000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) phy_lock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (is_rdb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ret = __bcm_phy_enable_legacy_access(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) mask = BCM54XX_ECD_CTRL_CROSS_SHORT_DIS | BCM54XX_ECD_CTRL_UNIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) set = BCM54XX_ECD_CTRL_RUN | BCM54XX_ECD_CTRL_BREAK_LINK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) FIELD_PREP(BCM54XX_ECD_CTRL_UNIT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) BCM54XX_ECD_CTRL_UNIT_CM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ret = __bcm_phy_modify_exp(phydev, BCM54XX_EXP_ECD_CTRL, mask, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* re-enable the RDB access even if there was an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (is_rdb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ret = __bcm_phy_enable_rdb_access(phydev) ? : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) phy_unlock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int bcm_phy_cable_test_report_trans(int result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) switch (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) case BCM54XX_ECD_FAULT_TYPE_OK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return ETHTOOL_A_CABLE_RESULT_CODE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) case BCM54XX_ECD_FAULT_TYPE_OPEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) case BCM54XX_ECD_FAULT_TYPE_SAME_SHORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) case BCM54XX_ECD_FAULT_TYPE_CROSS_SHORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) case BCM54XX_ECD_FAULT_TYPE_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) case BCM54XX_ECD_FAULT_TYPE_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static bool bcm_phy_distance_valid(int result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) switch (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) case BCM54XX_ECD_FAULT_TYPE_OPEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) case BCM54XX_ECD_FAULT_TYPE_SAME_SHORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) case BCM54XX_ECD_FAULT_TYPE_CROSS_SHORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static int bcm_phy_report_length(struct phy_device *phydev, int pair)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) val = __bcm_phy_read_exp(phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) BCM54XX_EXP_ECD_PAIR_A_LENGTH_RESULTS + pair);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (val == BCM54XX_ECD_LENGTH_RESULTS_INVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ethnl_cable_test_fault_length(phydev, pair, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static int _bcm_phy_cable_test_get_status(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) bool *finished, bool is_rdb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int pair_a, pair_b, pair_c, pair_d, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) *finished = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) phy_lock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (is_rdb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ret = __bcm_phy_enable_legacy_access(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ret = __bcm_phy_read_exp(phydev, BCM54XX_EXP_ECD_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (ret & BCM54XX_ECD_CTRL_IN_PROGRESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ret = __bcm_phy_read_exp(phydev, BCM54XX_EXP_ECD_FAULT_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) pair_a = FIELD_GET(BCM54XX_ECD_FAULT_TYPE_PAIR_A_MASK, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) pair_b = FIELD_GET(BCM54XX_ECD_FAULT_TYPE_PAIR_B_MASK, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) pair_c = FIELD_GET(BCM54XX_ECD_FAULT_TYPE_PAIR_C_MASK, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) pair_d = FIELD_GET(BCM54XX_ECD_FAULT_TYPE_PAIR_D_MASK, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) bcm_phy_cable_test_report_trans(pair_a));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) bcm_phy_cable_test_report_trans(pair_b));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) bcm_phy_cable_test_report_trans(pair_c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) bcm_phy_cable_test_report_trans(pair_d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (bcm_phy_distance_valid(pair_a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) bcm_phy_report_length(phydev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (bcm_phy_distance_valid(pair_b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) bcm_phy_report_length(phydev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (bcm_phy_distance_valid(pair_c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) bcm_phy_report_length(phydev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (bcm_phy_distance_valid(pair_d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) bcm_phy_report_length(phydev, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) *finished = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* re-enable the RDB access even if there was an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (is_rdb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ret = __bcm_phy_enable_rdb_access(phydev) ? : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) phy_unlock_mdio_bus(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) int bcm_phy_cable_test_start(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return _bcm_phy_cable_test_start(phydev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) EXPORT_SYMBOL_GPL(bcm_phy_cable_test_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) int bcm_phy_cable_test_get_status(struct phy_device *phydev, bool *finished)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return _bcm_phy_cable_test_get_status(phydev, finished, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) EXPORT_SYMBOL_GPL(bcm_phy_cable_test_get_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* We assume that all PHYs which support RDB access can be switched to legacy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * mode. If, in the future, this is not true anymore, we have to re-implement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * this with RDB access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) int bcm_phy_cable_test_start_rdb(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return _bcm_phy_cable_test_start(phydev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) EXPORT_SYMBOL_GPL(bcm_phy_cable_test_start_rdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) int bcm_phy_cable_test_get_status_rdb(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) bool *finished)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return _bcm_phy_cable_test_get_status(phydev, finished, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) EXPORT_SYMBOL_GPL(bcm_phy_cable_test_get_status_rdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) MODULE_DESCRIPTION("Broadcom PHY Library");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) MODULE_AUTHOR("Broadcom Corporation");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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