^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /* Broadcom Cygnus SoC internal transceivers support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include "bcm-phy-lib.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/brcmphy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct bcm_omega_phy_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) u64 *stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Broadcom Cygnus Phy specific registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MII_BCM_CYGNUS_AFE_VDAC_ICTRL_0 0x91E5 /* VDAL Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static int bcm_cygnus_afe_config(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* ensure smdspclk is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, 0x0c30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* AFE_VDAC_ICTRL_0 bit 7:4 Iq=1100 for 1g 10bt, normal modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) rc = bcm_phy_write_misc(phydev, 0x39, 0x01, 0xA7C8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* AFE_HPF_TRIM_OTHERS bit11=1, short cascode enable for all modes*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) rc = bcm_phy_write_misc(phydev, 0x3A, 0x00, 0x0803);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* AFE_TX_CONFIG_1 bit 7:4 Iq=1100 for test modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) rc = bcm_phy_write_misc(phydev, 0x3A, 0x01, 0xA740);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* AFE TEMPSEN_OTHERS rcal_HT, rcal_LT 10000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) rc = bcm_phy_write_misc(phydev, 0x3A, 0x03, 0x8400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* AFE_FUTURE_RSV bit 2:0 rccal <2:0>=100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) rc = bcm_phy_write_misc(phydev, 0x3B, 0x00, 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Adjust bias current trim to overcome digital offSet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) rc = phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* make rcal=100, since rdb default is 000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) rc = bcm_phy_write_exp_sel(phydev, MII_BRCM_CORE_EXPB1, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* CORE_EXPB0, Reset R_CAL/RC_CAL Engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) rc = bcm_phy_write_exp_sel(phydev, MII_BRCM_CORE_EXPB0, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* CORE_EXPB0, Disable Reset R_CAL/RC_CAL Engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) rc = bcm_phy_write_exp_sel(phydev, MII_BRCM_CORE_EXPB0, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int bcm_cygnus_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int reg, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) reg = phy_read(phydev, MII_BCM54XX_ECR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Mask interrupts globally. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) reg |= MII_BCM54XX_ECR_IM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) rc = phy_write(phydev, MII_BCM54XX_ECR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Unmask events of interest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) reg = ~(MII_BCM54XX_INT_DUPLEX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MII_BCM54XX_INT_SPEED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MII_BCM54XX_INT_LINK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) rc = phy_write(phydev, MII_BCM54XX_IMR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Apply AFE settings for the PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) rc = bcm_cygnus_afe_config(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Advertise EEE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) rc = bcm_phy_set_eee(phydev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Enable APD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return bcm_phy_enable_apd(phydev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int bcm_cygnus_resume(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) genphy_resume(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Re-initialize the PHY to apply AFE work-arounds and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * configurations when coming out of suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) rc = bcm_cygnus_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* restart auto negotiation with the new settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return genphy_config_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int bcm_omega_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 count, rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pr_info_once("%s: %s PHY revision: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) phydev_name(phydev), phydev->drv->name, rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Dummy read to a register to workaround an issue upon reset where the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * internal inverter may not allow the first MDIO transaction to pass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * the MDIO management controller and make us return 0xffff for such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * reads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) phy_read(phydev, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ret = bcm_phy_28nm_a0b0_afe_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = bcm_phy_downshift_get(phydev, &count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Only enable EEE if Wirespeed/downshift is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return bcm_phy_enable_apd(phydev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int bcm_omega_resume(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Re-apply workarounds coming out suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = bcm_omega_config_init(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* 28nm Gigabit PHYs come out of reset without any half-duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * or "hub" compliant advertised mode, fix that. This does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * cause any problems with the PHY library since genphy_config_aneg()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * gracefully handles auto-negotiated and forced modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return genphy_config_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int bcm_omega_get_tunable(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct ethtool_tunable *tuna, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) switch (tuna->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) case ETHTOOL_PHY_DOWNSHIFT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return bcm_phy_downshift_get(phydev, (u8 *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int bcm_omega_set_tunable(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct ethtool_tunable *tuna,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) const void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 count = *(u8 *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) switch (tuna->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) case ETHTOOL_PHY_DOWNSHIFT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ret = bcm_phy_downshift_set(phydev, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Disable EEE advertisement since this prevents the PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * from successfully linking up, trigger auto-negotiation restart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * to let the MAC decide what to do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return genphy_restart_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void bcm_omega_get_phy_stats(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct ethtool_stats *stats, u64 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct bcm_omega_phy_priv *priv = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) bcm_phy_get_stats(phydev, priv->stats, stats, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int bcm_omega_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct bcm_omega_phy_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) phydev->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) priv->stats = devm_kcalloc(&phydev->mdio.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) bcm_phy_get_sset_count(phydev), sizeof(u64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!priv->stats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static struct phy_driver bcm_cygnus_phy_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .phy_id = PHY_ID_BCM_CYGNUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .name = "Broadcom Cygnus PHY",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .config_init = bcm_cygnus_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .ack_interrupt = bcm_phy_ack_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .config_intr = bcm_phy_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .resume = bcm_cygnus_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .phy_id = PHY_ID_BCM_OMEGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .phy_id_mask = 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .name = "Broadcom Omega Combo GPHY",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* PHY_GBIT_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .flags = PHY_IS_INTERNAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .config_init = bcm_omega_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .suspend = genphy_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .resume = bcm_omega_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .get_tunable = bcm_omega_get_tunable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .set_tunable = bcm_omega_set_tunable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .get_sset_count = bcm_phy_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .get_strings = bcm_phy_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .get_stats = bcm_omega_get_phy_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .probe = bcm_omega_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static struct mdio_device_id __maybe_unused bcm_cygnus_phy_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { PHY_ID_BCM_CYGNUS, 0xfffffff0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { PHY_ID_BCM_OMEGA, 0xfffffff0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MODULE_DEVICE_TABLE(mdio, bcm_cygnus_phy_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) module_phy_driver(bcm_cygnus_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MODULE_DESCRIPTION("Broadcom Cygnus internal PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MODULE_AUTHOR("Broadcom Corporation");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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