^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Aquantia PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Shaohui Xie <Shaohui.Xie@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2015 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "aquantia.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PHY_ID_AQ1202 0x03a1b445
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PHY_ID_AQ2104 0x03a1b460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PHY_ID_AQR105 0x03a1b4a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PHY_ID_AQR106 0x03a1b4d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PHY_ID_AQR107 0x03a1b4e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PHY_ID_AQCS109 0x03a1b5c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PHY_ID_AQR405 0x03a1b4b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MDIO_PHYXS_VEND_IF_STATUS 0xe812
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MDIO_AN_VEND_PROV 0xc400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MDIO_AN_TX_VEND_STATUS1 0xc800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MDIO_AN_TX_VEND_STATUS1_10BASET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MDIO_AN_TX_VEND_INT_MASK2 0xd401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MDIO_AN_RX_LP_STAT1 0xe820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MDIO_AN_RX_LP_STAT4 0xe823
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MDIO_AN_RX_VEND_STAT3 0xe832
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* MDIO_MMD_C22EXT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Vendor specific 1, MDIO_MMD_VEND1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define VEND1_GLOBAL_FW_ID 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define VEND1_GLOBAL_RSVD_STAT1 0xc885
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define VEND1_GLOBAL_RSVD_STAT9 0xc88d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define VEND1_GLOBAL_INT_STD_MASK 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define VEND1_GLOBAL_INT_VEND_MASK 0xff01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct aqr107_hw_stat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct aqr107_hw_stat aqr107_hw_stats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct aqr107_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int aqr107_get_sset_count(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return AQR107_SGMII_STAT_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ETH_GSTRING_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static u64 aqr107_get_stat(struct phy_device *phydev, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) const struct aqr107_hw_stat *stat = aqr107_hw_stats + index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int len_l = min(stat->size, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int len_h = stat->size - len_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u64 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return U64_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = val & GENMASK(len_l - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (len_h) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return U64_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret += (val & GENMASK(len_h - 1, 0)) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static void aqr107_get_stats(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct ethtool_stats *stats, u64 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct aqr107_priv *priv = phydev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) val = aqr107_get_stat(phydev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (val == U64_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) phydev_err(phydev, "Reading HW Statistics failed for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) aqr107_hw_stats[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) priv->sgmii_stats[i] += val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) data[i] = priv->sgmii_stats[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int aqr_config_aneg(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) bool changed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (phydev->autoneg == AUTONEG_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return genphy_c45_pma_setup_forced(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ret = genphy_c45_an_config_aneg(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Clause 45 has no standardized support for 1000BaseT, therefore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * use vendor registers for this mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) phydev->advertising))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) phydev->advertising))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MDIO_AN_VEND_PROV_1000BASET_HALF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MDIO_AN_VEND_PROV_1000BASET_FULL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return genphy_c45_check_and_restart_aneg(phydev, changed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int aqr_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) VEND1_GLOBAL_INT_VEND_MASK_AN : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int aqr_ack_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) reg = phy_read_mmd(phydev, MDIO_MMD_AN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MDIO_AN_TX_VEND_INT_STATUS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return (reg < 0) ? reg : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int aqr_read_status(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (phydev->autoneg == AUTONEG_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) phydev->lp_advertising,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) phydev->lp_advertising,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return genphy_c45_read_status(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int aqr107_read_rate(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case MDIO_AN_TX_VEND_STATUS1_10BASET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) phydev->speed = SPEED_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case MDIO_AN_TX_VEND_STATUS1_100BASETX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) phydev->speed = SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) case MDIO_AN_TX_VEND_STATUS1_1000BASET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) phydev->speed = SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) case MDIO_AN_TX_VEND_STATUS1_2500BASET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) phydev->speed = SPEED_2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case MDIO_AN_TX_VEND_STATUS1_5000BASET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) phydev->speed = SPEED_5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case MDIO_AN_TX_VEND_STATUS1_10GBASET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) phydev->speed = SPEED_10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) phydev->speed = SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) phydev->duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) phydev->duplex = DUPLEX_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int aqr107_read_status(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int val, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ret = aqr_read_status(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) phydev->interface = PHY_INTERFACE_MODE_10GKR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) phydev->interface = PHY_INTERFACE_MODE_10GBASER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) phydev->interface = PHY_INTERFACE_MODE_USXGMII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) phydev->interface = PHY_INTERFACE_MODE_SGMII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) phydev->interface = PHY_INTERFACE_MODE_NA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Read possibly downshifted rate from vendor register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return aqr107_read_rate(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int val, cnt, enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return -E2BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (cnt != DOWNSHIFT_DEV_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int aqr107_get_tunable(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct ethtool_tunable *tuna, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) switch (tuna->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case ETHTOOL_PHY_DOWNSHIFT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return aqr107_get_downshift(phydev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int aqr107_set_tunable(struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct ethtool_tunable *tuna, const void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) switch (tuna->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case ETHTOOL_PHY_DOWNSHIFT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return aqr107_set_downshift(phydev, *(const u8 *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* If we configure settings whilst firmware is still initializing the chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * then these settings may be overwritten. Therefore make sure chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * initialization has completed. Use presence of the firmware ID as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * indicator for initialization having completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * The chip also provides a "reset completed" bit, but it's cleared after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * read. Therefore function would time out if called again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int aqr107_wait_reset_complete(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) VEND1_GLOBAL_FW_ID, val, val != 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 20000, 2000000, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static void aqr107_chip_info(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u8 fw_major, fw_minor, build_id, prov_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) fw_major, fw_minor, build_id, prov_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int aqr107_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Check that the PHY interface type is compatible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) phydev->interface != PHY_INTERFACE_MODE_XGMII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) phydev->interface != PHY_INTERFACE_MODE_10GKR &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) phydev->interface != PHY_INTERFACE_MODE_10GBASER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = aqr107_wait_reset_complete(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) aqr107_chip_info(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int aqcs109_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Check that the PHY interface type is compatible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ret = aqr107_wait_reset_complete(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) aqr107_chip_info(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* AQCS109 belongs to a chip family partially supporting 10G and 5G.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * PMA speed ability bits are the same for all members of the family,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * AQCS109 however supports speeds up to 2.5G only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ret = phy_set_max_speed(phydev, SPEED_2500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static void aqr107_link_change_notify(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u8 fw_major, fw_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) bool downshift, short_reach, afr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int mode, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* call failed or link partner is no Aquantia PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) fw_major, fw_minor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) short_reach ? ", short reach mode" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) downshift ? ", fast-retrain downshift advertised" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) afr ? ", fast reframe advertised" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static int aqr107_suspend(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) MDIO_CTRL1_LPOWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static int aqr107_resume(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MDIO_CTRL1_LPOWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static int aqr107_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) phydev->priv = devm_kzalloc(&phydev->mdio.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) sizeof(struct aqr107_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (!phydev->priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return aqr_hwmon_probe(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static struct phy_driver aqr_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .name = "Aquantia AQ1202",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .config_aneg = aqr_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .config_intr = aqr_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .ack_interrupt = aqr_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .read_status = aqr_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .name = "Aquantia AQ2104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .config_aneg = aqr_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .config_intr = aqr_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .ack_interrupt = aqr_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .read_status = aqr_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .name = "Aquantia AQR105",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .config_aneg = aqr_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .config_intr = aqr_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .ack_interrupt = aqr_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .read_status = aqr_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .suspend = aqr107_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .resume = aqr107_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .name = "Aquantia AQR106",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .config_aneg = aqr_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .config_intr = aqr_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .ack_interrupt = aqr_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .read_status = aqr_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .name = "Aquantia AQR107",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .probe = aqr107_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .config_init = aqr107_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .config_aneg = aqr_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .config_intr = aqr_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .ack_interrupt = aqr_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .read_status = aqr107_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .get_tunable = aqr107_get_tunable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .set_tunable = aqr107_set_tunable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .suspend = aqr107_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .resume = aqr107_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .get_sset_count = aqr107_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .get_strings = aqr107_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .get_stats = aqr107_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .link_change_notify = aqr107_link_change_notify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .name = "Aquantia AQCS109",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .probe = aqr107_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .config_init = aqcs109_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .config_aneg = aqr_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .config_intr = aqr_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .ack_interrupt = aqr_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .read_status = aqr107_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .get_tunable = aqr107_get_tunable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .set_tunable = aqr107_set_tunable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .suspend = aqr107_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .resume = aqr107_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .get_sset_count = aqr107_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .get_strings = aqr107_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .get_stats = aqr107_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .link_change_notify = aqr107_link_change_notify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .name = "Aquantia AQR405",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .config_aneg = aqr_config_aneg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .config_intr = aqr_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .ack_interrupt = aqr_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .read_status = aqr_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) module_phy_driver(aqr_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static struct mdio_device_id __maybe_unused aqr_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) MODULE_DEVICE_TABLE(mdio, aqr_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) MODULE_DESCRIPTION("Aquantia PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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