^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* HWMON driver for Aquantia PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Andrew Lunn <andrew@lunn.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Heiner Kallweit <hkallweit1@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "aquantia.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Vendor specific 1, MDIO_MMD_VEND2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define VEND1_THERMAL_STAT1 0xc820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define VEND1_THERMAL_STAT2 0xc821
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define VEND1_THERMAL_STAT2_VALID BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VEND1_GENERAL_STAT1 0xc830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #if IS_REACHABLE(CONFIG_HWMON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static umode_t aqr_hwmon_is_visible(const void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (type != hwmon_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) case hwmon_temp_min_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) case hwmon_temp_max_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) case hwmon_temp_lcrit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) case hwmon_temp_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) case hwmon_temp_lcrit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) case hwmon_temp_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int aqr_hwmon_get(struct phy_device *phydev, int reg, long *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (temp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* 16 bit value is 2's complement with LSB = 1/256th degree Celsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *value = (s16)temp * 1000 / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int aqr_hwmon_set(struct phy_device *phydev, int reg, long value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (value >= 128000 || value < -128000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) temp = value * 256 / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* temp is in s16 range and we're interested in lower 16 bits only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int aqr_hwmon_test_bit(struct phy_device *phydev, int reg, int bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return !!(val & bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int aqr_hwmon_status1(struct phy_device *phydev, int bit, long *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int val = aqr_hwmon_test_bit(phydev, VEND1_GENERAL_STAT1, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *value = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int aqr_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 attr, int channel, long *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct phy_device *phydev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (type != hwmon_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) reg = aqr_hwmon_test_bit(phydev, VEND1_THERMAL_STAT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) VEND1_THERMAL_STAT2_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return aqr_hwmon_get(phydev, VEND1_THERMAL_STAT1, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case hwmon_temp_lcrit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case hwmon_temp_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) case hwmon_temp_lcrit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return aqr_hwmon_status1(phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) VEND1_GENERAL_STAT1_LOW_TEMP_FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case hwmon_temp_min_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return aqr_hwmon_status1(phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) VEND1_GENERAL_STAT1_LOW_TEMP_WARN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case hwmon_temp_max_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return aqr_hwmon_status1(phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) VEND1_GENERAL_STAT1_HIGH_TEMP_WARN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case hwmon_temp_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return aqr_hwmon_status1(phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int aqr_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 attr, int channel, long value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct phy_device *phydev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (type != hwmon_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) case hwmon_temp_lcrit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case hwmon_temp_min:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case hwmon_temp_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct hwmon_ops aqr_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .is_visible = aqr_hwmon_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .read = aqr_hwmon_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .write = aqr_hwmon_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static u32 aqr_hwmon_chip_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) HWMON_C_REGISTER_TZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct hwmon_channel_info aqr_hwmon_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .type = hwmon_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .config = aqr_hwmon_chip_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static u32 aqr_hwmon_temp_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) HWMON_T_INPUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) HWMON_T_MAX | HWMON_T_MIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) HWMON_T_MAX_ALARM | HWMON_T_MIN_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) HWMON_T_CRIT | HWMON_T_LCRIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) HWMON_T_CRIT_ALARM | HWMON_T_LCRIT_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const struct hwmon_channel_info aqr_hwmon_temp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .type = hwmon_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .config = aqr_hwmon_temp_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const struct hwmon_channel_info *aqr_hwmon_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) &aqr_hwmon_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) &aqr_hwmon_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const struct hwmon_chip_info aqr_hwmon_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .ops = &aqr_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .info = aqr_hwmon_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int aqr_hwmon_probe(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct device *dev = &phydev->mdio.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) char *hwmon_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (!hwmon_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) for (i = j = 0; hwmon_name[i]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (isalnum(hwmon_name[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (i != j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) hwmon_name[j] = hwmon_name[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) hwmon_name[j] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) phydev, &aqr_hwmon_chip_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return PTR_ERR_OR_ZERO(hwmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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