Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Driver for AMD am79c PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Author: Heiko Schocher <hs@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (c) 2011 DENX Software Engineering GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PHY_ID_AM79C874		0x0022561b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MII_AM79C_IR		17	/* Interrupt Status/Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MII_AM79C_IR_EN_LINK	0x0400	/* IR enable Linkstate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MII_AM79C_IR_EN_ANEG	0x0100	/* IR enable Aneg Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MII_AM79C_IR_IMASK_INIT	(MII_AM79C_IR_EN_LINK | MII_AM79C_IR_EN_ANEG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MODULE_DESCRIPTION("AMD PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MODULE_AUTHOR("Heiko Schocher <hs@denx.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static int am79c_ack_interrupt(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	err = phy_read(phydev, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	err = phy_read(phydev, MII_AM79C_IR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int am79c_config_init(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int am79c_config_intr(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		err = phy_write(phydev, MII_AM79C_IR, MII_AM79C_IR_IMASK_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		err = phy_write(phydev, MII_AM79C_IR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static struct phy_driver am79c_driver[] = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	.phy_id		= PHY_ID_AM79C874,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	.name		= "AM79C874",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	.phy_id_mask	= 0xfffffff0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	/* PHY_BASIC_FEATURES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	.config_init	= am79c_config_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	.ack_interrupt	= am79c_ack_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	.config_intr	= am79c_config_intr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) module_phy_driver(am79c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct mdio_device_id __maybe_unused amd_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	{ PHY_ID_AM79C874, 0xfffffff0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MODULE_DEVICE_TABLE(mdio, amd_tbl);