Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Copyright 2020 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Lynx PCS MDIO helpers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/phylink.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/pcs-lynx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define SGMII_CLOCK_PERIOD_NS		8 /* PCS is clocked at 125 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define LINK_TIMER_VAL(ns)		((u32)((ns) / SGMII_CLOCK_PERIOD_NS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define SGMII_AN_LINK_TIMER_NS		1600000 /* defined by SGMII spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define LINK_TIMER_LO			0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define LINK_TIMER_HI			0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define IF_MODE				0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define IF_MODE_SGMII_EN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define IF_MODE_USE_SGMII_AN		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define IF_MODE_SPEED(x)		(((x) << 2) & GENMASK(3, 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define IF_MODE_SPEED_MSK		GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define IF_MODE_HALF_DUPLEX		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) enum sgmii_speed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	SGMII_SPEED_10		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	SGMII_SPEED_100		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	SGMII_SPEED_1000	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	SGMII_SPEED_2500	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define phylink_pcs_to_lynx(pl_pcs) container_of((pl_pcs), struct lynx_pcs, pcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static void lynx_pcs_get_state_usxgmii(struct mdio_device *pcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 				       struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct mii_bus *bus = pcs->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	int addr = pcs->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	int status, lpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	status = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	state->link = !!(status & MDIO_STAT1_LSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	state->an_complete = !!(status & MDIO_AN_STAT1_COMPLETE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	if (!state->link || !state->an_complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	lpa = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_LPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	if (lpa < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	phylink_decode_usxgmii_word(state, lpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static void lynx_pcs_get_state_2500basex(struct mdio_device *pcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 					 struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct mii_bus *bus = pcs->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	int addr = pcs->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	int bmsr, lpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	bmsr = mdiobus_read(bus, addr, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	lpa = mdiobus_read(bus, addr, MII_LPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	if (bmsr < 0 || lpa < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		state->link = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	state->link = !!(bmsr & BMSR_LSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	if (!state->link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	state->speed = SPEED_2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	state->pause |= MLO_PAUSE_TX | MLO_PAUSE_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	state->duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static void lynx_pcs_get_state(struct phylink_pcs *pcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			       struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	switch (state->interface) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	case PHY_INTERFACE_MODE_SGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	case PHY_INTERFACE_MODE_QSGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		phylink_mii_c22_pcs_get_state(lynx->mdio, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	case PHY_INTERFACE_MODE_2500BASEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		lynx_pcs_get_state_2500basex(lynx->mdio, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	case PHY_INTERFACE_MODE_USXGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		lynx_pcs_get_state_usxgmii(lynx->mdio, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	case PHY_INTERFACE_MODE_10GBASER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		phylink_mii_c45_pcs_get_state(lynx->mdio, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	dev_dbg(&lynx->mdio->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		"mode=%s/%s/%s link=%u an_enabled=%u an_complete=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		phy_modes(state->interface),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		phy_speed_to_str(state->speed),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		phy_duplex_to_str(state->duplex),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		state->link, state->an_enabled, state->an_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int lynx_pcs_config_sgmii(struct mdio_device *pcs, unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 				 const unsigned long *advertising)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct mii_bus *bus = pcs->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	int addr = pcs->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u16 if_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if_mode = IF_MODE_SGMII_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (mode == MLO_AN_INBAND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		u32 link_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		if_mode |= IF_MODE_USE_SGMII_AN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		/* Adjust link timer for SGMII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		link_timer = LINK_TIMER_VAL(SGMII_AN_LINK_TIMER_NS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		mdiobus_write(bus, addr, LINK_TIMER_LO, link_timer & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		mdiobus_write(bus, addr, LINK_TIMER_HI, link_timer >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	err = mdiobus_modify(bus, addr, IF_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			     IF_MODE_SGMII_EN | IF_MODE_USE_SGMII_AN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			     if_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return phylink_mii_c22_pcs_config(pcs, mode, PHY_INTERFACE_MODE_SGMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 					 advertising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int lynx_pcs_config_usxgmii(struct mdio_device *pcs, unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 				   const unsigned long *advertising)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct mii_bus *bus = pcs->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	int addr = pcs->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (!phylink_autoneg_inband(mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		dev_err(&pcs->dev, "USXGMII only supports in-band AN for now\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* Configure device ability for the USXGMII Replicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	return mdiobus_c45_write(bus, addr, MDIO_MMD_VEND2, MII_ADVERTISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 				 MDIO_USXGMII_10G | MDIO_USXGMII_LINK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 				 MDIO_USXGMII_FULL_DUPLEX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 				 ADVERTISE_SGMII | ADVERTISE_LPACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int lynx_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			   phy_interface_t ifmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			   const unsigned long *advertising,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			   bool permit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	switch (ifmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	case PHY_INTERFACE_MODE_SGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	case PHY_INTERFACE_MODE_QSGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		return lynx_pcs_config_sgmii(lynx->mdio, mode, advertising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	case PHY_INTERFACE_MODE_2500BASEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		if (phylink_autoneg_inband(mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			dev_err(&lynx->mdio->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 				"AN not supported on 3.125GHz SerDes lane\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	case PHY_INTERFACE_MODE_USXGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		return lynx_pcs_config_usxgmii(lynx->mdio, mode, advertising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	case PHY_INTERFACE_MODE_10GBASER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		/* Nothing to do here for 10GBASER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void lynx_pcs_link_up_sgmii(struct mdio_device *pcs, unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 				   int speed, int duplex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	struct mii_bus *bus = pcs->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	u16 if_mode = 0, sgmii_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	int addr = pcs->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* The PCS needs to be configured manually only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 * when not operating on in-band mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (mode == MLO_AN_INBAND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (duplex == DUPLEX_HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		if_mode |= IF_MODE_HALF_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	switch (speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	case SPEED_1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		sgmii_speed = SGMII_SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	case SPEED_100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		sgmii_speed = SGMII_SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	case SPEED_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		sgmii_speed = SGMII_SPEED_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	case SPEED_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		/* Silently don't do anything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		dev_err(&pcs->dev, "Invalid PCS speed %d\n", speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if_mode |= IF_MODE_SPEED(sgmii_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	mdiobus_modify(bus, addr, IF_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		       IF_MODE_HALF_DUPLEX | IF_MODE_SPEED_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		       if_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* 2500Base-X is SerDes protocol 7 on Felix and 6 on ENETC. It is a SerDes lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  * clocked at 3.125 GHz which encodes symbols with 8b/10b and does not have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  * auto-negotiation of any link parameters. Electrically it is compatible with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)  * a single lane of XAUI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)  * The hardware reference manual wants to call this mode SGMII, but it isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  * really, since the fundamental features of SGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  * - Downgrading the link speed by duplicating symbols
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  * - Auto-negotiation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  * are not there.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  * The speed is configured at 1000 in the IF_MODE because the clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  * is actually given by a PLL configured in the Reset Configuration Word (RCW).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  * Since there is no difference between fixed speed SGMII w/o AN and 802.3z w/o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  * AN, we call this PHY interface type 2500Base-X. In case a PHY negotiates a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  * lower link speed on line side, the system-side interface remains fixed at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  * 2500 Mbps and we do rate adaptation through pause frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void lynx_pcs_link_up_2500basex(struct mdio_device *pcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 				       unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 				       int speed, int duplex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	struct mii_bus *bus = pcs->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	int addr = pcs->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	u16 if_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (mode == MLO_AN_INBAND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		dev_err(&pcs->dev, "AN not supported for 2500BaseX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (duplex == DUPLEX_HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		if_mode |= IF_MODE_HALF_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if_mode |= IF_MODE_SPEED(SGMII_SPEED_2500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	mdiobus_modify(bus, addr, IF_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		       IF_MODE_HALF_DUPLEX | IF_MODE_SPEED_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		       if_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void lynx_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			     phy_interface_t interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			     int speed, int duplex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	switch (interface) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	case PHY_INTERFACE_MODE_SGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	case PHY_INTERFACE_MODE_QSGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		lynx_pcs_link_up_sgmii(lynx->mdio, mode, speed, duplex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	case PHY_INTERFACE_MODE_2500BASEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		lynx_pcs_link_up_2500basex(lynx->mdio, mode, speed, duplex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	case PHY_INTERFACE_MODE_USXGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		/* At the moment, only in-band AN is supported for USXGMII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		 * so nothing to do in link_up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const struct phylink_pcs_ops lynx_pcs_phylink_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.pcs_get_state = lynx_pcs_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.pcs_config = lynx_pcs_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.pcs_link_up = lynx_pcs_link_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct lynx_pcs *lynx_pcs_create(struct mdio_device *mdio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct lynx_pcs *lynx_pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	lynx_pcs = kzalloc(sizeof(*lynx_pcs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (!lynx_pcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	lynx_pcs->mdio = mdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	lynx_pcs->pcs.ops = &lynx_pcs_phylink_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	lynx_pcs->pcs.poll = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	return lynx_pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) EXPORT_SYMBOL(lynx_pcs_create);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) void lynx_pcs_destroy(struct lynx_pcs *pcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	kfree(pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) EXPORT_SYMBOL(lynx_pcs_destroy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MODULE_LICENSE("Dual BSD/GPL");