Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Applied Micro X-Gene SoC MDIO Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2016, Applied Micro Circuits Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Iyappan Subramanian <isubramanian@apm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/efi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/if_vlan.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mdio/mdio-xgene.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_net.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/prefetch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <net/ip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static bool xgene_mdio_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) u32 xgene_mdio_rd_mac(struct xgene_mdio_pdata *pdata, u32 rd_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	void __iomem *addr, *rd, *cmd, *cmd_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	u32 done, rd_data = BUSY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u8 wait = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	addr = pdata->mac_csr_addr + MAC_ADDR_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	rd = pdata->mac_csr_addr + MAC_READ_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	cmd = pdata->mac_csr_addr + MAC_COMMAND_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	cmd_done = pdata->mac_csr_addr + MAC_COMMAND_DONE_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	spin_lock(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	iowrite32(rd_addr, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	iowrite32(XGENE_ENET_RD_CMD, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	while (!(done = ioread32(cmd_done)) && wait--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	if (done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		rd_data = ioread32(rd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	iowrite32(0, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	spin_unlock(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	return rd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) EXPORT_SYMBOL(xgene_mdio_rd_mac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) void xgene_mdio_wr_mac(struct xgene_mdio_pdata *pdata, u32 wr_addr, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	void __iomem *addr, *wr, *cmd, *cmd_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u8 wait = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u32 done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	addr = pdata->mac_csr_addr + MAC_ADDR_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	wr = pdata->mac_csr_addr + MAC_WRITE_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	cmd = pdata->mac_csr_addr + MAC_COMMAND_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	cmd_done = pdata->mac_csr_addr + MAC_COMMAND_DONE_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	spin_lock(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	iowrite32(wr_addr, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	iowrite32(data, wr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	iowrite32(XGENE_ENET_WR_CMD, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	while (!(done = ioread32(cmd_done)) && wait--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	if (!done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		pr_err("MCX mac write failed, addr: 0x%04x\n", wr_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	iowrite32(0, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	spin_unlock(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) EXPORT_SYMBOL(xgene_mdio_wr_mac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) int xgene_mdio_rgmii_read(struct mii_bus *bus, int phy_id, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct xgene_mdio_pdata *pdata = (struct xgene_mdio_pdata *)bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u32 data, done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u8 wait = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	data = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	xgene_mdio_wr_mac(pdata, MII_MGMT_ADDRESS_ADDR, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	xgene_mdio_wr_mac(pdata, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		usleep_range(5, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		done = xgene_mdio_rd_mac(pdata, MII_MGMT_INDICATORS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	} while ((done & BUSY_MASK) && wait--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	if (done & BUSY_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		dev_err(&bus->dev, "MII_MGMT read failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	data = xgene_mdio_rd_mac(pdata, MII_MGMT_STATUS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	xgene_mdio_wr_mac(pdata, MII_MGMT_COMMAND_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) EXPORT_SYMBOL(xgene_mdio_rgmii_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int xgene_mdio_rgmii_write(struct mii_bus *bus, int phy_id, int reg, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct xgene_mdio_pdata *pdata = (struct xgene_mdio_pdata *)bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	u32 val, done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	u8 wait = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	val = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	xgene_mdio_wr_mac(pdata, MII_MGMT_ADDRESS_ADDR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	xgene_mdio_wr_mac(pdata, MII_MGMT_CONTROL_ADDR, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		usleep_range(5, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		done = xgene_mdio_rd_mac(pdata, MII_MGMT_INDICATORS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	} while ((done & BUSY_MASK) && wait--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (done & BUSY_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		dev_err(&bus->dev, "MII_MGMT write failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) EXPORT_SYMBOL(xgene_mdio_rgmii_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static u32 xgene_menet_rd_diag_csr(struct xgene_mdio_pdata *pdata, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	return ioread32(pdata->diag_csr_addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void xgene_menet_wr_diag_csr(struct xgene_mdio_pdata *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 				    u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	iowrite32(val, pdata->diag_csr_addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int xgene_enet_ecc_init(struct xgene_mdio_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	u8 wait = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	xgene_menet_wr_diag_csr(pdata, MENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		usleep_range(100, 110);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		data = xgene_menet_rd_diag_csr(pdata, MENET_BLOCK_MEM_RDY_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	} while ((data != 0xffffffff) && wait--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (data != 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		dev_err(pdata->dev, "Failed to release memory from shutdown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void xgene_gmac_reset(struct xgene_mdio_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	xgene_mdio_wr_mac(pdata, MAC_CONFIG_1_ADDR, SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	xgene_mdio_wr_mac(pdata, MAC_CONFIG_1_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int xgene_mdio_reset(struct xgene_mdio_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (pdata->dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		clk_prepare_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		clk_disable_unprepare(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		clk_prepare_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		acpi_evaluate_object(ACPI_HANDLE(pdata->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 				     "_RST", NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	ret = xgene_enet_ecc_init(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		if (pdata->dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			clk_disable_unprepare(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	xgene_gmac_reset(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void xgene_enet_rd_mdio_csr(void __iomem *base_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 				   u32 offset, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	void __iomem *addr = base_addr  + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	*val = ioread32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void xgene_enet_wr_mdio_csr(void __iomem *base_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				   u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	void __iomem *addr = base_addr  + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	iowrite32(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int xgene_xfi_mdio_write(struct mii_bus *bus, int phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 				int reg, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	void __iomem *addr = (void __iomem *)bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	int timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	u32 status, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	val = SET_VAL(HSTPHYADX, phy_id) | SET_VAL(HSTREGADX, reg) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	      SET_VAL(HSTMIIMWRDAT, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	xgene_enet_wr_mdio_csr(addr, MIIM_FIELD_ADDR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	val = HSTLDCMD | SET_VAL(HSTMIIMCMD, MIIM_CMD_LEGACY_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	xgene_enet_wr_mdio_csr(addr, MIIM_COMMAND_ADDR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		usleep_range(5, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		xgene_enet_rd_mdio_csr(addr, MIIM_INDICATOR_ADDR, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	} while ((status & BUSY_MASK) && timeout--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	xgene_enet_wr_mdio_csr(addr, MIIM_COMMAND_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int xgene_xfi_mdio_read(struct mii_bus *bus, int phy_id, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	void __iomem *addr = (void __iomem *)bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	u32 data, status, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	int timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	val = SET_VAL(HSTPHYADX, phy_id) | SET_VAL(HSTREGADX, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	xgene_enet_wr_mdio_csr(addr, MIIM_FIELD_ADDR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	val = HSTLDCMD | SET_VAL(HSTMIIMCMD, MIIM_CMD_LEGACY_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	xgene_enet_wr_mdio_csr(addr, MIIM_COMMAND_ADDR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		usleep_range(5, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		xgene_enet_rd_mdio_csr(addr, MIIM_INDICATOR_ADDR, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	} while ((status & BUSY_MASK) && timeout--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (status & BUSY_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		pr_err("XGENET_MII_MGMT write failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	xgene_enet_rd_mdio_csr(addr, MIIMRD_FIELD_ADDR, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	xgene_enet_wr_mdio_csr(addr, MIIM_COMMAND_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct phy_device *xgene_enet_phy_register(struct mii_bus *bus, int phy_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	struct phy_device *phy_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	phy_dev = get_phy_device(bus, phy_addr, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (!phy_dev || IS_ERR(phy_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (phy_device_register(phy_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		phy_device_free(phy_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	return phy_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) EXPORT_SYMBOL(xgene_enet_phy_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static acpi_status acpi_register_phy(acpi_handle handle, u32 lvl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 				     void *context, void **ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct mii_bus *mdio = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct acpi_device *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	struct phy_device *phy_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	const union acpi_object *obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	u32 phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	if (acpi_bus_get_device(handle, &adev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		return AE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (acpi_dev_get_property(adev, "phy-channel", ACPI_TYPE_INTEGER, &obj))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		return AE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	phy_addr = obj->integer.value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	phy_dev = xgene_enet_phy_register(mdio, phy_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	adev->driver_data = phy_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	return AE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct of_device_id xgene_mdio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		.compatible = "apm,xgene-mdio-rgmii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		.data = (void *)XGENE_MDIO_RGMII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		.compatible = "apm,xgene-mdio-xfi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		.data = (void *)XGENE_MDIO_XFI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MODULE_DEVICE_TABLE(of, xgene_mdio_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const struct acpi_device_id xgene_mdio_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	{ "APMC0D65", XGENE_MDIO_RGMII },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	{ "APMC0D66", XGENE_MDIO_XFI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MODULE_DEVICE_TABLE(acpi, xgene_mdio_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int xgene_mdio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	struct mii_bus *mdio_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	struct xgene_mdio_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	void __iomem *csr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	int mdio_id = 0, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	of_id = of_match_device(xgene_mdio_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (of_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		mdio_id = (enum xgene_mdio_id)of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		const struct acpi_device_id *acpi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		acpi_id = acpi_match_device(xgene_mdio_acpi_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		if (acpi_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			mdio_id = (enum xgene_mdio_id)acpi_id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	if (!mdio_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	pdata = devm_kzalloc(dev, sizeof(struct xgene_mdio_pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	pdata->mdio_id = mdio_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	pdata->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	csr_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (IS_ERR(csr_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		return PTR_ERR(csr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	pdata->mac_csr_addr = csr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	pdata->mdio_csr_addr = csr_base + BLOCK_XG_MDIO_CSR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	pdata->diag_csr_addr = csr_base + BLOCK_DIAG_CSR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	if (mdio_id == XGENE_MDIO_RGMII)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		spin_lock_init(&pdata->mac_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	if (dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		pdata->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		if (IS_ERR(pdata->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 			dev_err(dev, "Unable to retrieve clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 			return PTR_ERR(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	ret = xgene_mdio_reset(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	mdio_bus = mdiobus_alloc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	if (!mdio_bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	mdio_bus->name = "APM X-Gene MDIO bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	if (mdio_id == XGENE_MDIO_RGMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		mdio_bus->read = xgene_mdio_rgmii_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		mdio_bus->write = xgene_mdio_rgmii_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		mdio_bus->priv = (void __force *)pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 			 "xgene-mii-rgmii");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		mdio_bus->read = xgene_xfi_mdio_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		mdio_bus->write = xgene_xfi_mdio_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		mdio_bus->priv = (void __force *)pdata->mdio_csr_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 			 "xgene-mii-xfi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	mdio_bus->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	platform_set_drvdata(pdev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	if (dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		ret = of_mdiobus_register(mdio_bus, dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		/* Mask out all PHYs from auto probing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		mdio_bus->phy_mask = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		ret = mdiobus_register(mdio_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 			goto out_mdiobus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_HANDLE(dev), 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 				    acpi_register_phy, NULL, mdio_bus, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		goto out_mdiobus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	pdata->mdio_bus = mdio_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	xgene_mdio_status = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) out_mdiobus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	mdiobus_free(mdio_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) out_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	if (dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		clk_disable_unprepare(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int xgene_mdio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	struct xgene_mdio_pdata *pdata = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	struct mii_bus *mdio_bus = pdata->mdio_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	mdiobus_unregister(mdio_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	mdiobus_free(mdio_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	if (dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		clk_disable_unprepare(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static struct platform_driver xgene_mdio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		.name = "xgene-mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		.of_match_table = of_match_ptr(xgene_mdio_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		.acpi_match_table = ACPI_PTR(xgene_mdio_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	.probe = xgene_mdio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	.remove = xgene_mdio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) module_platform_driver(xgene_mdio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MODULE_DESCRIPTION("APM X-Gene SoC MDIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MODULE_AUTHOR("Iyappan Subramanian <isubramanian@apm.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MODULE_LICENSE("GPL");