^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Allwinner EMAC MDIO interface driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2012-2013 Stefan Roese <sr@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on the Linux driver provided by Allwinner:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1997 Sten Wang
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EMAC_MAC_MCMD_REG (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EMAC_MAC_MADR_REG (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EMAC_MAC_MWTD_REG (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EMAC_MAC_MRDD_REG (0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EMAC_MAC_MIND_REG (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define EMAC_MAC_SSRR_REG (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MDIO_TIMEOUT (msecs_to_jiffies(100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct sun4i_mdio_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct regulator *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int sun4i_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct sun4i_mdio_data *data = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long timeout_jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* issue the phy address and reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* pull up the phy io line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) writel(0x1, data->membase + EMAC_MAC_MCMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Wait read complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) timeout_jiffies = jiffies + MDIO_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (time_is_before_jiffies(timeout_jiffies))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* push down the phy io line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) writel(0x0, data->membase + EMAC_MAC_MCMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* and read data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) value = readl(data->membase + EMAC_MAC_MRDD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int sun4i_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct sun4i_mdio_data *data = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long timeout_jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* issue the phy address and reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* pull up the phy io line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) writel(0x1, data->membase + EMAC_MAC_MCMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Wait read complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) timeout_jiffies = jiffies + MDIO_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (time_is_before_jiffies(timeout_jiffies))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* push down the phy io line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) writel(0x0, data->membase + EMAC_MAC_MCMD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* and write data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) writel(value, data->membase + EMAC_MAC_MWTD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int sun4i_mdio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct mii_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct sun4i_mdio_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) bus = mdiobus_alloc_size(sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (!bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) bus->name = "sun4i_mii_bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) bus->read = &sun4i_mdio_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) bus->write = &sun4i_mdio_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) bus->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) data = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) data->membase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (IS_ERR(data->membase)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = PTR_ERR(data->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) goto err_out_free_mdiobus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) data->regulator = devm_regulator_get(&pdev->dev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (IS_ERR(data->regulator)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (PTR_ERR(data->regulator) == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) goto err_out_free_mdiobus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_info(&pdev->dev, "no regulator found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) data->regulator = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ret = regulator_enable(data->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) goto err_out_free_mdiobus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ret = of_mdiobus_register(bus, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) goto err_out_disable_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) platform_set_drvdata(pdev, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) err_out_disable_regulator:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (data->regulator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) regulator_disable(data->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) err_out_free_mdiobus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mdiobus_free(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int sun4i_mdio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct mii_bus *bus = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct sun4i_mdio_data *data = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) mdiobus_unregister(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (data->regulator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) regulator_disable(data->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) mdiobus_free(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct of_device_id sun4i_mdio_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { .compatible = "allwinner,sun4i-a10-mdio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { .compatible = "allwinner,sun4i-mdio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MODULE_DEVICE_TABLE(of, sun4i_mdio_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static struct platform_driver sun4i_mdio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .probe = sun4i_mdio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .remove = sun4i_mdio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .name = "sun4i-mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .of_match_table = sun4i_mdio_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) module_platform_driver(sun4i_mdio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MODULE_DESCRIPTION("Allwinner EMAC MDIO interface driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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