^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Simple memory-mapped device MDIO MUX driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Timur Tabi <timur@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2012 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mdio-mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct mdio_mux_mmioreg_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) void *mux_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) phys_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) unsigned int iosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * MDIO multiplexing switch function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * This function is called by the mdio-mux layer when it thinks the mdio bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * multiplexer needs to switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * 'current_child' is the current value of the mux register (masked via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * s->mask).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * 'desired_child' is the value of the 'reg' property of the target child MDIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * The first time this function is called, current_child == -1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * If current_child == desired_child, then the mux is already set to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * correct bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int mdio_mux_mmioreg_switch_fn(int current_child, int desired_child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct mdio_mux_mmioreg_state *s = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (current_child ^ desired_child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void __iomem *p = ioremap(s->phys, s->iosize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) switch (s->iosize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) case sizeof(uint8_t): {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) uint8_t x, y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) x = ioread8(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) y = (x & ~s->mask) | desired_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (x != y) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) iowrite8((x & ~s->mask) | desired_child, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pr_debug("%s: %02x -> %02x\n", __func__, x, y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) case sizeof(uint16_t): {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) uint16_t x, y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) x = ioread16(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) y = (x & ~s->mask) | desired_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (x != y) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) iowrite16((x & ~s->mask) | desired_child, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pr_debug("%s: %04x -> %04x\n", __func__, x, y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) case sizeof(uint32_t): {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) uint32_t x, y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) x = ioread32(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) y = (x & ~s->mask) | desired_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (x != y) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) iowrite32((x & ~s->mask) | desired_child, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pr_debug("%s: %08x -> %08x\n", __func__, x, y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) iounmap(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int mdio_mux_mmioreg_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct device_node *np2, *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct mdio_mux_mmioreg_state *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const __be32 *iprop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int len, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dev_dbg(&pdev->dev, "probing node %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (!s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ret = of_address_to_resource(np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dev_err(&pdev->dev, "could not obtain memory map for node %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) s->phys = res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) s->iosize = resource_size(&res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (s->iosize != sizeof(uint8_t) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) s->iosize != sizeof(uint16_t) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) s->iosize != sizeof(uint32_t)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_err(&pdev->dev, "only 8/16/32-bit registers are supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) iprop = of_get_property(np, "mux-mask", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (!iprop || len != sizeof(uint32_t)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dev_err(&pdev->dev, "missing or invalid mux-mask property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (be32_to_cpup(iprop) >= BIT(s->iosize * 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dev_err(&pdev->dev, "only 8/16/32-bit registers are supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) s->mask = be32_to_cpup(iprop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Verify that the 'reg' property of each child MDIO bus does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * set any bits outside of the 'mask'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) for_each_available_child_of_node(np, np2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) iprop = of_get_property(np2, "reg", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (!iprop || len != sizeof(uint32_t)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dev_err(&pdev->dev, "mdio-mux child node %pOF is "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "missing a 'reg' property\n", np2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) of_node_put(np2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (be32_to_cpup(iprop) & ~s->mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev_err(&pdev->dev, "mdio-mux child node %pOF has "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "a 'reg' value with unmasked bits\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) np2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) of_node_put(np2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = mdio_mux_init(&pdev->dev, pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mdio_mux_mmioreg_switch_fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) &s->mux_handle, s, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "failed to register mdio-mux bus %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) pdev->dev.platform_data = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int mdio_mux_mmioreg_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct mdio_mux_mmioreg_state *s = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) mdio_mux_uninit(s->mux_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct of_device_id mdio_mux_mmioreg_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .compatible = "mdio-mux-mmioreg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MODULE_DEVICE_TABLE(of, mdio_mux_mmioreg_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static struct platform_driver mdio_mux_mmioreg_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .name = "mdio-mux-mmioreg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .of_match_table = mdio_mux_mmioreg_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .probe = mdio_mux_mmioreg_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .remove = mdio_mux_mmioreg_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) module_platform_driver(mdio_mux_mmioreg_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MODULE_DESCRIPTION("Memory-mapped device MDIO MUX driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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