^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (c) 2019 Baylibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mdio-mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ETH_PLL_STS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ETH_PLL_CTL0 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PLL_CTL0_LOCK_DIG BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PLL_CTL0_RST BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PLL_CTL0_EN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PLL_CTL0_SEL BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PLL_CTL0_N GENMASK(14, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PLL_CTL0_M GENMASK(8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PLL_LOCK_TIMEOUT 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PLL_MUX_NUM_PARENT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ETH_PLL_CTL1 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ETH_PLL_CTL2 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ETH_PLL_CTL3 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ETH_PLL_CTL4 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ETH_PLL_CTL5 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ETH_PLL_CTL6 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ETH_PLL_CTL7 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ETH_PHY_CNTL0 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EPHY_G12A_ID 0x33010180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ETH_PHY_CNTL1 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PHY_CNTL1_ST_MODE GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PHY_CNTL1_ST_PHYADD GENMASK(7, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EPHY_DFLT_ADD 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PHY_CNTL1_MII_MODE GENMASK(15, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EPHY_MODE_RMII 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PHY_CNTL1_CLK_EN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PHY_CNTL1_CLKFREQ BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PHY_CNTL1_PHY_ENB BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ETH_PHY_CNTL2 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PHY_CNTL2_USE_INTERNAL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PHY_CNTL2_SMI_SRC_MAC BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PHY_CNTL2_RX_CLK_EPHY BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MESON_G12A_MDIO_EXTERNAL_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MESON_G12A_MDIO_INTERNAL_ID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct g12a_mdio_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) bool pll_is_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) void *mux_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct clk *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct g12a_ephy_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define g12a_ephy_pll_to_dev(_hw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) container_of(_hw, struct g12a_ephy_pll, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static unsigned long g12a_ephy_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 val, m, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) val = readl(pll->base + ETH_PLL_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) m = FIELD_GET(PLL_CTL0_M, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) n = FIELD_GET(PLL_CTL0_N, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return parent_rate * m / n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int g12a_ephy_pll_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 val = readl(pll->base + ETH_PLL_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Apply both enable an reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) val |= PLL_CTL0_RST | PLL_CTL0_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) writel(val, pll->base + ETH_PLL_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Clear the reset to let PLL lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) val &= ~PLL_CTL0_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writel(val, pll->base + ETH_PLL_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Poll on the digital lock instead of the usual analog lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * This is done because bit 31 is unreliable on some SoC. Bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * 31 may indicate that the PLL is not lock eventhough the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * is actually running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) val & PLL_CTL0_LOCK_DIG, 0, PLL_LOCK_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void g12a_ephy_pll_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) val = readl(pll->base + ETH_PLL_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) val &= ~PLL_CTL0_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) val |= PLL_CTL0_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel(val, pll->base + ETH_PLL_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int g12a_ephy_pll_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) val = readl(pll->base + ETH_PLL_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return (val & PLL_CTL0_LOCK_DIG) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int g12a_ephy_pll_init(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Apply PLL HW settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writel(0x29c0040a, pll->base + ETH_PLL_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) writel(0x927e0000, pll->base + ETH_PLL_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) writel(0xac5f49e5, pll->base + ETH_PLL_CTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) writel(0x00000000, pll->base + ETH_PLL_CTL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writel(0x00000000, pll->base + ETH_PLL_CTL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) writel(0x20200000, pll->base + ETH_PLL_CTL5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) writel(0x0000c002, pll->base + ETH_PLL_CTL6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) writel(0x00000023, pll->base + ETH_PLL_CTL7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const struct clk_ops g12a_ephy_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .recalc_rate = g12a_ephy_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .is_enabled = g12a_ephy_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .enable = g12a_ephy_pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .disable = g12a_ephy_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .init = g12a_ephy_pll_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int g12a_enable_internal_mdio(struct g12a_mdio_mux *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Enable the phy clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (!priv->pll_is_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = clk_prepare_enable(priv->pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) priv->pll_is_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Initialize ephy control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) writel(EPHY_G12A_ID, priv->regs + ETH_PHY_CNTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) writel(FIELD_PREP(PHY_CNTL1_ST_MODE, 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) FIELD_PREP(PHY_CNTL1_ST_PHYADD, EPHY_DFLT_ADD) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) FIELD_PREP(PHY_CNTL1_MII_MODE, EPHY_MODE_RMII) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PHY_CNTL1_CLK_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PHY_CNTL1_CLKFREQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PHY_CNTL1_PHY_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) priv->regs + ETH_PHY_CNTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) writel(PHY_CNTL2_USE_INTERNAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PHY_CNTL2_SMI_SRC_MAC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PHY_CNTL2_RX_CLK_EPHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) priv->regs + ETH_PHY_CNTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int g12a_enable_external_mdio(struct g12a_mdio_mux *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Reset the mdio bus mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) writel_relaxed(0x0, priv->regs + ETH_PHY_CNTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Disable the phy clock if enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (priv->pll_is_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) clk_disable_unprepare(priv->pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) priv->pll_is_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int g12a_mdio_switch_fn(int current_child, int desired_child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct g12a_mdio_mux *priv = dev_get_drvdata(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (current_child == desired_child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) switch (desired_child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) case MESON_G12A_MDIO_EXTERNAL_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return g12a_enable_external_mdio(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) case MESON_G12A_MDIO_INTERNAL_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return g12a_enable_internal_mdio(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const struct of_device_id g12a_mdio_mux_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { .compatible = "amlogic,g12a-mdio-mux", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MODULE_DEVICE_TABLE(of, g12a_mdio_mux_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int g12a_ephy_glue_clk_register(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct g12a_mdio_mux *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) const char *parent_names[PLL_MUX_NUM_PARENT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct g12a_ephy_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct clk_mux *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* get the mux parents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) for (i = 0; i < PLL_MUX_NUM_PARENT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) char in_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) snprintf(in_name, sizeof(in_name), "clkin%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) clk = devm_clk_get(dev, in_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (PTR_ERR(clk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_err(dev, "Missing clock %s\n", in_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) parent_names[i] = __clk_get_name(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* create the input mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) name = kasprintf(GFP_KERNEL, "%s#mux", dev_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) init.ops = &clk_mux_ro_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) init.num_parents = PLL_MUX_NUM_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mux->reg = priv->regs + ETH_PLL_CTL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mux->shift = __ffs(PLL_CTL0_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) mux->mask = PLL_CTL0_SEL >> mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) mux->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) clk = devm_clk_register(dev, &mux->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) kfree(name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev_err(dev, "failed to register input mux\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* create the pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (!pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) name = kasprintf(GFP_KERNEL, "%s#pll", dev_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (!name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) init.ops = &g12a_ephy_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) parent_names[0] = __clk_get_name(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) pll->base = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) pll->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) clk = devm_clk_register(dev, &pll->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) kfree(name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_err(dev, "failed to register input mux\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) priv->pll = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int g12a_mdio_mux_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct g12a_mdio_mux *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) priv->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (IS_ERR(priv->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return PTR_ERR(priv->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) priv->pclk = devm_clk_get(dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (IS_ERR(priv->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret = PTR_ERR(priv->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dev_err(dev, "failed to get peripheral clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Make sure the device registers are clocked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = clk_prepare_enable(priv->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev_err(dev, "failed to enable peripheral clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Register PLL in CCF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret = g12a_ephy_glue_clk_register(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ret = mdio_mux_init(dev, dev->of_node, g12a_mdio_switch_fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) &priv->mux_handle, dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_err(dev, "mdio multiplexer init failed: %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) clk_disable_unprepare(priv->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int g12a_mdio_mux_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct g12a_mdio_mux *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mdio_mux_uninit(priv->mux_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (priv->pll_is_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) clk_disable_unprepare(priv->pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) clk_disable_unprepare(priv->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static struct platform_driver g12a_mdio_mux_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .probe = g12a_mdio_mux_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .remove = g12a_mdio_mux_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .name = "g12a-mdio_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .of_match_table = g12a_mdio_mux_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) module_platform_driver(g12a_mdio_mux_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MODULE_DESCRIPTION("Amlogic G12a MDIO multiplexer driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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