Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2016 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/of_mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mdio-mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define MDIO_RATE_ADJ_EXT_OFFSET	0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define MDIO_RATE_ADJ_INT_OFFSET	0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define MDIO_RATE_ADJ_DIVIDENT_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MDIO_SCAN_CTRL_OFFSET		0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MDIO_SCAN_CTRL_OVRIDE_EXT_MSTR	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MDIO_PARAM_OFFSET		0x23c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MDIO_PARAM_MIIM_CYCLE		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MDIO_PARAM_INTERNAL_SEL		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MDIO_PARAM_BUS_ID		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MDIO_PARAM_C45_SEL		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MDIO_PARAM_PHY_ID		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MDIO_PARAM_PHY_DATA		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MDIO_READ_OFFSET		0x240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MDIO_READ_DATA_MASK		0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MDIO_ADDR_OFFSET		0x244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MDIO_CTRL_OFFSET		0x248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MDIO_CTRL_WRITE_OP		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MDIO_CTRL_READ_OP		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MDIO_STAT_OFFSET		0x24c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MDIO_STAT_DONE			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define BUS_MAX_ADDR			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define EXT_BUS_START_ADDR		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MDIO_REG_ADDR_SPACE_SIZE	0x250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MDIO_OPERATING_FREQUENCY	11000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MDIO_RATE_ADJ_DIVIDENT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) struct iproc_mdiomux_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	void *mux_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct mii_bus *mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct clk *core_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static void mdio_mux_iproc_config(struct iproc_mdiomux_desc *md)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u32 divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	/* Disable external mdio master access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	val = readl(md->base + MDIO_SCAN_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	val |= BIT(MDIO_SCAN_CTRL_OVRIDE_EXT_MSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	writel(val, md->base + MDIO_SCAN_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if (md->core_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		/* use rate adjust regs to derrive the mdio's operating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		 * frequency from the specified core clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		divisor = clk_get_rate(md->core_clk) / MDIO_OPERATING_FREQUENCY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		divisor = divisor / (MDIO_RATE_ADJ_DIVIDENT + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		val = divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		val |= MDIO_RATE_ADJ_DIVIDENT << MDIO_RATE_ADJ_DIVIDENT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		writel(val, md->base + MDIO_RATE_ADJ_EXT_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		writel(val, md->base + MDIO_RATE_ADJ_INT_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static int iproc_mdio_wait_for_idle(void __iomem *base, bool result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	return readl_poll_timeout(base + MDIO_STAT_OFFSET, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 				  (val & MDIO_STAT_DONE) == result,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 				  2000, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /* start_miim_ops- Program and start MDIO transaction over mdio bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * @base: Base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  * @phyid: phyid of the selected bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  * @reg: register offset to be read/written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * @val :0 if read op else value to be written in @reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  * @op: Operation that need to be carried out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  *      MDIO_CTRL_READ_OP: Read transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  *      MDIO_CTRL_WRITE_OP: Write transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * Return value: Successful Read operation returns read reg values and write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  *      operation returns 0. Failure operation returns negative error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int start_miim_ops(void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			  u16 phyid, u32 reg, u16 val, u32 op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u32 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	writel(0, base + MDIO_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	ret = iproc_mdio_wait_for_idle(base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	param = readl(base + MDIO_PARAM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	param |= phyid << MDIO_PARAM_PHY_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	param |= val << MDIO_PARAM_PHY_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (reg & MII_ADDR_C45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		param |= BIT(MDIO_PARAM_C45_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	writel(param, base + MDIO_PARAM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	writel(reg, base + MDIO_ADDR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	writel(op, base + MDIO_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	ret = iproc_mdio_wait_for_idle(base, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (op == MDIO_CTRL_READ_OP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		ret = readl(base + MDIO_READ_OFFSET) & MDIO_READ_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int iproc_mdiomux_read(struct mii_bus *bus, int phyid, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct iproc_mdiomux_desc *md = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	ret = start_miim_ops(md->base, phyid, reg, 0, MDIO_CTRL_READ_OP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		dev_err(&bus->dev, "mdiomux read operation failed!!!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int iproc_mdiomux_write(struct mii_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			       int phyid, int reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct iproc_mdiomux_desc *md = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	/* Write val at reg offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	ret = start_miim_ops(md->base, phyid, reg, val, MDIO_CTRL_WRITE_OP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		dev_err(&bus->dev, "mdiomux write operation failed!!!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int mdio_mux_iproc_switch_fn(int current_child, int desired_child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				    void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct iproc_mdiomux_desc *md = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	u32 param, bus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	bool bus_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	/* select bus and its properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	bus_dir = (desired_child < EXT_BUS_START_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	bus_id = bus_dir ? desired_child : (desired_child - EXT_BUS_START_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	param = (bus_dir ? 1 : 0) << MDIO_PARAM_INTERNAL_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	param |= (bus_id << MDIO_PARAM_BUS_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	writel(param, md->base + MDIO_PARAM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int mdio_mux_iproc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct iproc_mdiomux_desc *md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct mii_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	md = devm_kzalloc(&pdev->dev, sizeof(*md), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (!md)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	md->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (res->start & 0xfff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		/* For backward compatibility in case the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		 * base address is specified with an offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		dev_info(&pdev->dev, "fix base address in dt-blob\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		res->start &= ~0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		res->end = res->start + MDIO_REG_ADDR_SPACE_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	md->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (IS_ERR(md->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		dev_err(&pdev->dev, "failed to ioremap register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		return PTR_ERR(md->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	md->mii_bus = devm_mdiobus_alloc(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (!md->mii_bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		dev_err(&pdev->dev, "mdiomux bus alloc failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	md->core_clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (md->core_clk == ERR_PTR(-ENOENT) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	    md->core_clk == ERR_PTR(-EINVAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		md->core_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	else if (IS_ERR(md->core_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		return PTR_ERR(md->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	rc = clk_prepare_enable(md->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		dev_err(&pdev->dev, "failed to enable core clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	bus = md->mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	bus->priv = md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	bus->name = "iProc MDIO mux bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", pdev->name, pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	bus->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	bus->read = iproc_mdiomux_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	bus->write = iproc_mdiomux_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	bus->phy_mask = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	bus->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	rc = mdiobus_register(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		dev_err(&pdev->dev, "mdiomux registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	platform_set_drvdata(pdev, md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	rc = mdio_mux_init(md->dev, md->dev->of_node, mdio_mux_iproc_switch_fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			   &md->mux_handle, md, md->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		dev_info(md->dev, "mdiomux initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		goto out_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	mdio_mux_iproc_config(md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	dev_info(md->dev, "iProc mdiomux registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) out_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	mdiobus_unregister(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) out_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	clk_disable_unprepare(md->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int mdio_mux_iproc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	struct iproc_mdiomux_desc *md = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	mdio_mux_uninit(md->mux_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	mdiobus_unregister(md->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	clk_disable_unprepare(md->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int mdio_mux_iproc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	struct iproc_mdiomux_desc *md = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	clk_disable_unprepare(md->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int mdio_mux_iproc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	struct iproc_mdiomux_desc *md = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	rc = clk_prepare_enable(md->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		dev_err(md->dev, "failed to enable core clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	mdio_mux_iproc_config(md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static SIMPLE_DEV_PM_OPS(mdio_mux_iproc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			 mdio_mux_iproc_suspend, mdio_mux_iproc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const struct of_device_id mdio_mux_iproc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		.compatible = "brcm,mdio-mux-iproc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MODULE_DEVICE_TABLE(of, mdio_mux_iproc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static struct platform_driver mdiomux_iproc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		.name		= "mdio-mux-iproc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		.of_match_table = mdio_mux_iproc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		.pm		= &mdio_mux_iproc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.probe		= mdio_mux_iproc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.remove		= mdio_mux_iproc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) module_platform_driver(mdiomux_iproc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) MODULE_DESCRIPTION("iProc MDIO Mux Bus Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MODULE_AUTHOR("Pramod Kumar <pramod.kumar@broadcom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MODULE_LICENSE("GPL v2");