^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* MOXA ART Ethernet (RTL8201CP) MDIO interface driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013 Jonas Jensen <jonas.jensen@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define REG_PHY_CTRL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define REG_PHY_WRITE_DATA 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* REG_PHY_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MIIWR BIT(27) /* init write sequence (auto cleared)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MIIRD BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define REGAD_MASK 0x3e00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PHYAD_MASK 0x1f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MIIRDATA_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* REG_PHY_WRITE_DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MIIWDATA_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct moxart_mdio_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int moxart_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct moxart_mdio_data *data = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int count = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) dev_dbg(&bus->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ctrl |= MIIRD | ((mii_id << 16) & PHYAD_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ((regnum << 21) & REGAD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) writel(ctrl, data->base + REG_PHY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ctrl = readl(data->base + REG_PHY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (!(ctrl & MIIRD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return ctrl & MIIRDATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) } while (count > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) dev_dbg(&bus->dev, "%s timed out\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int moxart_mdio_write(struct mii_bus *bus, int mii_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int regnum, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct moxart_mdio_data *data = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int count = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) dev_dbg(&bus->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ctrl |= MIIWR | ((mii_id << 16) & PHYAD_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ((regnum << 21) & REGAD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) value &= MIIWDATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) writel(value, data->base + REG_PHY_WRITE_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) writel(ctrl, data->base + REG_PHY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ctrl = readl(data->base + REG_PHY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (!(ctrl & MIIWR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) } while (count > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dev_dbg(&bus->dev, "%s timed out\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int moxart_mdio_reset(struct mii_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int data, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) for (i = 0; i < PHY_MAX_ADDR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) data = moxart_mdio_read(bus, i, MII_BMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (data < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) data |= BMCR_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (moxart_mdio_write(bus, i, MII_BMCR, data) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int moxart_mdio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct mii_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct moxart_mdio_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) bus = mdiobus_alloc_size(sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (!bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) bus->name = "MOXA ART Ethernet MII";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) bus->read = &moxart_mdio_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) bus->write = &moxart_mdio_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) bus->reset = &moxart_mdio_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d-mii", pdev->name, pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) bus->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Setting PHY_IGNORE_INTERRUPT here even if it has no effect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * of_mdiobus_register() sets these PHY_POLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Ideally, the interrupt from MAC controller could be used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * detect link state changes, not polling, i.e. if there was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * a way phy_driver could set PHY_HAS_INTERRUPT but have that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * interrupt handled in ethernet drivercode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) for (i = 0; i < PHY_MAX_ADDR; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bus->irq[i] = PHY_IGNORE_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) data = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) data->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (IS_ERR(data->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ret = PTR_ERR(data->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) goto err_out_free_mdiobus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ret = of_mdiobus_register(bus, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) goto err_out_free_mdiobus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) platform_set_drvdata(pdev, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) err_out_free_mdiobus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mdiobus_free(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int moxart_mdio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct mii_bus *bus = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) mdiobus_unregister(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) mdiobus_free(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct of_device_id moxart_mdio_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { .compatible = "moxa,moxart-mdio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MODULE_DEVICE_TABLE(of, moxart_mdio_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct platform_driver moxart_mdio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .probe = moxart_mdio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .remove = moxart_mdio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .name = "moxart-mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .of_match_table = moxart_mdio_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) module_platform_driver(moxart_mdio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MODULE_DESCRIPTION("MOXA ART MDIO interface driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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