^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Hisilicon Fast Ethernet MDIO Bus Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MDIO_RWCTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MDIO_RO_DATA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MDIO_WRITE BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MDIO_RW_FINISH BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BIT_PHY_ADDR_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BIT_WR_DATA_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct hisi_femac_mdio_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static int hisi_femac_mdio_wait_ready(struct hisi_femac_mdio_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) return readl_poll_timeout(data->membase + MDIO_RWCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) val, val & MDIO_RW_FINISH, 20, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int hisi_femac_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct hisi_femac_mdio_data *data = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ret = hisi_femac_mdio_wait_ready(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) writel((mii_id << BIT_PHY_ADDR_OFFSET) | regnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) data->membase + MDIO_RWCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ret = hisi_femac_mdio_wait_ready(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return readl(data->membase + MDIO_RO_DATA) & 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int hisi_femac_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct hisi_femac_mdio_data *data = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ret = hisi_femac_mdio_wait_ready(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) writel(MDIO_WRITE | (value << BIT_WR_DATA_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) (mii_id << BIT_PHY_ADDR_OFFSET) | regnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) data->membase + MDIO_RWCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return hisi_femac_mdio_wait_ready(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int hisi_femac_mdio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct mii_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct hisi_femac_mdio_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) bus = mdiobus_alloc_size(sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (!bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) bus->name = "hisi_femac_mii_bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bus->read = &hisi_femac_mdio_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) bus->write = &hisi_femac_mdio_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) snprintf(bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) bus->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) data = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) data->membase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (IS_ERR(data->membase)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ret = PTR_ERR(data->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) goto err_out_free_mdiobus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) data->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (IS_ERR(data->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ret = PTR_ERR(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) goto err_out_free_mdiobus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ret = clk_prepare_enable(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) goto err_out_free_mdiobus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret = of_mdiobus_register(bus, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) goto err_out_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) platform_set_drvdata(pdev, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) err_out_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) clk_disable_unprepare(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) err_out_free_mdiobus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mdiobus_free(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int hisi_femac_mdio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct mii_bus *bus = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct hisi_femac_mdio_data *data = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mdiobus_unregister(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clk_disable_unprepare(data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mdiobus_free(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct of_device_id hisi_femac_mdio_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { .compatible = "hisilicon,hisi-femac-mdio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MODULE_DEVICE_TABLE(of, hisi_femac_mdio_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct platform_driver hisi_femac_mdio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .probe = hisi_femac_mdio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .remove = hisi_femac_mdio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .name = "hisi-femac-mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .of_match_table = hisi_femac_mdio_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) module_platform_driver(hisi_femac_mdio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MODULE_DESCRIPTION("Hisilicon Fast Ethernet MAC MDIO interface driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MODULE_AUTHOR("Dongpo Li <lidongpo@hisilicon.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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