^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2009-2016 Cavium, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) enum cavium_mdiobus_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) UNINIT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) C22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) C45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SMI_CMD 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SMI_WR_DAT 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SMI_RD_DAT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SMI_CLK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SMI_EN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifdef __BIG_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OCT_MDIO_BITFIELD_FIELD(field, more) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) field; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OCT_MDIO_BITFIELD_FIELD(field, more) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) more \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) union cvmx_smix_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u64 u64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct cvmx_smix_clk_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) OCT_MDIO_BITFIELD_FIELD(u64 reserved_25_63:39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) OCT_MDIO_BITFIELD_FIELD(u64 mode:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) OCT_MDIO_BITFIELD_FIELD(u64 sample_hi:5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) OCT_MDIO_BITFIELD_FIELD(u64 sample_mode:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) OCT_MDIO_BITFIELD_FIELD(u64 reserved_14_14:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) OCT_MDIO_BITFIELD_FIELD(u64 clk_idle:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) OCT_MDIO_BITFIELD_FIELD(u64 preamble:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) OCT_MDIO_BITFIELD_FIELD(u64 sample:4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ;))))))))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) } s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) union cvmx_smix_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u64 u64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct cvmx_smix_cmd_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) OCT_MDIO_BITFIELD_FIELD(u64 phy_op:2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) OCT_MDIO_BITFIELD_FIELD(u64 reserved_13_15:3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) OCT_MDIO_BITFIELD_FIELD(u64 phy_adr:5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) OCT_MDIO_BITFIELD_FIELD(u64 reserved_5_7:3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) OCT_MDIO_BITFIELD_FIELD(u64 reg_adr:5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ;))))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) } s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) union cvmx_smix_en {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u64 u64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct cvmx_smix_en_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) OCT_MDIO_BITFIELD_FIELD(u64 reserved_1_63:63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) OCT_MDIO_BITFIELD_FIELD(u64 en:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ;))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) } s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) union cvmx_smix_rd_dat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u64 u64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct cvmx_smix_rd_dat_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) OCT_MDIO_BITFIELD_FIELD(u64 val:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ;))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) } s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) union cvmx_smix_wr_dat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u64 u64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct cvmx_smix_wr_dat_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) OCT_MDIO_BITFIELD_FIELD(u64 val:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ;))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) } s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct cavium_mdiobus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct mii_bus *mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void __iomem *register_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) enum cavium_mdiobus_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #ifdef CONFIG_CAVIUM_OCTEON_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #include <asm/octeon/octeon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static inline void oct_mdio_writeq(u64 val, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) cvmx_write_csr((u64 __force)addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static inline u64 oct_mdio_readq(void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return cvmx_read_csr((u64 __force)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #include <linux/io-64-nonatomic-lo-hi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define oct_mdio_writeq(val, addr) writeq(val, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define oct_mdio_readq(addr) readq(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int cavium_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int cavium_mdiobus_write(struct mii_bus *bus, int phy_id, int regnum, u16 val);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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