^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Bitbanged MDIO support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Scott Wood <scottwood@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2007 Freescale Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on CPM2 MDIO code which is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (c) 2003 Intracom S.A.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * by Pantelis Antoniou <panto@intracom.gr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 2005 (c) MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Vitaly Bordug <vbordug@ru.mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mdio-bitbang.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MDIO_READ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MDIO_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MDIO_C45 (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MDIO_C45_ADDR (MDIO_C45 | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MDIO_C45_READ (MDIO_C45 | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MDIO_C45_WRITE (MDIO_C45 | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MDIO_SETUP_TIME 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MDIO_HOLD_TIME 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Minimum MDC period is 400 ns, plus some margin for error. MDIO_DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * is done twice per period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MDIO_DELAY 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* The PHY may take up to 300 ns to produce data, plus some margin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * for error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MDIO_READ_DELAY 350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* MDIO must already be configured as output. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static void mdiobb_send_bit(struct mdiobb_ctrl *ctrl, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) const struct mdiobb_ops *ops = ctrl->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ops->set_mdio_data(ctrl, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ndelay(MDIO_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ops->set_mdc(ctrl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ndelay(MDIO_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ops->set_mdc(ctrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* MDIO must already be configured as input. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int mdiobb_get_bit(struct mdiobb_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const struct mdiobb_ops *ops = ctrl->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ndelay(MDIO_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ops->set_mdc(ctrl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ndelay(MDIO_READ_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ops->set_mdc(ctrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return ops->get_mdio_data(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* MDIO must already be configured as output. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static void mdiobb_send_num(struct mdiobb_ctrl *ctrl, u16 val, int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) for (i = bits - 1; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) mdiobb_send_bit(ctrl, (val >> i) & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* MDIO must already be configured as input. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static u16 mdiobb_get_num(struct mdiobb_ctrl *ctrl, int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u16 ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) for (i = bits - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ret |= mdiobb_get_bit(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Utility to send the preamble, address, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * register (common to read and write).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void mdiobb_cmd(struct mdiobb_ctrl *ctrl, int op, u8 phy, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const struct mdiobb_ops *ops = ctrl->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ops->set_mdio_dir(ctrl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Send a 32 bit preamble ('1's) with an extra '1' bit for good
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * measure. The IEEE spec says this is a PHY optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * requirement. The AMD 79C874 requires one after power up and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * one after a MII communications error. This means that we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * doing more preambles than we need, but it is safer and will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * much more robust.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) for (i = 0; i < 32; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) mdiobb_send_bit(ctrl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* send the start bit (01) and the read opcode (10) or write (01).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) Clause 45 operation uses 00 for the start and 11, 10 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mdiobb_send_bit(ctrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (op & MDIO_C45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) mdiobb_send_bit(ctrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mdiobb_send_bit(ctrl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) mdiobb_send_bit(ctrl, (op >> 1) & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) mdiobb_send_bit(ctrl, (op >> 0) & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mdiobb_send_num(ctrl, phy, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) mdiobb_send_num(ctrl, reg, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* In clause 45 mode all commands are prefixed by MDIO_ADDR to specify the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) lower 16 bits of the 21 bit address. This transfer is done identically to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MDIO_WRITE except for a different code. To enable clause 45 mode or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MII_ADDR_C45 into the address. Theoretically clause 45 and normal devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) can exist on the same bus. Normal devices should ignore the MDIO_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) phase. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int mdiobb_cmd_addr(struct mdiobb_ctrl *ctrl, int phy, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int dev_addr = (addr >> 16) & 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int reg = addr & 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mdiobb_cmd(ctrl, MDIO_C45_ADDR, phy, dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* send the turnaround (10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mdiobb_send_bit(ctrl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) mdiobb_send_bit(ctrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) mdiobb_send_num(ctrl, reg, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ctrl->ops->set_mdio_dir(ctrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mdiobb_get_bit(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int mdiobb_read(struct mii_bus *bus, int phy, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct mdiobb_ctrl *ctrl = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (reg & MII_ADDR_C45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) reg = mdiobb_cmd_addr(ctrl, phy, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) mdiobb_cmd(ctrl, MDIO_READ, phy, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ctrl->ops->set_mdio_dir(ctrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* check the turnaround bit: the PHY should be driving it to zero, if this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * PHY is listed in phy_ignore_ta_mask as having broken TA, skip that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (mdiobb_get_bit(ctrl) != 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) !(bus->phy_ignore_ta_mask & (1 << phy))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* PHY didn't drive TA low -- flush any bits it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * may be trying to send.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) for (i = 0; i < 32; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) mdiobb_get_bit(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ret = mdiobb_get_num(ctrl, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mdiobb_get_bit(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct mdiobb_ctrl *ctrl = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (reg & MII_ADDR_C45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) reg = mdiobb_cmd_addr(ctrl, phy, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) mdiobb_cmd(ctrl, MDIO_WRITE, phy, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* send the turnaround (10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mdiobb_send_bit(ctrl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) mdiobb_send_bit(ctrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mdiobb_send_num(ctrl, val, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ctrl->ops->set_mdio_dir(ctrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) mdiobb_get_bit(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct mii_bus *alloc_mdio_bitbang(struct mdiobb_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct mii_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) bus = mdiobus_alloc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) __module_get(ctrl->ops->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) bus->read = mdiobb_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) bus->write = mdiobb_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) bus->priv = ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) EXPORT_SYMBOL(alloc_mdio_bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) void free_mdio_bitbang(struct mii_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct mdiobb_ctrl *ctrl = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) module_put(ctrl->ops->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) mdiobus_free(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) EXPORT_SYMBOL(free_mdio_bitbang);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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