Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Broadcom UniMAC MDIO bus controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014-2017 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/platform_data/mdio-bcm-unimac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MDIO_CMD		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define  MDIO_START_BUSY	(1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define  MDIO_READ_FAIL		(1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define  MDIO_RD		(2 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define  MDIO_WR		(1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define  MDIO_PMD_SHIFT		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define  MDIO_PMD_MASK		0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define  MDIO_REG_SHIFT		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define  MDIO_REG_MASK		0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MDIO_CFG		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define  MDIO_C22		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define  MDIO_C45		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define  MDIO_CLK_DIV_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define  MDIO_CLK_DIV_MASK	0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define  MDIO_SUPP_PREAMBLE	(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) struct unimac_mdio_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct mii_bus		*mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	void __iomem		*base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	int (*wait_func)	(void *wait_func_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	void			*wait_func_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct clk		*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	u32			clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static inline u32 unimac_mdio_readl(struct unimac_mdio_priv *priv, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	/* MIPS chips strapped for BE will automagically configure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	 * peripheral registers for CPU-native byte order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		return __raw_readl(priv->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		return readl_relaxed(priv->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static inline void unimac_mdio_writel(struct unimac_mdio_priv *priv, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 				      u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		__raw_writel(val, priv->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		writel_relaxed(val, priv->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static inline void unimac_mdio_start(struct unimac_mdio_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	reg = unimac_mdio_readl(priv, MDIO_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	reg |= MDIO_START_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	unimac_mdio_writel(priv, reg, MDIO_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static inline unsigned int unimac_mdio_busy(struct unimac_mdio_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	return unimac_mdio_readl(priv, MDIO_CMD) & MDIO_START_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static int unimac_mdio_poll(void *wait_func_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct unimac_mdio_priv *priv = wait_func_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	unsigned int timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		if (!unimac_mdio_busy(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	} while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static int unimac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct unimac_mdio_priv *priv = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	/* Prepare the read operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	cmd = MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	unimac_mdio_writel(priv, cmd, MDIO_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	/* Start MDIO transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	unimac_mdio_start(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	ret = priv->wait_func(priv->wait_func_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	cmd = unimac_mdio_readl(priv, MDIO_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/* Some broken devices are known not to release the line during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 * turn-around, e.g: Broadcom BCM53125 external switches, so check for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	 * that condition here and ignore the MDIO controller read failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 * indication.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (cmd & MDIO_READ_FAIL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	return cmd & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int unimac_mdio_write(struct mii_bus *bus, int phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			     int reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct unimac_mdio_priv *priv = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/* Prepare the write operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	cmd = MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		(reg << MDIO_REG_SHIFT) | (0xffff & val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	unimac_mdio_writel(priv, cmd, MDIO_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	unimac_mdio_start(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	return priv->wait_func(priv->wait_func_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * their internal MDIO management controller making them fail to successfully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * be read from or written to for the first transaction.  We insert a dummy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  * BMSR read here to make sure that phy_get_device() and get_phy_id() can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  * correctly read the PHY MII_PHYSID1/2 registers and successfully register a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  * PHY device for this peripheral.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  * Once the PHY driver is registered, we can workaround subsequent reads from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  * there (e.g: during system-wide power management).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * bus->reset is invoked before mdiobus_scan during mdiobus_register and is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  * therefore the right location to stick that workaround. Since we do not want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  * to read from non-existing PHYs, we either use bus->phy_mask or do a manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  * Device Tree scan to limit the search area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int unimac_mdio_reset(struct mii_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct device_node *np = bus->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	u32 read_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		read_mask = ~bus->phy_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		for_each_available_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			addr = of_mdio_parse_addr(&bus->dev, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			if (addr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			read_mask |= 1 << addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		if (read_mask & 1 << addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			dev_dbg(&bus->dev, "Workaround for PHY @ %d\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			mdiobus_read(bus, addr, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void unimac_mdio_clk_set(struct unimac_mdio_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	u32 reg, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	/* Keep the hardware default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (!priv->clk_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (!priv->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		rate = 250000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		rate = clk_get_rate(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	div = (rate / (2 * priv->clk_freq)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (div & ~MDIO_CLK_DIV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		pr_warn("Incorrect MDIO clock frequency, ignoring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	/* The MDIO clock is the reference clock (typicaly 250Mhz) divided by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	 * 2 x (MDIO_CLK_DIV + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	reg = unimac_mdio_readl(priv, MDIO_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	reg &= ~(MDIO_CLK_DIV_MASK << MDIO_CLK_DIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	reg |= div << MDIO_CLK_DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	unimac_mdio_writel(priv, reg, MDIO_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int unimac_mdio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	struct unimac_mdio_pdata *pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct unimac_mdio_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	struct mii_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (!r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/* Just ioremap, as this MDIO block is usually integrated into an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 * Ethernet MAC controller register range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	priv->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (!priv->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		dev_err(&pdev->dev, "failed to remap register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	priv->clk = devm_clk_get_optional(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (IS_ERR(priv->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (of_property_read_u32(np, "clock-frequency", &priv->clk_freq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		priv->clk_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	unimac_mdio_clk_set(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	priv->mii_bus = mdiobus_alloc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (!priv->mii_bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	bus = priv->mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	bus->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		bus->name = pdata->bus_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		priv->wait_func = pdata->wait_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		priv->wait_func_data = pdata->wait_func_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		bus->phy_mask = ~pdata->phy_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		bus->name = "unimac MII bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		priv->wait_func_data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		priv->wait_func = unimac_mdio_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	bus->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	bus->read = unimac_mdio_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	bus->write = unimac_mdio_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	bus->reset = unimac_mdio_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", pdev->name, pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	ret = of_mdiobus_register(bus, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		dev_err(&pdev->dev, "MDIO bus registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		goto out_mdio_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	dev_info(&pdev->dev, "Broadcom UniMAC MDIO bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) out_mdio_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	mdiobus_free(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) out_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int unimac_mdio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	struct unimac_mdio_priv *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	mdiobus_unregister(priv->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	mdiobus_free(priv->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int __maybe_unused unimac_mdio_suspend(struct device *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	struct unimac_mdio_priv *priv = dev_get_drvdata(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int __maybe_unused unimac_mdio_resume(struct device *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	struct unimac_mdio_priv *priv = dev_get_drvdata(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	unimac_mdio_clk_set(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static SIMPLE_DEV_PM_OPS(unimac_mdio_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			 unimac_mdio_suspend, unimac_mdio_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct of_device_id unimac_mdio_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	{ .compatible = "brcm,genet-mdio-v5", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	{ .compatible = "brcm,genet-mdio-v4", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	{ .compatible = "brcm,genet-mdio-v3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	{ .compatible = "brcm,genet-mdio-v2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	{ .compatible = "brcm,genet-mdio-v1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	{ .compatible = "brcm,unimac-mdio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MODULE_DEVICE_TABLE(of, unimac_mdio_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static struct platform_driver unimac_mdio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.name = UNIMAC_MDIO_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		.of_match_table = unimac_mdio_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		.pm = &unimac_mdio_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	.probe	= unimac_mdio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	.remove	= unimac_mdio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) module_platform_driver(unimac_mdio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MODULE_AUTHOR("Broadcom Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MODULE_DESCRIPTION("Broadcom UniMAC MDIO bus controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MODULE_ALIAS("platform:" UNIMAC_MDIO_DRV_NAME);