Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2018-2020 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include "ipa.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "ipa_clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "ipa_uc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * DOC:  The IPA embedded microcontroller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * The IPA incorporates a microcontroller that is able to do some additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * handling/offloading of network activity.  The current code makes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * essentially no use of the microcontroller, but it still requires some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * initialization.  It needs to be notified in the event the AP crashes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * The microcontroller can generate two interrupts to the AP.  One interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * is used to indicate that a response to a request from the AP is available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * The other is used to notify the AP of the occurrence of an event.  In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * addition, the AP can interrupt the microcontroller by writing a register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * A 128 byte block of structured memory within the IPA SRAM is used together
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * with these interrupts to implement the communication interface between the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * AP and the IPA microcontroller.  Each side writes data to the shared area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * before interrupting its peer, which will read the written data in response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * to the interrupt.  Some information found in the shared area is currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * unused.  All remaining space in the shared area is reserved, and must not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * be read or written by the AP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* Supports hardware interface version 0x2000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* Delay to allow a the microcontroller to save state when crashing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define IPA_SEND_DELAY		100	/* microseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * struct ipa_uc_mem_area - AP/microcontroller shared memory area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * @command:		command code (AP->microcontroller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * @reserved0:		reserved bytes; avoid reading or writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * @command_param:	low 32 bits of command parameter (AP->microcontroller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * @command_param_hi:	high 32 bits of command parameter (AP->microcontroller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * @response:		response code (microcontroller->AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * @reserved1:		reserved bytes; avoid reading or writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * @response_param:	response parameter (microcontroller->AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * @event:		event code (microcontroller->AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * @reserved2:		reserved bytes; avoid reading or writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * @event_param:	event parameter (microcontroller->AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * @first_error_address: address of first error-source on SNOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * @hw_state:		state of hardware (including error type information)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * @warning_counter:	counter of non-fatal hardware errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * @reserved3:		reserved bytes; avoid reading or writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * @interface_version:	hardware-reported interface version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * @reserved4:		reserved bytes; avoid reading or writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * A shared memory area at the base of IPA resident memory is used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * communication with the microcontroller.  The region is 128 bytes in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * size, but only the first 40 bytes (structured this way) are used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) struct ipa_uc_mem_area {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u8 command;		/* enum ipa_uc_command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u8 reserved0[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	__le32 command_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	__le32 command_param_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	u8 response;		/* enum ipa_uc_response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	u8 reserved1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	__le32 response_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	u8 event;		/* enum ipa_uc_event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u8 reserved2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	__le32 event_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	__le32 first_error_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u8 hw_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u8 warning_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	__le16 reserved3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	__le16 interface_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	__le16 reserved4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /** enum ipa_uc_command - commands from the AP to the microcontroller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) enum ipa_uc_command {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	IPA_UC_COMMAND_NO_OP		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	IPA_UC_COMMAND_UPDATE_FLAGS	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	IPA_UC_COMMAND_DEBUG_RUN_TEST	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	IPA_UC_COMMAND_DEBUG_GET_INFO	= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	IPA_UC_COMMAND_ERR_FATAL	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	IPA_UC_COMMAND_CLK_GATE		= 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	IPA_UC_COMMAND_CLK_UNGATE	= 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	IPA_UC_COMMAND_MEMCPY		= 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	IPA_UC_COMMAND_RESET_PIPE	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	IPA_UC_COMMAND_REG_WRITE	= 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	IPA_UC_COMMAND_GSI_CH_EMPTY	= 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /** enum ipa_uc_response - microcontroller response codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum ipa_uc_response {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	IPA_UC_RESPONSE_NO_OP		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	IPA_UC_RESPONSE_INIT_COMPLETED	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	IPA_UC_RESPONSE_CMD_COMPLETED	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	IPA_UC_RESPONSE_DEBUG_GET_INFO	= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /** enum ipa_uc_event - common cpu events reported by the microcontroller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) enum ipa_uc_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	IPA_UC_EVENT_NO_OP     = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	IPA_UC_EVENT_ERROR     = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	IPA_UC_EVENT_LOG_INFO  = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct ipa_uc_mem_area *ipa_uc_shared(struct ipa *ipa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	u32 offset = ipa->mem_offset + ipa->mem[IPA_MEM_UC_SHARED].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	return ipa->mem_virt + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Microcontroller event IPA interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void ipa_uc_event_handler(struct ipa *ipa, enum ipa_irq_id irq_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct ipa_uc_mem_area *shared = ipa_uc_shared(ipa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct device *dev = &ipa->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (shared->event == IPA_UC_EVENT_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		dev_err(dev, "microcontroller error event\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		dev_err(dev, "unsupported microcontroller event %hhu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			shared->event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Microcontroller response IPA interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void ipa_uc_response_hdlr(struct ipa *ipa, enum ipa_irq_id irq_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct ipa_uc_mem_area *shared = ipa_uc_shared(ipa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	/* An INIT_COMPLETED response message is sent to the AP by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	 * microcontroller when it is operational.  Other than this, the AP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	 * should only receive responses from the microcontroller when it has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	 * sent it a request message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	 * We can drop the clock reference taken in ipa_uc_setup() once we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	 * know the microcontroller has finished its initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	switch (shared->response) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	case IPA_UC_RESPONSE_INIT_COMPLETED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		ipa->uc_loaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		ipa_clock_put(ipa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		dev_warn(&ipa->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			 "unsupported microcontroller response %hhu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			 shared->response);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* ipa_uc_setup() - Set up the microcontroller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) void ipa_uc_setup(struct ipa *ipa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	/* The microcontroller needs the IPA clock running until it has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	 * completed its initialization.  It signals this by sending an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	 * INIT_COMPLETED response message to the AP.  This could occur after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	 * we have finished doing the rest of the IPA initialization, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	 * need to take an extra "proxy" reference, and hold it until we've
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	 * received that signal.  (This reference is dropped in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	 * ipa_uc_response_hdlr(), above.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	ipa_clock_get(ipa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	ipa->uc_loaded = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	ipa_interrupt_add(ipa->interrupt, IPA_IRQ_UC_0, ipa_uc_event_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	ipa_interrupt_add(ipa->interrupt, IPA_IRQ_UC_1, ipa_uc_response_hdlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Inverse of ipa_uc_setup() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void ipa_uc_teardown(struct ipa *ipa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	ipa_interrupt_remove(ipa->interrupt, IPA_IRQ_UC_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	ipa_interrupt_remove(ipa->interrupt, IPA_IRQ_UC_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (!ipa->uc_loaded)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		ipa_clock_put(ipa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Send a command to the microcontroller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void send_uc_command(struct ipa *ipa, u32 command, u32 command_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct ipa_uc_mem_area *shared = ipa_uc_shared(ipa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	shared->command = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	shared->command_param = cpu_to_le32(command_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	shared->command_param_hi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	shared->response = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	shared->response_param = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	iowrite32(1, ipa->reg_virt + IPA_REG_IRQ_UC_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Tell the microcontroller the AP is shutting down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void ipa_uc_panic_notifier(struct ipa *ipa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (!ipa->uc_loaded)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	send_uc_command(ipa, IPA_UC_COMMAND_ERR_FATAL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	/* give uc enough time to save state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	udelay(IPA_SEND_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }