^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2018-2020 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _IPA_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _IPA_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "ipa_version.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct ipa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * DOC: IPA Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * IPA registers are located within the "ipa-reg" address space defined by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Device Tree. The offset of each register within that space is specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * by symbols defined below. The address space is mapped to virtual memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * space in ipa_mem_init(). All IPA registers are 32 bits wide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Certain register types are duplicated for a number of instances of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * something. For example, each IPA endpoint has an set of registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * defining its configuration. The offset to an endpoint's set of registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * is computed based on an "base" offset, plus an endpoint's ID multiplied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * and a "stride" value for the register. For such registers, the offset is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * computed by a function-like macro that takes a parameter used in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * computation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Some register offsets depend on execution environment. For these an "ee"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * parameter is supplied to the offset macro. The "ee" value is a member of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * the gsi_ee enumerated type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * The offset of a register dependent on endpoint ID is computed by a macro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * that is supplied a parameter "ep", "txep", or "rxep". A register with an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * "ep" parameter is valid for any endpoint; a register with a "txep" or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * "rxep" parameter is valid only for TX or RX endpoints, respectively. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * "*ep" value is assumed to be less than the maximum valid endpoint ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * for the current hardware, and that will not exceed IPA_ENDPOINT_MAX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * The offset of registers related to filter and route tables is computed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * by a macro that is supplied a parameter "er". The "er" represents an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * endpoint ID for filters, or a route ID for routes. For filters, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * endpoint ID must be less than IPA_ENDPOINT_MAX, but is further restricted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * because not all endpoints support filtering. For routes, the route ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * must be less than IPA_ROUTE_MAX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * The offset of registers related to resource types is computed by a macro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * that is supplied a parameter "rt". The "rt" represents a resource type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * which is is a member of the ipa_resource_type_src enumerated type for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * source endpoint resources or the ipa_resource_type_dst enumerated type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * for destination endpoint resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Some registers encode multiple fields within them. For these, each field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * has a symbol below defining a field mask that encodes both the position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * and width of the field within its register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * In some cases, different versions of IPA hardware use different offset or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * field mask values. In such cases an inline_function(ipa) is used rather
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * than a MACRO to define the offset or field mask to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Finally, some registers hold bitmasks representing endpoints. In such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * cases the @available field in the @ipa structure defines the "full" set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * of valid bits for the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IPA_REG_ENABLED_PIPES_OFFSET 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IPA_REG_COMP_CFG_OFFSET 0x0000003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ENABLE_FMASK GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IPA_QMB_SELECT_CONS_EN_FMASK GENMASK(5, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IPA_QMB_SELECT_PROD_EN_FMASK GENMASK(6, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GSI_MULTI_INORDER_RD_DIS_FMASK GENMASK(7, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GSI_MULTI_INORDER_WR_DIS_FMASK GENMASK(8, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GEN_QMB_0_MULTI_INORDER_RD_DIS_FMASK GENMASK(9, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GEN_QMB_1_MULTI_INORDER_RD_DIS_FMASK GENMASK(10, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GEN_QMB_0_MULTI_INORDER_WR_DIS_FMASK GENMASK(11, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GEN_QMB_1_MULTI_INORDER_WR_DIS_FMASK GENMASK(12, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS_FMASK GENMASK(13, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GSI_SNOC_CNOC_LOOP_PROT_DISABLE_FMASK GENMASK(14, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GSI_MULTI_AXI_MASTERS_DIS_FMASK GENMASK(15, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IPA_QMB_SELECT_GLOBAL_EN_FMASK GENMASK(16, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_FMASK GENMASK(20, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IPA_REG_CLKON_CFG_OFFSET 0x00000044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RX_FMASK GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PROC_FMASK GENMASK(1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TX_WRAPPER_FMASK GENMASK(2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MISC_FMASK GENMASK(3, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RAM_ARB_FMASK GENMASK(4, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define FTCH_HPS_FMASK GENMASK(5, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define FTCH_DPS_FMASK GENMASK(6, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HPS_FMASK GENMASK(7, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DPS_FMASK GENMASK(8, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RX_HPS_CMDQS_FMASK GENMASK(9, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HPS_DPS_CMDQS_FMASK GENMASK(10, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DPS_TX_CMDQS_FMASK GENMASK(11, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RSRC_MNGR_FMASK GENMASK(12, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CTX_HANDLER_FMASK GENMASK(13, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ACK_MNGR_FMASK GENMASK(14, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define D_DCPH_FMASK GENMASK(15, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define H_DCPH_FMASK GENMASK(16, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DCMP_FMASK GENMASK(17, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define NTF_TX_CMDQS_FMASK GENMASK(18, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TX_0_FMASK GENMASK(19, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TX_1_FMASK GENMASK(20, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define FNR_FMASK GENMASK(21, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define QSB2AXI_CMDQ_L_FMASK GENMASK(22, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AGGR_WRAPPER_FMASK GENMASK(23, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RAM_SLAVEWAY_FMASK GENMASK(24, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define QMB_FMASK GENMASK(25, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define WEIGHT_ARB_FMASK GENMASK(26, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GSI_IF_FMASK GENMASK(27, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GLOBAL_FMASK GENMASK(28, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GLOBAL_2X_CLK_FMASK GENMASK(29, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IPA_REG_ROUTE_OFFSET 0x00000048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ROUTE_DIS_FMASK GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ROUTE_DEF_PIPE_FMASK GENMASK(5, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ROUTE_DEF_HDR_TABLE_FMASK GENMASK(6, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ROUTE_DEF_HDR_OFST_FMASK GENMASK(16, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ROUTE_FRAG_DEF_PIPE_FMASK GENMASK(21, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ROUTE_DEF_RETAIN_HDR_FMASK GENMASK(24, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IPA_REG_SHARED_MEM_SIZE_OFFSET 0x00000054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SHARED_MEM_SIZE_FMASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SHARED_MEM_BADDR_FMASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IPA_REG_QSB_MAX_WRITES_OFFSET 0x00000074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GEN_QMB_0_MAX_WRITES_FMASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GEN_QMB_1_MAX_WRITES_FMASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IPA_REG_QSB_MAX_READS_OFFSET 0x00000078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GEN_QMB_0_MAX_READS_FMASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GEN_QMB_1_MAX_READS_FMASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* The next two fields are present for IPA v4.0 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GEN_QMB_0_MAX_READS_BEATS_FMASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GEN_QMB_1_MAX_READS_BEATS_FMASK GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (version == IPA_VERSION_3_5_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0x0000010c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0x000000b4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* The next register is present for IPA v4.2 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IPA_REG_FILT_ROUT_HASH_EN_OFFSET 0x00000148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IPV6_ROUTER_HASH_EN GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IPV6_FILTER_HASH_EN GENMASK(4, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IPV4_ROUTER_HASH_EN GENMASK(8, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IPV4_FILTER_HASH_EN GENMASK(12, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (version == IPA_VERSION_3_5_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0x0000090;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0x000014c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IPV6_ROUTER_HASH_FLUSH GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IPV6_FILTER_HASH_FLUSH GENMASK(4, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IPV4_ROUTER_HASH_FLUSH GENMASK(8, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IPV4_FILTER_HASH_FLUSH GENMASK(12, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IPA_REG_BCR_OFFSET 0x000001d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define BCR_CMDQ_L_LACK_ONE_ENTRY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define BCR_TX_NOT_USING_BRESP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define BCR_SUSPEND_L2_IRQ BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define BCR_HOLB_DROP_L2_IRQ BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define BCR_DUAL_TX BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Backward compatibility register value to use for each version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static inline u32 ipa_reg_bcr_val(enum ipa_version version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (version == IPA_VERSION_3_5_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return BCR_CMDQ_L_LACK_ONE_ENTRY | BCR_TX_NOT_USING_BRESP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) BCR_SUSPEND_L2_IRQ | BCR_HOLB_DROP_L2_IRQ | BCR_DUAL_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (version == IPA_VERSION_4_0 || version == IPA_VERSION_4_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return BCR_CMDQ_L_LACK_ONE_ENTRY | BCR_SUSPEND_L2_IRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) BCR_HOLB_DROP_L2_IRQ | BCR_DUAL_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IPA_REG_LOCAL_PKT_PROC_CNTXT_BASE_OFFSET 0x000001e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* The internal inactivity timer clock is used for the aggregation timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TIMER_FREQUENCY 32000 /* 32 KHz inactivity timer clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define AGGR_GRANULARITY GENMASK(8, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Compute the value to use in the AGGR_GRANULARITY field representing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * given number of microseconds. The value is one less than the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * timer ticks in the requested period. Zero not a valid granularity value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static inline u32 ipa_aggr_granularity_val(u32 usec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return DIV_ROUND_CLOSEST(usec * TIMER_FREQUENCY, USEC_PER_SEC) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IPA_REG_TX_CFG_OFFSET 0x000001fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* The first three fields are present for IPA v3.5.1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TX0_PREFETCH_DISABLE GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TX1_PREFETCH_DISABLE GENMASK(1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define PREFETCH_ALMOST_EMPTY_SIZE GENMASK(4, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* The next fields are present for IPA v4.0 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define PREFETCH_ALMOST_EMPTY_SIZE_TX0 GENMASK(5, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DMAW_SCND_OUTSD_PRED_THRESHOLD GENMASK(9, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define DMAW_SCND_OUTSD_PRED_EN GENMASK(10, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DMAW_MAX_BEATS_256_DIS GENMASK(11, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define PA_MASK_EN GENMASK(12, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define PREFETCH_ALMOST_EMPTY_SIZE_TX1 GENMASK(16, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* The last two fields are present for IPA v4.2 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SSPND_PA_NO_START_STATE GENMASK(18, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SSPND_PA_NO_BQ_STATE GENMASK(19, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IPA_REG_FLAVOR_0_OFFSET 0x00000210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define BAM_MAX_PIPES_FMASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define BAM_MAX_CONS_PIPES_FMASK GENMASK(12, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define BAM_MAX_PROD_PIPES_FMASK GENMASK(20, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define BAM_PROD_LOWEST_FMASK GENMASK(27, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (version == IPA_VERSION_4_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0x00000240;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return 0x00000220;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define ENTER_IDLE_DEBOUNCE_THRESH_FMASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CONST_NON_IDLE_ENABLE_FMASK GENMASK(16, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IPA_REG_SRC_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) (0x00000400 + 0x0020 * (rt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IPA_REG_SRC_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) (0x00000404 + 0x0020 * (rt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define IPA_REG_SRC_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) (0x00000408 + 0x0020 * (rt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IPA_REG_DST_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) (0x00000500 + 0x0020 * (rt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IPA_REG_DST_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) (0x00000504 + 0x0020 * (rt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IPA_REG_DST_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) (0x00000508 + 0x0020 * (rt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define X_MIN_LIM_FMASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define X_MAX_LIM_FMASK GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define Y_MIN_LIM_FMASK GENMASK(21, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define Y_MAX_LIM_FMASK GENMASK(29, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IPA_REG_ENDP_INIT_CTRL_N_OFFSET(ep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) (0x00000800 + 0x0070 * (ep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define ENDP_SUSPEND_FMASK GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define ENDP_DELAY_FMASK GENMASK(1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IPA_REG_ENDP_INIT_CFG_N_OFFSET(ep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) (0x00000808 + 0x0070 * (ep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define FRAG_OFFLOAD_EN_FMASK GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CS_OFFLOAD_EN_FMASK GENMASK(2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) (0x00000810 + 0x0070 * (ep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define HDR_LEN_FMASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define HDR_OFST_METADATA_FMASK GENMASK(12, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define HDR_OFST_PKT_SIZE_VALID_FMASK GENMASK(19, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define HDR_OFST_PKT_SIZE_FMASK GENMASK(25, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define HDR_A5_MUX_FMASK GENMASK(26, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define HDR_LEN_INC_DEAGG_HDR_FMASK GENMASK(27, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define HDR_METADATA_REG_VALID_FMASK GENMASK(28, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define IPA_REG_ENDP_INIT_HDR_EXT_N_OFFSET(ep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) (0x00000814 + 0x0070 * (ep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define HDR_ENDIANNESS_FMASK GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define HDR_TOTAL_LEN_OR_PAD_VALID_FMASK GENMASK(1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define HDR_TOTAL_LEN_OR_PAD_FMASK GENMASK(2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define HDR_PAYLOAD_LEN_INC_PADDING_FMASK GENMASK(3, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Valid only for RX (IPA producer) endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(rxep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) (0x00000818 + 0x0070 * (rxep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Valid only for TX (IPA consumer) endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define IPA_REG_ENDP_INIT_MODE_N_OFFSET(txep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) (0x00000820 + 0x0070 * (txep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define MODE_FMASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define DEST_PIPE_INDEX_FMASK GENMASK(8, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define BYTE_THRESHOLD_FMASK GENMASK(27, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define PIPE_REPLICATION_EN_FMASK GENMASK(28, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define PAD_EN_FMASK GENMASK(29, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define HDR_FTCH_DISABLE_FMASK GENMASK(30, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define IPA_REG_ENDP_INIT_AGGR_N_OFFSET(ep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) (0x00000824 + 0x0070 * (ep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define AGGR_EN_FMASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define AGGR_TYPE_FMASK GENMASK(4, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define AGGR_BYTE_LIMIT_FMASK GENMASK(9, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define AGGR_TIME_LIMIT_FMASK GENMASK(14, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define AGGR_PKT_LIMIT_FMASK GENMASK(20, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define AGGR_SW_EOF_ACTIVE_FMASK GENMASK(21, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define AGGR_FORCE_CLOSE_FMASK GENMASK(22, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define AGGR_HARD_BYTE_LIMIT_ENABLE_FMASK GENMASK(24, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Valid only for RX (IPA producer) endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(rxep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) (0x0000082c + 0x0070 * (rxep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define HOL_BLOCK_EN_FMASK GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Valid only for RX (IPA producer) endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(rxep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) (0x00000830 + 0x0070 * (rxep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* The next fields are present for IPA v4.2 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define BASE_VALUE_FMASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SCALE_FMASK GENMASK(12, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Valid only for TX (IPA consumer) endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) (0x00000834 + 0x0070 * (txep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define MAX_PACKET_LEN_FMASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(ep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) (0x00000838 + 0x0070 * (ep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define RSRC_GRP_FMASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Valid only for TX (IPA consumer) endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(txep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) (0x0000083c + 0x0070 * (txep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define HPS_SEQ_TYPE_FMASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define DPS_SEQ_TYPE_FMASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define HPS_REP_SEQ_TYPE_FMASK GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define DPS_REP_SEQ_TYPE_FMASK GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) (0x00000840 + 0x0070 * (ep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define STATUS_EN_FMASK GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define STATUS_ENDP_FMASK GENMASK(5, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define STATUS_LOCATION_FMASK GENMASK(8, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* The next field is present for IPA v4.0 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* "er" is either an endpoint ID (for filters) or a route ID (for routes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(er) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) (0x0000085c + 0x0070 * (er))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define FILTER_HASH_MSK_SRC_IP_FMASK GENMASK(1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define FILTER_HASH_MSK_DST_IP_FMASK GENMASK(2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define FILTER_HASH_MSK_SRC_PORT_FMASK GENMASK(3, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define FILTER_HASH_MSK_DST_PORT_FMASK GENMASK(4, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define FILTER_HASH_MSK_PROTOCOL_FMASK GENMASK(5, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define FILTER_HASH_MSK_METADATA_FMASK GENMASK(6, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define IPA_REG_ENDP_FILTER_HASH_MSK_ALL GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define ROUTER_HASH_MSK_SRC_ID_FMASK GENMASK(16, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define ROUTER_HASH_MSK_SRC_IP_FMASK GENMASK(17, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define ROUTER_HASH_MSK_DST_IP_FMASK GENMASK(18, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define ROUTER_HASH_MSK_SRC_PORT_FMASK GENMASK(19, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define ROUTER_HASH_MSK_DST_PORT_FMASK GENMASK(20, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define ROUTER_HASH_MSK_PROTOCOL_FMASK GENMASK(21, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define ROUTER_HASH_MSK_METADATA_FMASK GENMASK(22, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define IPA_REG_ENDP_ROUTER_HASH_MSK_ALL GENMASK(22, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define IPA_REG_IRQ_STTS_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) IPA_REG_IRQ_STTS_EE_N_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define IPA_REG_IRQ_STTS_EE_N_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) (0x00003008 + 0x1000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define IPA_REG_IRQ_EN_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) IPA_REG_IRQ_EN_EE_N_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define IPA_REG_IRQ_EN_EE_N_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) (0x0000300c + 0x1000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define IPA_REG_IRQ_CLR_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) IPA_REG_IRQ_CLR_EE_N_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define IPA_REG_IRQ_CLR_EE_N_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) (0x00003010 + 0x1000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define IPA_REG_IRQ_UC_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) IPA_REG_IRQ_UC_EE_N_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define IPA_REG_IRQ_UC_EE_N_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) (0x0000301c + 0x1000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define IPA_REG_IRQ_SUSPEND_INFO_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) (0x00003030 + 0x1000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* ipa->available defines the valid bits in the SUSPEND_INFO register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define IPA_REG_SUSPEND_IRQ_EN_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) IPA_REG_SUSPEND_IRQ_EN_EE_N_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define IPA_REG_SUSPEND_IRQ_EN_EE_N_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) (0x00003034 + 0x1000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* ipa->available defines the valid bits in the SUSPEND_IRQ_EN register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define IPA_REG_SUSPEND_IRQ_CLR_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) IPA_REG_SUSPEND_IRQ_CLR_EE_N_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define IPA_REG_SUSPEND_IRQ_CLR_EE_N_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) (0x00003038 + 0x1000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* ipa->available defines the valid bits in the SUSPEND_IRQ_CLR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /** enum ipa_cs_offload_en - checksum offload field in ENDP_INIT_CFG_N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) enum ipa_cs_offload_en {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) IPA_CS_OFFLOAD_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) IPA_CS_OFFLOAD_UL = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) IPA_CS_OFFLOAD_DL = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) IPA_CS_RSVD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /** enum ipa_aggr_en - aggregation enable field in ENDP_INIT_AGGR_N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) enum ipa_aggr_en {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) IPA_BYPASS_AGGR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) IPA_ENABLE_AGGR = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) IPA_ENABLE_DEAGGR = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /** enum ipa_aggr_type - aggregation type field in in_ENDP_INIT_AGGR_N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) enum ipa_aggr_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) IPA_MBIM_16 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) IPA_HDLC = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) IPA_TLP = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) IPA_RNDIS = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) IPA_GENERIC = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) IPA_COALESCE = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) IPA_QCMAP = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /** enum ipa_mode - mode field in ENDP_INIT_MODE_N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) enum ipa_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) IPA_BASIC = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) IPA_ENABLE_FRAMING_HDLC = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) IPA_ENABLE_DEFRAMING_HDLC = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) IPA_DMA = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * enum ipa_seq_type - HPS and DPS sequencer type fields in in ENDP_INIT_SEQ_N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * @IPA_SEQ_DMA_ONLY: only DMA is performed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * @IPA_SEQ_PKT_PROCESS_NO_DEC_UCP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * packet processing + no decipher + microcontroller (Ethernet Bridging)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * @IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * second packet processing pass + no decipher + microcontroller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * @IPA_SEQ_DMA_DEC: DMA + cipher/decipher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * @IPA_SEQ_DMA_COMP_DECOMP: DMA + compression/decompression
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * @IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * packet processing + no decipher + no uCP + HPS REP DMA parser
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * @IPA_SEQ_INVALID: invalid sequencer type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * The values defined here are broken into 4-bit nibbles that are written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * into fields of the INIT_SEQ_N endpoint registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) enum ipa_seq_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) IPA_SEQ_DMA_ONLY = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) IPA_SEQ_PKT_PROCESS_NO_DEC_UCP = 0x0002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) IPA_SEQ_DMA_DEC = 0x0011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) IPA_SEQ_DMA_COMP_DECOMP = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP = 0x0806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) IPA_SEQ_INVALID = 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) int ipa_reg_init(struct ipa *ipa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) void ipa_reg_exit(struct ipa *ipa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #endif /* _IPA_REG_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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