^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2019-2021 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dma-direction.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "gsi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "gsi_trans.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "ipa.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "ipa_endpoint.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "ipa_table.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ipa_cmd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ipa_mem.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * DOC: IPA Immediate Commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * The AP command TX endpoint is used to issue immediate commands to the IPA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * An immediate command is generally used to request the IPA do something
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * other than data transfer to another endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Immediate commands are represented by GSI transactions just like other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * transfer requests, represented by a single GSI TRE. Each immediate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * command has a well-defined format, having a payload of a known length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * This allows the transfer element's length field to be used to hold an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * immediate command's opcode. The payload for a command resides in DRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * and is described by a single scatterlist entry in its transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Commands do not require a transaction completion callback. To commit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * an immediate command transaction, either gsi_trans_commit_wait() or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * gsi_trans_commit_wait_timeout() is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Some commands can wait until indicated pipeline stages are clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) enum pipeline_clear_options {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) pipeline_clear_hps = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) pipeline_clear_src_grp = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) pipeline_clear_full = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* IPA_CMD_IP_V{4,6}_{FILTER,ROUTING}_INIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct ipa_cmd_hw_ip_fltrt_init {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __le64 hash_rules_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) __le64 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __le64 nhash_rules_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Field masks for ipa_cmd_hw_ip_fltrt_init structure fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IP_FLTRT_FLAGS_HASH_SIZE_FMASK GENMASK_ULL(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IP_FLTRT_FLAGS_HASH_ADDR_FMASK GENMASK_ULL(27, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IP_FLTRT_FLAGS_NHASH_SIZE_FMASK GENMASK_ULL(39, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IP_FLTRT_FLAGS_NHASH_ADDR_FMASK GENMASK_ULL(55, 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* IPA_CMD_HDR_INIT_LOCAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct ipa_cmd_hw_hdr_init_local {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) __le64 hdr_table_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __le32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __le32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Field masks for ipa_cmd_hw_hdr_init_local structure fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK GENMASK(27, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* IPA_CMD_REGISTER_WRITE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* For IPA v4.0+, this opcode gets modified with pipeline clear options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define REGISTER_WRITE_OPCODE_SKIP_CLEAR_FMASK GENMASK(8, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define REGISTER_WRITE_OPCODE_CLEAR_OPTION_FMASK GENMASK(10, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct ipa_cmd_register_write {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) __le16 flags; /* Unused/reserved for IPA v3.5.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __le16 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __le32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __le32 value_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __le32 clear_options; /* Unused/reserved for IPA v4.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Field masks for ipa_cmd_register_write structure fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* The next field is present for IPA v4.0 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK GENMASK(14, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* The next field is present for IPA v3.5.1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define REGISTER_WRITE_FLAGS_SKIP_CLEAR_FMASK GENMASK(15, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* The next field and its values are present for IPA v3.5.1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define REGISTER_WRITE_CLEAR_OPTIONS_FMASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* IPA_CMD_IP_PACKET_INIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct ipa_cmd_ip_packet_init {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 dest_endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 reserved[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Field masks for ipa_cmd_ip_packet_init dest_endpoint field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IPA_PACKET_INIT_DEST_ENDPOINT_FMASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* IPA_CMD_DMA_SHARED_MEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* For IPA v4.0+, this opcode gets modified with pipeline clear options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DMA_SHARED_MEM_OPCODE_SKIP_CLEAR_FMASK GENMASK(8, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DMA_SHARED_MEM_OPCODE_CLEAR_OPTION_FMASK GENMASK(10, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct ipa_cmd_hw_dma_mem_mem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __le16 clear_after_read; /* 0 or DMA_SHARED_MEM_CLEAR_AFTER_READ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __le16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __le16 local_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __le64 system_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Flag allowing atomic clear of target region after reading data (v4.0+)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DMA_SHARED_MEM_CLEAR_AFTER_READ GENMASK(15, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Field masks for ipa_cmd_hw_dma_mem_mem structure fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DMA_SHARED_MEM_FLAGS_DIRECTION_FMASK GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* The next two fields are present for IPA v3.5.1 only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DMA_SHARED_MEM_FLAGS_SKIP_CLEAR_FMASK GENMASK(1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DMA_SHARED_MEM_FLAGS_CLEAR_OPTIONS_FMASK GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* IPA_CMD_IP_PACKET_TAG_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct ipa_cmd_ip_packet_tag_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) __le64 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IP_PACKET_TAG_STATUS_TAG_FMASK GENMASK_ULL(63, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Immediate command payload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) union ipa_cmd_payload {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct ipa_cmd_hw_ip_fltrt_init table_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct ipa_cmd_hw_hdr_init_local hdr_init_local;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct ipa_cmd_register_write register_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct ipa_cmd_ip_packet_init ip_packet_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct ipa_cmd_hw_dma_mem_mem dma_shared_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct ipa_cmd_ip_packet_tag_status ip_packet_tag_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static void ipa_cmd_validate_build(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* The sizes of a filter and route tables need to fit into fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * in the ipa_cmd_hw_ip_fltrt_init structure. Although hashed tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * might not be used, non-hashed and hashed tables have the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * maximum size. IPv4 and IPv6 filter tables have the same number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * of entries, as and IPv4 and IPv6 route tables have the same number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * of entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TABLE_SIZE (TABLE_COUNT_MAX * IPA_TABLE_ENTRY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TABLE_COUNT_MAX max_t(u32, IPA_ROUTE_COUNT_MAX, IPA_FILTER_COUNT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) BUILD_BUG_ON(TABLE_SIZE > field_max(IP_FLTRT_FLAGS_HASH_SIZE_FMASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) BUILD_BUG_ON(TABLE_SIZE > field_max(IP_FLTRT_FLAGS_NHASH_SIZE_FMASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #undef TABLE_COUNT_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #undef TABLE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #ifdef IPA_VALIDATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Validate a memory region holding a table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) bool ipa_cmd_table_valid(struct ipa *ipa, const struct ipa_mem *mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) bool route, bool ipv6, bool hashed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct device *dev = &ipa->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 offset_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) offset_max = hashed ? field_max(IP_FLTRT_FLAGS_HASH_ADDR_FMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) : field_max(IP_FLTRT_FLAGS_NHASH_ADDR_FMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (mem->offset > offset_max ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ipa->mem_offset > offset_max - mem->offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dev_err(dev, "IPv%c %s%s table region offset too large\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ipv6 ? '6' : '4', hashed ? "hashed " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) route ? "route" : "filter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ipa->mem_offset, mem->offset, offset_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (mem->offset > ipa->mem_size ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mem->size > ipa->mem_size - mem->offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev_err(dev, "IPv%c %s%s table region out of range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ipv6 ? '6' : '4', hashed ? "hashed " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) route ? "route" : "filter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mem->offset, mem->size, ipa->mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Validate the memory region that holds headers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static bool ipa_cmd_header_valid(struct ipa *ipa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) const struct ipa_mem *mem = &ipa->mem[IPA_MEM_MODEM_HEADER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct device *dev = &ipa->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 offset_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 size_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* In ipa_cmd_hdr_init_local_add() we record the offset and size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * of the header table memory area. Make sure the offset and size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * fit in the fields that need to hold them, and that the entire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * range is within the overall IPA memory range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) offset_max = field_max(HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (mem->offset > offset_max ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ipa->mem_offset > offset_max - mem->offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dev_err(dev, "header table region offset too large\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ipa->mem_offset, mem->offset, offset_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) size_max = field_max(HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) size = ipa->mem[IPA_MEM_MODEM_HEADER].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) size += ipa->mem[IPA_MEM_AP_HEADER].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (size > size_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_err(dev, "header table region size too large\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_err(dev, " (0x%04x > 0x%08x)\n", size, size_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (size > ipa->mem_size || mem->offset > ipa->mem_size - size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dev_err(dev, "header table region out of range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mem->offset, size, ipa->mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Indicate whether an offset can be used with a register_write command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static bool ipa_cmd_register_write_offset_valid(struct ipa *ipa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) const char *name, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct ipa_cmd_register_write *payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct device *dev = &ipa->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 offset_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u32 bit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* The maximum offset in a register_write immediate command depends
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * on the version of IPA. IPA v3.5.1 supports a 16 bit offset, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * newer versions allow some additional high-order bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) bit_count = BITS_PER_BYTE * sizeof(payload->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (ipa->version != IPA_VERSION_3_5_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) bit_count += hweight32(REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) BUILD_BUG_ON(bit_count > 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) offset_max = ~0U >> (32 - bit_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Make sure the offset can be represented by the field(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * that holds it. Also make sure the offset is not outside
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * the overall IPA memory range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (offset > offset_max || ipa->mem_offset > offset_max - offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dev_err(dev, "%s offset too large 0x%04x + 0x%04x > 0x%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) name, ipa->mem_offset, offset, offset_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Check whether offsets passed to register_write are valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static bool ipa_cmd_register_write_valid(struct ipa *ipa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* If hashed tables are supported, ensure the hash flush register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * offset will fit in a register write IPA immediate command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (ipa->version != IPA_VERSION_4_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) offset = ipa_reg_filt_rout_hash_flush_offset(ipa->version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) name = "filter/route hash flush";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (!ipa_cmd_register_write_offset_valid(ipa, name, offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Each endpoint can have a status endpoint associated with it,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * and this is recorded in an endpoint register. If the modem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * crashes, we reset the status endpoint for all modem endpoints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * using a register write IPA immediate command. Make sure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * worst case (highest endpoint number) offset of that endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * fits in the register write command field(s) that must hold it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) offset = IPA_REG_ENDP_STATUS_N_OFFSET(IPA_ENDPOINT_COUNT - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) name = "maximal endpoint status";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (!ipa_cmd_register_write_offset_valid(ipa, name, offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) bool ipa_cmd_data_valid(struct ipa *ipa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (!ipa_cmd_header_valid(ipa))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (!ipa_cmd_register_write_valid(ipa))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #endif /* IPA_VALIDATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int ipa_cmd_pool_init(struct gsi_channel *channel, u32 tre_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct gsi_trans_info *trans_info = &channel->trans_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct device *dev = channel->gsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* This is as good a place as any to validate build constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ipa_cmd_validate_build();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Even though command payloads are allocated one at a time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * a single transaction can require up to tlv_count of them,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * so we treat them as if that many can be allocated at once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret = gsi_trans_pool_init_dma(dev, &trans_info->cmd_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) sizeof(union ipa_cmd_payload),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) tre_max, channel->tlv_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Each TRE needs a command info structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ret = gsi_trans_pool_init(&trans_info->info_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) sizeof(struct ipa_cmd_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) tre_max, channel->tlv_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) gsi_trans_pool_exit_dma(dev, &trans_info->cmd_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) void ipa_cmd_pool_exit(struct gsi_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct gsi_trans_info *trans_info = &channel->trans_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct device *dev = channel->gsi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) gsi_trans_pool_exit(&trans_info->info_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) gsi_trans_pool_exit_dma(dev, &trans_info->cmd_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static union ipa_cmd_payload *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ipa_cmd_payload_alloc(struct ipa *ipa, dma_addr_t *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct gsi_trans_info *trans_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct ipa_endpoint *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) trans_info = &ipa->gsi.channel[endpoint->channel_id].trans_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return gsi_trans_pool_alloc_dma(&trans_info->cmd_pool, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* If hash_size is 0, hash_offset and hash_addr ignored. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) void ipa_cmd_table_init_add(struct gsi_trans *trans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) enum ipa_cmd_opcode opcode, u16 size, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dma_addr_t addr, u16 hash_size, u32 hash_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dma_addr_t hash_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) enum dma_data_direction direction = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct ipa_cmd_hw_ip_fltrt_init *payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) union ipa_cmd_payload *cmd_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dma_addr_t payload_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Record the non-hash table offset and size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) offset += ipa->mem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) val = u64_encode_bits(offset, IP_FLTRT_FLAGS_NHASH_ADDR_FMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) val |= u64_encode_bits(size, IP_FLTRT_FLAGS_NHASH_SIZE_FMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* The hash table offset and address are zero if its size is 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (hash_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Record the hash table offset and size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) hash_offset += ipa->mem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) val |= u64_encode_bits(hash_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) IP_FLTRT_FLAGS_HASH_ADDR_FMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) val |= u64_encode_bits(hash_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) IP_FLTRT_FLAGS_HASH_SIZE_FMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) payload = &cmd_payload->table_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Fill in all offsets and sizes and the non-hash table address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (hash_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) payload->hash_rules_addr = cpu_to_le64(hash_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) payload->flags = cpu_to_le64(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) payload->nhash_rules_addr = cpu_to_le64(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) direction, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Initialize header space in IPA-local memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) void ipa_cmd_hdr_init_local_add(struct gsi_trans *trans, u32 offset, u16 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) enum ipa_cmd_opcode opcode = IPA_CMD_HDR_INIT_LOCAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) enum dma_data_direction direction = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct ipa_cmd_hw_hdr_init_local *payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) union ipa_cmd_payload *cmd_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dma_addr_t payload_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) offset += ipa->mem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* With this command we tell the IPA where in its local memory the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * header tables reside. The content of the buffer provided is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * also written via DMA into that space. The IPA hardware owns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * the table, but the AP must initialize it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) payload = &cmd_payload->hdr_init_local;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) payload->hdr_table_addr = cpu_to_le64(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) flags = u32_encode_bits(size, HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) flags |= u32_encode_bits(offset, HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) payload->flags = cpu_to_le32(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) direction, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) void ipa_cmd_register_write_add(struct gsi_trans *trans, u32 offset, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 mask, bool clear_full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct ipa_cmd_register_write *payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) union ipa_cmd_payload *cmd_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u32 opcode = IPA_CMD_REGISTER_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dma_addr_t payload_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u32 clear_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u32 options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* pipeline_clear_src_grp is not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) clear_option = clear_full ? pipeline_clear_full : pipeline_clear_hps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (ipa->version != IPA_VERSION_3_5_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u16 offset_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Opcode encodes pipeline clear options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* SKIP_CLEAR is always 0 (don't skip pipeline clear) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) val = u16_encode_bits(clear_option,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) REGISTER_WRITE_OPCODE_CLEAR_OPTION_FMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) opcode |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* Extract the high 4 bits from the offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) offset_high = (u16)u32_get_bits(offset, GENMASK(19, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) offset &= (1 << 16) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Extract the top 4 bits and encode it into the flags field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) flags = u16_encode_bits(offset_high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) options = 0; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) flags = 0; /* SKIP_CLEAR flag is always 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) options = u16_encode_bits(clear_option,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) REGISTER_WRITE_CLEAR_OPTIONS_FMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) payload = &cmd_payload->register_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) payload->flags = cpu_to_le16(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) payload->offset = cpu_to_le16((u16)offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) payload->value = cpu_to_le32(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) payload->value_mask = cpu_to_le32(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) payload->clear_options = cpu_to_le32(options);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) DMA_NONE, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Skip IP packet processing on the next data transfer on a TX channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static void ipa_cmd_ip_packet_init_add(struct gsi_trans *trans, u8 endpoint_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) enum ipa_cmd_opcode opcode = IPA_CMD_IP_PACKET_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) enum dma_data_direction direction = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct ipa_cmd_ip_packet_init *payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) union ipa_cmd_payload *cmd_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dma_addr_t payload_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* assert(endpoint_id <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) field_max(IPA_PACKET_INIT_DEST_ENDPOINT_FMASK)); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) payload = &cmd_payload->ip_packet_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) payload->dest_endpoint = u8_encode_bits(endpoint_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) IPA_PACKET_INIT_DEST_ENDPOINT_FMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) direction, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* Use a DMA command to read or write a block of IPA-resident memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) void ipa_cmd_dma_shared_mem_add(struct gsi_trans *trans, u32 offset, u16 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dma_addr_t addr, bool toward_ipa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) enum ipa_cmd_opcode opcode = IPA_CMD_DMA_SHARED_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct ipa_cmd_hw_dma_mem_mem *payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) union ipa_cmd_payload *cmd_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) enum dma_data_direction direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dma_addr_t payload_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* size and offset must fit in 16 bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* assert(size > 0 && size <= U16_MAX); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* assert(offset <= U16_MAX && ipa->mem_offset <= U16_MAX - offset); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) offset += ipa->mem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) payload = &cmd_payload->dma_shared_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* payload->clear_after_read was reserved prior to IPA v4.0. It's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * never needed for current code, so it's 0 regardless of version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) payload->size = cpu_to_le16(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) payload->local_addr = cpu_to_le16(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* payload->flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * direction: 0 = write to IPA, 1 read from IPA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * Starting at v4.0 these are reserved; either way, all zero:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * pipeline clear: 0 = wait for pipeline clear (don't skip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * clear_options: 0 = pipeline_clear_hps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * Instead, for v4.0+ these are encoded in the opcode. But again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * since both values are 0 we won't bother OR'ing them in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) flags = toward_ipa ? 0 : DMA_SHARED_MEM_FLAGS_DIRECTION_FMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) payload->flags = cpu_to_le16(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) payload->system_addr = cpu_to_le64(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) direction = toward_ipa ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) direction, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static void ipa_cmd_ip_tag_status_add(struct gsi_trans *trans, u64 tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) enum ipa_cmd_opcode opcode = IPA_CMD_IP_PACKET_TAG_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) enum dma_data_direction direction = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct ipa_cmd_ip_packet_tag_status *payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) union ipa_cmd_payload *cmd_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dma_addr_t payload_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* assert(tag <= field_max(IP_PACKET_TAG_STATUS_TAG_FMASK)); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) payload = &cmd_payload->ip_packet_tag_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) payload->tag = u64_encode_bits(tag, IP_PACKET_TAG_STATUS_TAG_FMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) direction, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* Issue a small command TX data transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static void ipa_cmd_transfer_add(struct gsi_trans *trans, u16 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) enum dma_data_direction direction = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) enum ipa_cmd_opcode opcode = IPA_CMD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) union ipa_cmd_payload *payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dma_addr_t payload_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* assert(size <= sizeof(*payload)); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Just transfer a zero-filled payload structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) payload = ipa_cmd_payload_alloc(ipa, &payload_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) direction, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) void ipa_cmd_tag_process_add(struct gsi_trans *trans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct ipa_endpoint *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) endpoint = ipa->name_map[IPA_ENDPOINT_AP_LAN_RX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ipa_cmd_register_write_add(trans, 0, 0, 0, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ipa_cmd_ip_packet_init_add(trans, endpoint->endpoint_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ipa_cmd_ip_tag_status_add(trans, 0xcba987654321);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ipa_cmd_transfer_add(trans, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* Returns the number of commands required for the tag process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u32 ipa_cmd_tag_process_count(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) void ipa_cmd_tag_process(struct ipa *ipa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u32 count = ipa_cmd_tag_process_count();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct gsi_trans *trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) trans = ipa_cmd_trans_alloc(ipa, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (trans) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ipa_cmd_tag_process_add(trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) gsi_trans_commit_wait(trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) dev_err(&ipa->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) "error allocating %u entry tag transaction\n", count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static struct ipa_cmd_info *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ipa_cmd_info_alloc(struct ipa_endpoint *endpoint, u32 tre_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct gsi_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) channel = &endpoint->ipa->gsi.channel[endpoint->channel_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return gsi_trans_pool_alloc(&channel->trans_info.info_pool, tre_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* Allocate a transaction for the command TX endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct gsi_trans *ipa_cmd_trans_alloc(struct ipa *ipa, u32 tre_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct ipa_endpoint *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct gsi_trans *trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) trans = gsi_channel_trans_alloc(&ipa->gsi, endpoint->channel_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) tre_count, DMA_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (trans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) trans->info = ipa_cmd_info_alloc(endpoint, tre_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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