^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2019-2020 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/refcount.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-direction.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "gsi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "gsi_private.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "gsi_trans.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "ipa_gsi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ipa_data.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ipa_cmd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * DOC: GSI Transactions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * A GSI transaction abstracts the behavior of a GSI channel by representing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * everything about a related group of IPA commands in a single structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * (A "command" in this sense is either a data transfer or an IPA immediate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * command.) Most details of interaction with the GSI hardware are managed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * by the GSI transaction core, allowing users to simply describe commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * to be performed. When a transaction has completed a callback function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * (dependent on the type of endpoint associated with the channel) allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * cleanup of resources associated with the transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * To perform a command (or set of them), a user of the GSI transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * interface allocates a transaction, indicating the number of TREs required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * (one per command). If sufficient TREs are available, they are reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * for use in the transaction and the allocation succeeds. This way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * exhaustion of the available TREs in a channel ring is detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * as early as possible. All resources required to complete a transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * are allocated at transaction allocation time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Commands performed as part of a transaction are represented in an array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * of Linux scatterlist structures. This array is allocated with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * transaction, and its entries are initialized using standard scatterlist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * functions (such as sg_set_buf() or skb_to_sgvec()).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Once a transaction's scatterlist structures have been initialized, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * transaction is committed. The caller is responsible for mapping buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * for DMA if necessary, and this should be done *before* allocating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * the transaction. Between a successful allocation and commit of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * transaction no errors should occur.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Committing transfers ownership of the entire transaction to the GSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * transaction core. The GSI transaction code formats the content of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * the scatterlist array into the channel ring buffer and informs the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * hardware that new TREs are available to process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * The last TRE in each transaction is marked to interrupt the AP when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * GSI hardware has completed it. Because transfers described by TREs are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * performed strictly in order, signaling the completion of just the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * TRE in the transaction is sufficient to indicate the full transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * is complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * When a transaction is complete, ipa_gsi_trans_complete() is called by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * GSI code into the IPA layer, allowing it to perform any final cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * required before the transaction is freed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Hardware values representing a transfer element type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) enum gsi_tre_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) GSI_RE_XFER = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) GSI_RE_IMMD_CMD = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* An entry in a channel ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct gsi_tre {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __le64 addr; /* DMA address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __le16 len_opcode; /* length in bytes or enum IPA_CMD_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __le16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __le32 flags; /* TRE_FLAGS_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* gsi_tre->flags mask values (in CPU byte order) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TRE_FLAGS_CHAIN_FMASK GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TRE_FLAGS_IEOT_FMASK GENMASK(9, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TRE_FLAGS_BEI_FMASK GENMASK(10, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TRE_FLAGS_TYPE_FMASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int gsi_trans_pool_init(struct gsi_trans_pool *pool, size_t size, u32 count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 max_alloc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void *virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #ifdef IPA_VALIDATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!size || size % 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (count < max_alloc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (!max_alloc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif /* IPA_VALIDATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* By allocating a few extra entries in our pool (one less
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * than the maximum number that will be requested in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * single allocation), we can always satisfy requests without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * ever worrying about straddling the end of the pool array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * If there aren't enough entries starting at the free index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * we just allocate free entries from the beginning of the pool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) virt = kcalloc(count + max_alloc - 1, size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (!virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pool->base = virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* If the allocator gave us any extra memory, use it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) pool->count = ksize(pool->base) / size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pool->free = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pool->max_alloc = max_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pool->size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) pool->addr = 0; /* Only used for DMA pools */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void gsi_trans_pool_exit(struct gsi_trans_pool *pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) kfree(pool->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) memset(pool, 0, sizeof(*pool));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Allocate the requested number of (zeroed) entries from the pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Home-grown DMA pool. This way we can preallocate and use the tre_count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * to guarantee allocations will succeed. Even though we specify max_alloc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * (and it can be more than one), we only allow allocation of a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * element from a DMA pool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int gsi_trans_pool_init_dma(struct device *dev, struct gsi_trans_pool *pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) size_t size, u32 count, u32 max_alloc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) size_t total_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void *virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #ifdef IPA_VALIDATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (!size || size % 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (count < max_alloc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!max_alloc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif /* IPA_VALIDATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Don't let allocations cross a power-of-two boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) size = __roundup_pow_of_two(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) total_size = (count + max_alloc - 1) * size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* The allocator will give us a power-of-2 number of pages. But we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * can't guarantee that, so request it. That way we won't waste any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * memory that would be available beyond the required space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Note that gsi_trans_pool_exit_dma() assumes the total allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * size is exactly (count * size).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) total_size = get_order(total_size) << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) virt = dma_alloc_coherent(dev, total_size, &addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (!virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) pool->base = virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) pool->count = total_size / size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pool->free = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pool->size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pool->max_alloc = max_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) pool->addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void gsi_trans_pool_exit_dma(struct device *dev, struct gsi_trans_pool *pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) size_t total_size = pool->count * pool->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dma_free_coherent(dev, total_size, pool->base, pool->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) memset(pool, 0, sizeof(*pool));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Return the byte offset of the next free entry in the pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static u32 gsi_trans_pool_alloc_common(struct gsi_trans_pool *pool, u32 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* assert(count > 0); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* assert(count <= pool->max_alloc); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Allocate from beginning if wrap would occur */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (count > pool->count - pool->free)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pool->free = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) offset = pool->free * pool->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pool->free += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) memset(pool->base + offset, 0, count * pool->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Allocate a contiguous block of zeroed entries from a pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) void *gsi_trans_pool_alloc(struct gsi_trans_pool *pool, u32 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return pool->base + gsi_trans_pool_alloc_common(pool, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Allocate a single zeroed entry from a DMA pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) void *gsi_trans_pool_alloc_dma(struct gsi_trans_pool *pool, dma_addr_t *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 offset = gsi_trans_pool_alloc_common(pool, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *addr = pool->addr + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return pool->base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Return the pool element that immediately follows the one given.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * This only works done if elements are allocated one at a time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) void *gsi_trans_pool_next(struct gsi_trans_pool *pool, void *element)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) void *end = pool->base + pool->count * pool->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* assert(element >= pool->base); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* assert(element < end); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* assert(pool->max_alloc == 1); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) element += pool->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return element < end ? element : pool->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Map a given ring entry index to the transaction associated with it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void gsi_channel_trans_map(struct gsi_channel *channel, u32 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct gsi_trans *trans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Note: index *must* be used modulo the ring count here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) channel->trans_info.map[index % channel->tre_ring.count] = trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Return the transaction mapped to a given ring entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct gsi_trans *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) gsi_channel_trans_mapped(struct gsi_channel *channel, u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Note: index *must* be used modulo the ring count here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return channel->trans_info.map[index % channel->tre_ring.count];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Return the oldest completed transaction for a channel (or null) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct gsi_trans *gsi_channel_trans_complete(struct gsi_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return list_first_entry_or_null(&channel->trans_info.complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct gsi_trans, links);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Move a transaction from the allocated list to the pending list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void gsi_trans_move_pending(struct gsi_trans *trans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct gsi_channel *channel = &trans->gsi->channel[trans->channel_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct gsi_trans_info *trans_info = &channel->trans_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) spin_lock_bh(&trans_info->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) list_move_tail(&trans->links, &trans_info->pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) spin_unlock_bh(&trans_info->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Move a transaction and all of its predecessors from the pending list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * to the completed list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) void gsi_trans_move_complete(struct gsi_trans *trans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct gsi_channel *channel = &trans->gsi->channel[trans->channel_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct gsi_trans_info *trans_info = &channel->trans_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) spin_lock_bh(&trans_info->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Move this transaction and all predecessors to completed list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) list_cut_position(&list, &trans_info->pending, &trans->links);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) list_splice_tail(&list, &trans_info->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) spin_unlock_bh(&trans_info->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Move a transaction from the completed list to the polled list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) void gsi_trans_move_polled(struct gsi_trans *trans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct gsi_channel *channel = &trans->gsi->channel[trans->channel_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct gsi_trans_info *trans_info = &channel->trans_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) spin_lock_bh(&trans_info->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) list_move_tail(&trans->links, &trans_info->polled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) spin_unlock_bh(&trans_info->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Reserve some number of TREs on a channel. Returns true if successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) gsi_trans_tre_reserve(struct gsi_trans_info *trans_info, u32 tre_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int avail = atomic_read(&trans_info->tre_avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) new = avail - (int)tre_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (unlikely(new < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } while (!atomic_try_cmpxchg(&trans_info->tre_avail, &avail, new));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Release previously-reserved TRE entries to a channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) gsi_trans_tre_release(struct gsi_trans_info *trans_info, u32 tre_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) atomic_add(tre_count, &trans_info->tre_avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Allocate a GSI transaction on a channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct gsi_trans *gsi_channel_trans_alloc(struct gsi *gsi, u32 channel_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 tre_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) enum dma_data_direction direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct gsi_channel *channel = &gsi->channel[channel_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct gsi_trans_info *trans_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct gsi_trans *trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* assert(tre_count <= gsi_channel_trans_tre_max(gsi, channel_id)); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) trans_info = &channel->trans_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* We reserve the TREs now, but consume them at commit time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * If there aren't enough available, we're done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!gsi_trans_tre_reserve(trans_info, tre_count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Allocate and initialize non-zero fields in the the transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) trans = gsi_trans_pool_alloc(&trans_info->pool, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) trans->gsi = gsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) trans->channel_id = channel_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) trans->tre_count = tre_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) init_completion(&trans->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Allocate the scatterlist and (if requested) info entries. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) trans->sgl = gsi_trans_pool_alloc(&trans_info->sg_pool, tre_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) sg_init_marker(trans->sgl, tre_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) trans->direction = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) spin_lock_bh(&trans_info->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) list_add_tail(&trans->links, &trans_info->alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) spin_unlock_bh(&trans_info->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) refcount_set(&trans->refcount, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Free a previously-allocated transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) void gsi_trans_free(struct gsi_trans *trans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) refcount_t *refcount = &trans->refcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct gsi_trans_info *trans_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) bool last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* We must hold the lock to release the last reference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (refcount_dec_not_one(refcount))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) trans_info = &trans->gsi->channel[trans->channel_id].trans_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) spin_lock_bh(&trans_info->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Reference might have been added before we got the lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) last = refcount_dec_and_test(refcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) list_del(&trans->links);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) spin_unlock_bh(&trans_info->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (!last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ipa_gsi_trans_release(trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Releasing the reserved TREs implicitly frees the sgl[] and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * (if present) info[] arrays, plus the transaction itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) gsi_trans_tre_release(trans_info, trans->tre_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Add an immediate command to a transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) void gsi_trans_cmd_add(struct gsi_trans *trans, void *buf, u32 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dma_addr_t addr, enum dma_data_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) enum ipa_cmd_opcode opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct ipa_cmd_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 which = trans->used++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* assert(which < trans->tre_count); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Commands are quite different from data transfer requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * Their payloads come from a pool whose memory is allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * using dma_alloc_coherent(). We therefore do *not* map them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * for DMA (unlike what we do for pages and skbs).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * When a transaction completes, the SGL is normally unmapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * A command transaction has direction DMA_NONE, which tells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * gsi_trans_complete() to skip the unmapping step.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * The only things we use directly in a command scatter/gather
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * entry are the DMA address and length. We still need the SG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * table flags to be maintained though, so assign a NULL page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * pointer for that purpose.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) sg = &trans->sgl[which];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) sg_assign_page(sg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) sg_dma_address(sg) = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) sg_dma_len(sg) = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) info = &trans->info[which];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) info->opcode = opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) info->direction = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Add a page transfer to a transaction. It will fill the only TRE. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int gsi_trans_page_add(struct gsi_trans *trans, struct page *page, u32 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct scatterlist *sg = &trans->sgl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* assert(trans->tre_count == 1); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* assert(!trans->used); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) sg_set_page(sg, page, size, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ret = dma_map_sg(trans->gsi->dev, sg, 1, trans->direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) trans->used++; /* Transaction now owns the (DMA mapped) page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Add an SKB transfer to a transaction. No other TREs will be used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int gsi_trans_skb_add(struct gsi_trans *trans, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct scatterlist *sg = &trans->sgl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u32 used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* assert(trans->tre_count == 1); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* assert(!trans->used); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* skb->len will not be 0 (checked early) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = skb_to_sgvec(skb, sg, 0, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) used = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = dma_map_sg(trans->gsi->dev, sg, used, trans->direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) trans->used += used; /* Transaction now owns the (DMA mapped) skb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* Compute the length/opcode value to use for a TRE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static __le16 gsi_tre_len_opcode(enum ipa_cmd_opcode opcode, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return opcode == IPA_CMD_NONE ? cpu_to_le16((u16)len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) : cpu_to_le16((u16)opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Compute the flags value to use for a given TRE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static __le32 gsi_tre_flags(bool last_tre, bool bei, enum ipa_cmd_opcode opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) enum gsi_tre_type tre_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u32 tre_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) tre_type = opcode == IPA_CMD_NONE ? GSI_RE_XFER : GSI_RE_IMMD_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) tre_flags = u32_encode_bits(tre_type, TRE_FLAGS_TYPE_FMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Last TRE contains interrupt flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (last_tre) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* All transactions end in a transfer completion interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) tre_flags |= TRE_FLAGS_IEOT_FMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* Don't interrupt when outbound commands are acknowledged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (bei)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) tre_flags |= TRE_FLAGS_BEI_FMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) } else { /* All others indicate there's more to come */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) tre_flags |= TRE_FLAGS_CHAIN_FMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return cpu_to_le32(tre_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static void gsi_trans_tre_fill(struct gsi_tre *dest_tre, dma_addr_t addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u32 len, bool last_tre, bool bei,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) enum ipa_cmd_opcode opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct gsi_tre tre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) tre.addr = cpu_to_le64(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) tre.len_opcode = gsi_tre_len_opcode(opcode, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) tre.reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) tre.flags = gsi_tre_flags(last_tre, bei, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* ARM64 can write 16 bytes as a unit with a single instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * Doing the assignment this way is an attempt to make that happen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) *dest_tre = tre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * __gsi_trans_commit() - Common GSI transaction commit code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * @trans: Transaction to commit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * @ring_db: Whether to tell the hardware about these queued transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * Formats channel ring TRE entries based on the content of the scatterlist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * Maps a transaction pointer to the last ring entry used for the transaction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * so it can be recovered when it completes. Moves the transaction to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * pending list. Finally, updates the channel ring pointer and optionally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * rings the doorbell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static void __gsi_trans_commit(struct gsi_trans *trans, bool ring_db)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct gsi_channel *channel = &trans->gsi->channel[trans->channel_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct gsi_ring *ring = &channel->tre_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) enum ipa_cmd_opcode opcode = IPA_CMD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) bool bei = channel->toward_ipa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct ipa_cmd_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct gsi_tre *dest_tre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 byte_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* assert(trans->used > 0); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Consume the entries. If we cross the end of the ring while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * filling them we'll switch to the beginning to finish.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * If there is no info array we're doing a simple data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * transfer request, whose opcode is IPA_CMD_NONE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) info = trans->info ? &trans->info[0] : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) avail = ring->count - ring->index % ring->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dest_tre = gsi_ring_virt(ring, ring->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) for_each_sg(trans->sgl, sg, trans->used, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) bool last_tre = i == trans->used - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dma_addr_t addr = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u32 len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) byte_count += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (!avail--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dest_tre = gsi_ring_virt(ring, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) opcode = info++->opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) gsi_trans_tre_fill(dest_tre, addr, len, last_tre, bei, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dest_tre++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ring->index += trans->used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (channel->toward_ipa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* We record TX bytes when they are sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) trans->len = byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) trans->trans_count = channel->trans_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) trans->byte_count = channel->byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) channel->trans_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) channel->byte_count += byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* Associate the last TRE with the transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) gsi_channel_trans_map(channel, ring->index - 1, trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) gsi_trans_move_pending(trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Ring doorbell if requested, or if all TREs are allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (ring_db || !atomic_read(&channel->trans_info.tre_avail)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* Report what we're handing off to hardware for TX channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (channel->toward_ipa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) gsi_channel_tx_queued(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) gsi_channel_doorbell(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Commit a GSI transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) void gsi_trans_commit(struct gsi_trans *trans, bool ring_db)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (trans->used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) __gsi_trans_commit(trans, ring_db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) gsi_trans_free(trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* Commit a GSI transaction and wait for it to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) void gsi_trans_commit_wait(struct gsi_trans *trans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (!trans->used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) goto out_trans_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) refcount_inc(&trans->refcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) __gsi_trans_commit(trans, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) wait_for_completion(&trans->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) out_trans_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) gsi_trans_free(trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* Commit a GSI transaction and wait for it to complete, with timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int gsi_trans_commit_wait_timeout(struct gsi_trans *trans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) unsigned long timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) unsigned long timeout_jiffies = msecs_to_jiffies(timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) unsigned long remaining = 1; /* In case of empty transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (!trans->used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) goto out_trans_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) refcount_inc(&trans->refcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) __gsi_trans_commit(trans, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) remaining = wait_for_completion_timeout(&trans->completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) timeout_jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) out_trans_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) gsi_trans_free(trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return remaining ? 0 : -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Process the completion of a transaction; called while polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) void gsi_trans_complete(struct gsi_trans *trans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* If the entire SGL was mapped when added, unmap it now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (trans->direction != DMA_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dma_unmap_sg(trans->gsi->dev, trans->sgl, trans->used,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) trans->direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ipa_gsi_trans_complete(trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) complete(&trans->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) gsi_trans_free(trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* Cancel a channel's pending transactions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) void gsi_channel_trans_cancel_pending(struct gsi_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct gsi_trans_info *trans_info = &channel->trans_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct gsi_trans *trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) bool cancelled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* channel->gsi->mutex is held by caller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) spin_lock_bh(&trans_info->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) cancelled = !list_empty(&trans_info->pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) list_for_each_entry(trans, &trans_info->pending, links)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) trans->cancelled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) list_splice_tail_init(&trans_info->pending, &trans_info->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) spin_unlock_bh(&trans_info->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* Schedule NAPI polling to complete the cancelled transactions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (cancelled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) napi_schedule(&channel->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Issue a command to read a single byte from a channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int gsi_trans_read_byte(struct gsi *gsi, u32 channel_id, dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct gsi_channel *channel = &gsi->channel[channel_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct gsi_ring *ring = &channel->tre_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct gsi_trans_info *trans_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct gsi_tre *dest_tre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) trans_info = &channel->trans_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* First reserve the TRE, if possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (!gsi_trans_tre_reserve(trans_info, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* Now fill the the reserved TRE and tell the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dest_tre = gsi_ring_virt(ring, ring->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) gsi_trans_tre_fill(dest_tre, addr, 1, true, false, IPA_CMD_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ring->index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) gsi_channel_doorbell(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* Mark a gsi_trans_read_byte() request done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) void gsi_trans_read_byte_done(struct gsi *gsi, u32 channel_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct gsi_channel *channel = &gsi->channel[channel_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) gsi_trans_tre_release(&channel->trans_info, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* Initialize a channel's GSI transaction info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) int gsi_channel_trans_init(struct gsi *gsi, u32 channel_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct gsi_channel *channel = &gsi->channel[channel_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct gsi_trans_info *trans_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u32 tre_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* Ensure the size of a channel element is what's expected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) BUILD_BUG_ON(sizeof(struct gsi_tre) != GSI_RING_ELEMENT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* The map array is used to determine what transaction is associated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * with a TRE that the hardware reports has completed. We need one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * map entry per TRE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) trans_info = &channel->trans_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) trans_info->map = kcalloc(channel->tre_count, sizeof(*trans_info->map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (!trans_info->map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* We can't use more TREs than there are available in the ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * This limits the number of transactions that can be oustanding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * Worst case is one TRE per transaction (but we actually limit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * it to something a little less than that). We allocate resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * for transactions (including transaction structures) based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * this maximum number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) tre_max = gsi_channel_tre_max(channel->gsi, channel_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* Transactions are allocated one at a time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ret = gsi_trans_pool_init(&trans_info->pool, sizeof(struct gsi_trans),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) tre_max, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) goto err_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* A transaction uses a scatterlist array to represent the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * transfers implemented by the transaction. Each scatterlist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * element is used to fill a single TRE when the transaction is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * committed. So we need as many scatterlist elements as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * maximum number of TREs that can be outstanding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * All TREs in a transaction must fit within the channel's TLV FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * A transaction on a channel can allocate as many TREs as that but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * no more.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ret = gsi_trans_pool_init(&trans_info->sg_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) sizeof(struct scatterlist),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) tre_max, channel->tlv_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) goto err_trans_pool_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* Finally, the tre_avail field is what ultimately limits the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * of outstanding transactions and their resources. A transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * allocation succeeds only if the TREs available are sufficient for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * what the transaction might need. Transaction resource pools are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * sized based on the maximum number of outstanding TREs, so there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * will always be resources available if there are TREs available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) atomic_set(&trans_info->tre_avail, tre_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) spin_lock_init(&trans_info->spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) INIT_LIST_HEAD(&trans_info->alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) INIT_LIST_HEAD(&trans_info->pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) INIT_LIST_HEAD(&trans_info->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) INIT_LIST_HEAD(&trans_info->polled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) err_trans_pool_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) gsi_trans_pool_exit(&trans_info->pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) err_kfree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) kfree(trans_info->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) dev_err(gsi->dev, "error %d initializing channel %u transactions\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ret, channel_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* Inverse of gsi_channel_trans_init() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) void gsi_channel_trans_exit(struct gsi_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct gsi_trans_info *trans_info = &channel->trans_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) gsi_trans_pool_exit(&trans_info->sg_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) gsi_trans_pool_exit(&trans_info->pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) kfree(trans_info->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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