Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2018-2020 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef _GSI_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define _GSI_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) /* === Only "gsi.c" should include this file === */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * DOC: GSI Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * GSI registers are located within the "gsi" address space defined by Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * Tree.  The offset of each register within that space is specified by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * symbols defined below.  The GSI address space is mapped to virtual memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * space in gsi_init().  All GSI registers are 32 bits wide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * Each register type is duplicated for a number of instances of something.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * For example, each GSI channel has its own set of registers defining its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * configuration.  The offset to a channel's set of registers is computed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * based on a "base" offset plus an additional "stride" amount computed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * from the channel's ID.  For such registers, the offset is computed by a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * function-like macro that takes a parameter used in the computation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * The offset of a register dependent on execution environment is computed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * by a macro that is supplied a parameter "ee".  The "ee" value is a member
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * of the gsi_ee_id enumerated type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * The offset of a channel register is computed by a macro that is supplied a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * parameter "ch".  The "ch" value is a channel id whose maximum value is 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * (though the actual limit is hardware-dependent).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * The offset of an event register is computed by a macro that is supplied a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * parameter "ev".  The "ev" value is an event id whose maximum value is 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * (though the actual limit is hardware-dependent).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define GSI_INTER_EE_SRC_CH_IRQ_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 			GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 			(0x0000c018 + 0x1000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define GSI_INTER_EE_SRC_EV_CH_IRQ_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 			GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			(0x0000c01c + 0x1000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define GSI_CH_C_CNTXT_0_OFFSET(ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		GSI_EE_N_CH_C_CNTXT_0_OFFSET((ch), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define GSI_EE_N_CH_C_CNTXT_0_OFFSET(ch, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		(0x0001c000 + 0x4000 * (ee) + 0x80 * (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CHTYPE_PROTOCOL_FMASK		GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CHTYPE_DIR_FMASK		GENMASK(3, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define EE_FMASK			GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CHID_FMASK			GENMASK(12, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* The next field is present for GSI v2.0 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CHTYPE_PROTOCOL_MSB_FMASK	GENMASK(13, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define ERINDEX_FMASK			GENMASK(18, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CHSTATE_FMASK			GENMASK(23, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define ELEMENT_SIZE_FMASK		GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define GSI_CH_C_CNTXT_1_OFFSET(ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		GSI_EE_N_CH_C_CNTXT_1_OFFSET((ch), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define GSI_EE_N_CH_C_CNTXT_1_OFFSET(ch, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		(0x0001c004 + 0x4000 * (ee) + 0x80 * (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define R_LENGTH_FMASK			GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define GSI_CH_C_CNTXT_2_OFFSET(ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		GSI_EE_N_CH_C_CNTXT_2_OFFSET((ch), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define GSI_EE_N_CH_C_CNTXT_2_OFFSET(ch, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		(0x0001c008 + 0x4000 * (ee) + 0x80 * (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define GSI_CH_C_CNTXT_3_OFFSET(ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		GSI_EE_N_CH_C_CNTXT_3_OFFSET((ch), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define GSI_EE_N_CH_C_CNTXT_3_OFFSET(ch, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		(0x0001c00c + 0x4000 * (ee) + 0x80 * (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define GSI_CH_C_QOS_OFFSET(ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		GSI_EE_N_CH_C_QOS_OFFSET((ch), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define GSI_EE_N_CH_C_QOS_OFFSET(ch, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		(0x0001c05c + 0x4000 * (ee) + 0x80 * (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define WRR_WEIGHT_FMASK		GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define MAX_PREFETCH_FMASK		GENMASK(8, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define USE_DB_ENG_FMASK		GENMASK(9, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /* The next field is present for GSI v2.0 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define USE_ESCAPE_BUF_ONLY_FMASK	GENMASK(10, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define GSI_CH_C_SCRATCH_0_OFFSET(ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		GSI_EE_N_CH_C_SCRATCH_0_OFFSET((ch), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define GSI_EE_N_CH_C_SCRATCH_0_OFFSET(ch, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		(0x0001c060 + 0x4000 * (ee) + 0x80 * (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define GSI_CH_C_SCRATCH_1_OFFSET(ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		GSI_EE_N_CH_C_SCRATCH_1_OFFSET((ch), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define GSI_EE_N_CH_C_SCRATCH_1_OFFSET(ch, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		(0x0001c064 + 0x4000 * (ee) + 0x80 * (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GSI_CH_C_SCRATCH_2_OFFSET(ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		GSI_EE_N_CH_C_SCRATCH_2_OFFSET((ch), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GSI_EE_N_CH_C_SCRATCH_2_OFFSET(ch, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		(0x0001c068 + 0x4000 * (ee) + 0x80 * (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GSI_CH_C_SCRATCH_3_OFFSET(ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		GSI_EE_N_CH_C_SCRATCH_3_OFFSET((ch), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GSI_EE_N_CH_C_SCRATCH_3_OFFSET(ch, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		(0x0001c06c + 0x4000 * (ee) + 0x80 * (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GSI_EV_CH_E_CNTXT_0_OFFSET(ev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET((ev), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET(ev, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		(0x0001d000 + 0x4000 * (ee) + 0x80 * (ev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define EV_CHTYPE_FMASK			GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define EV_EE_FMASK			GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define EV_EVCHID_FMASK			GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define EV_INTYPE_FMASK			GENMASK(16, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define EV_CHSTATE_FMASK		GENMASK(23, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define EV_ELEMENT_SIZE_FMASK		GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET((ev), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET(ev, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		(0x0001d004 + 0x4000 * (ee) + 0x80 * (ev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define EV_R_LENGTH_FMASK		GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GSI_EV_CH_E_CNTXT_2_OFFSET(ev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET((ev), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET(ev, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		(0x0001d008 + 0x4000 * (ee) + 0x80 * (ev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GSI_EV_CH_E_CNTXT_3_OFFSET(ev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET((ev), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET(ev, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		(0x0001d00c + 0x4000 * (ee) + 0x80 * (ev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GSI_EV_CH_E_CNTXT_4_OFFSET(ev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET((ev), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET(ev, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		(0x0001d010 + 0x4000 * (ee) + 0x80 * (ev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GSI_EV_CH_E_CNTXT_8_OFFSET(ev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET((ev), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET(ev, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		(0x0001d020 + 0x4000 * (ee) + 0x80 * (ev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MODT_FMASK			GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MODC_FMASK			GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MOD_CNT_FMASK			GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GSI_EV_CH_E_CNTXT_9_OFFSET(ev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET((ev), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET(ev, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		(0x0001d024 + 0x4000 * (ee) + 0x80 * (ev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GSI_EV_CH_E_CNTXT_10_OFFSET(ev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET((ev), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET(ev, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		(0x0001d028 + 0x4000 * (ee) + 0x80 * (ev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GSI_EV_CH_E_CNTXT_11_OFFSET(ev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET((ev), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET(ev, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		(0x0001d02c + 0x4000 * (ee) + 0x80 * (ev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GSI_EV_CH_E_CNTXT_12_OFFSET(ev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET((ev), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET(ev, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		(0x0001d030 + 0x4000 * (ee) + 0x80 * (ev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define GSI_EV_CH_E_CNTXT_13_OFFSET(ev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET((ev), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET(ev, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		(0x0001d034 + 0x4000 * (ee) + 0x80 * (ev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GSI_EV_CH_E_SCRATCH_0_OFFSET(ev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET((ev), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET(ev, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		(0x0001d048 + 0x4000 * (ee) + 0x80 * (ev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define GSI_EV_CH_E_SCRATCH_1_OFFSET(ev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET((ev), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET(ev, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		(0x0001d04c + 0x4000 * (ee) + 0x80 * (ev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define GSI_CH_C_DOORBELL_0_OFFSET(ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		GSI_EE_N_CH_C_DOORBELL_0_OFFSET((ch), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define GSI_EE_N_CH_C_DOORBELL_0_OFFSET(ch, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			(0x0001e000 + 0x4000 * (ee) + 0x08 * (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define GSI_EV_CH_E_DOORBELL_0_OFFSET(ev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET((ev), GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET(ev, ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			(0x0001e100 + 0x4000 * (ee) + 0x08 * (ev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define GSI_GSI_STATUS_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			GSI_EE_N_GSI_STATUS_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define GSI_EE_N_GSI_STATUS_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			(0x0001f000 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define ENABLED_FMASK			GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define GSI_CH_CMD_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			GSI_EE_N_CH_CMD_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define GSI_EE_N_CH_CMD_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			(0x0001f008 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CH_CHID_FMASK			GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CH_OPCODE_FMASK			GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define GSI_EV_CH_CMD_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			GSI_EE_N_EV_CH_CMD_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define GSI_EE_N_EV_CH_CMD_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			(0x0001f010 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define EV_CHID_FMASK			GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define EV_OPCODE_FMASK			GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define GSI_GENERIC_CMD_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			GSI_EE_N_GENERIC_CMD_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define GSI_EE_N_GENERIC_CMD_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			(0x0001f018 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define GENERIC_OPCODE_FMASK		GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define GENERIC_CHID_FMASK		GENMASK(9, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define GENERIC_EE_FMASK		GENMASK(13, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define GSI_GSI_HW_PARAM_2_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			GSI_EE_N_GSI_HW_PARAM_2_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define GSI_EE_N_GSI_HW_PARAM_2_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			(0x0001f040 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IRAM_SIZE_FMASK			GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IRAM_SIZE_ONE_KB_FVAL			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IRAM_SIZE_TWO_KB_FVAL			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* The next two values are available for GSI v2.0 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IRAM_SIZE_TWO_N_HALF_KB_FVAL		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IRAM_SIZE_THREE_KB_FVAL			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define NUM_CH_PER_EE_FMASK		GENMASK(7, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define NUM_EV_PER_EE_FMASK		GENMASK(12, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define GSI_CH_PEND_TRANSLATE_FMASK	GENMASK(13, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define GSI_CH_FULL_LOGIC_FMASK		GENMASK(14, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Fields below are present for GSI v2.0 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define GSI_USE_SDMA_FMASK		GENMASK(15, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define GSI_SDMA_N_INT_FMASK		GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define GSI_SDMA_MAX_BURST_FMASK	GENMASK(26, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define GSI_SDMA_N_IOVEC_FMASK		GENMASK(29, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Fields below are present for GSI v2.2 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define GSI_USE_RD_WR_ENG_FMASK		GENMASK(30, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define GSI_USE_INTER_EE_FMASK		GENMASK(31, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define GSI_CNTXT_TYPE_IRQ_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			(0x0001f080 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			(0x0001f088 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* The masks below are used for the TYPE_IRQ and TYPE_IRQ_MASK registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CH_CTRL_FMASK			GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define EV_CTRL_FMASK			GENMASK(1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define GLOB_EE_FMASK			GENMASK(2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IEOB_FMASK			GENMASK(3, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define INTER_EE_CH_CTRL_FMASK		GENMASK(4, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define INTER_EE_EV_CTRL_FMASK		GENMASK(5, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define GENERAL_FMASK			GENMASK(6, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define GSI_CNTXT_TYPE_IRQ_MSK_ALL	GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define GSI_CNTXT_SRC_CH_IRQ_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			(0x0001f090 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			(0x0001f094 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			(0x0001f098 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			(0x0001f09c + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			(0x0001f0a0 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			(0x0001f0a4 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define GSI_CNTXT_SRC_IEOB_IRQ_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			(0x0001f0b0 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			(0x0001f0b8 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			(0x0001f0c0 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define GSI_CNTXT_GLOB_IRQ_STTS_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			(0x0001f100 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 			GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			(0x0001f108 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 			(0x0001f110 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* The masks below are used for the general IRQ STTS, EN, and CLR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define ERROR_INT_FMASK			GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define GP_INT1_FMASK			GENMASK(1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define GP_INT2_FMASK			GENMASK(2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define GP_INT3_FMASK			GENMASK(3, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define GSI_CNTXT_GLOB_IRQ_ALL		GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			(0x0001f118 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define GSI_CNTXT_GSI_IRQ_EN_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			(0x0001f120 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			(0x0001f128 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* The masks below are used for the general IRQ STTS, EN, and CLR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define BREAK_POINT_FMASK		GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define BUS_ERROR_FMASK			GENMASK(1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define CMD_FIFO_OVRFLOW_FMASK		GENMASK(2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define MCS_STACK_OVRFLOW_FMASK		GENMASK(3, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define GSI_CNTXT_GSI_IRQ_ALL		GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define GSI_CNTXT_INTSET_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 			GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define GSI_EE_N_CNTXT_INTSET_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			(0x0001f180 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define INTYPE_FMASK			GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define GSI_ERROR_LOG_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 			GSI_EE_N_ERROR_LOG_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define GSI_EE_N_ERROR_LOG_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			(0x0001f200 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define ERR_ARG3_FMASK			GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define ERR_ARG2_FMASK			GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define ERR_ARG1_FMASK			GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define ERR_CODE_FMASK			GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define ERR_VIRT_IDX_FMASK		GENMASK(23, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define ERR_TYPE_FMASK			GENMASK(27, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define ERR_EE_FMASK			GENMASK(31, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define GSI_ERROR_LOG_CLR_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			GSI_EE_N_ERROR_LOG_CLR_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define GSI_EE_N_ERROR_LOG_CLR_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			(0x0001f210 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define GSI_CNTXT_SCRATCH_0_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 			GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(GSI_EE_AP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(ee) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 			(0x0001f400 + 0x4000 * (ee))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define INTER_EE_RESULT_FMASK		GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define GENERIC_EE_RESULT_FMASK		GENMASK(7, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define GENERIC_EE_SUCCESS_FVAL			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define GENERIC_EE_INCORRECT_DIRECTION_FVAL	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define GENERIC_EE_INCORRECT_CHANNEL_FVAL	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define GENERIC_EE_NO_RESOURCES_FVAL		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define USB_MAX_PACKET_FMASK		GENMASK(15, 15)	/* 0: HS; 1: SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define MHI_BASE_CHANNEL_FMASK		GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #endif	/* _GSI_REG_H_ */