^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Alan Ott <alan@signal11.us>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Signal 11 Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/ieee802154.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <net/cfg802154.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <net/mac802154.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* MRF24J40 Short Address Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define REG_RXMCR 0x00 /* Receive MAC control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BIT_PROMI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BIT_ERRPKT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BIT_NOACKRSP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BIT_PANCOORD BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REG_PANIDL 0x01 /* PAN ID (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REG_PANIDH 0x02 /* PAN ID (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REG_SADRL 0x03 /* Short address (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REG_SADRH 0x04 /* Short address (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REG_EADR0 0x05 /* Long address (low) (high is EADR7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REG_EADR1 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REG_EADR2 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_EADR3 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_EADR4 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_EADR5 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REG_EADR6 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_EADR7 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define REG_RXFLUSH 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define REG_ORDER 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_TXMCR 0x11 /* Transmit MAC control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TXMCR_MIN_BE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TXMCR_MIN_BE_MASK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TXMCR_CSMA_RETRIES_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TXMCR_CSMA_RETRIES_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REG_ACKTMOUT 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REG_ESLOTG1 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REG_SYMTICKL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_SYMTICKH 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define REG_PACON0 0x16 /* Power Amplifier Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_PACON1 0x17 /* Power Amplifier Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_PACON2 0x18 /* Power Amplifier Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_TXBCON0 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BIT_TXNTRIG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BIT_TXNSECEN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BIT_TXNACKREQ BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_TXG1CON 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define REG_TXG2CON 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define REG_ESLOTG23 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define REG_ESLOTG45 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define REG_ESLOTG67 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define REG_TXPEND 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define REG_WAKECON 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define REG_FROMOFFSET 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define REG_TXSTAT 0x24 /* TX MAC Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define REG_TXBCON1 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define REG_GATECLK 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define REG_TXTIME 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define REG_HSYMTMRL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define REG_HSYMTMRH 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define REG_SOFTRST 0x2A /* Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define REG_SECCON0 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define REG_SECCON1 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define REG_TXSTBL 0x2E /* TX Stabilization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define REG_RXSR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define REG_INTSTAT 0x31 /* Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BIT_TXNIF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BIT_RXIF BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define BIT_SECIF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BIT_SECIGNORE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define REG_INTCON 0x32 /* Interrupt Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BIT_TXNIE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BIT_RXIE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define BIT_SECIE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define REG_GPIO 0x33 /* GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define REG_TRISGPIO 0x34 /* GPIO direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define REG_SLPACK 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define REG_RFCTL 0x36 /* RF Control Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define BIT_RFRST BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define REG_SECCR2 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define REG_BBREG0 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define REG_BBREG1 0x39 /* Baseband Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define BIT_RXDECINV BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define REG_BBREG2 0x3A /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BBREG2_CCA_MODE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BBREG2_CCA_MODE_MASK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define REG_BBREG3 0x3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define REG_BBREG4 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define REG_BBREG6 0x3E /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define REG_CCAEDTH 0x3F /* Energy Detection Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* MRF24J40 Long Address Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define REG_RFCON0 0x200 /* RF Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RFCON0_CH_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RFCON0_CH_MASK 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RFOPT_RECOMMEND 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define REG_RFCON1 0x201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define REG_RFCON2 0x202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define REG_RFCON3 0x203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TXPWRL_MASK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TXPWRL_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TXPWRL_30 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TXPWRL_20 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TXPWRL_10 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TXPWRL_0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TXPWRS_MASK 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TXPWRS_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TXPWRS_6_3 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TXPWRS_4_9 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TXPWRS_3_7 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TXPWRS_2_8 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TXPWRS_1_9 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TXPWRS_1_2 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TXPWRS_0_5 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TXPWRS_0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define REG_RFCON5 0x205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define REG_RFCON6 0x206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define REG_RFCON7 0x207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define REG_RFCON8 0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define REG_SLPCAL0 0x209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define REG_SLPCAL1 0x20A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define REG_SLPCAL2 0x20B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define REG_RFSTATE 0x20F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define REG_RSSI 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define BIT_INTEDGE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define REG_SLPCON1 0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define REG_REMCNTL 0x224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define REG_REMCNTH 0x225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define REG_MAINCNT0 0x226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define REG_MAINCNT1 0x227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define REG_MAINCNT2 0x228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define REG_MAINCNT3 0x229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define REG_TESTMODE 0x22F /* Test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define REG_ASSOEAR0 0x230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define REG_ASSOEAR1 0x231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define REG_ASSOEAR2 0x232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define REG_ASSOEAR3 0x233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define REG_ASSOEAR4 0x234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define REG_ASSOEAR5 0x235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define REG_ASSOEAR6 0x236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define REG_ASSOEAR7 0x237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define REG_ASSOSAR0 0x238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define REG_ASSOSAR1 0x239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define REG_UNONCE0 0x240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define REG_UNONCE1 0x241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define REG_UNONCE2 0x242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define REG_UNONCE3 0x243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define REG_UNONCE4 0x244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define REG_UNONCE5 0x245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define REG_UNONCE6 0x246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define REG_UNONCE7 0x247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define REG_UNONCE8 0x248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define REG_UNONCE9 0x249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define REG_UNONCE10 0x24A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define REG_UNONCE11 0x24B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define REG_UNONCE12 0x24C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define REG_RX_FIFO 0x300 /* Receive FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Device configuration: Only channels 11-26 on page 0 are supported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MRF24J40_CHAN_MIN 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MRF24J40_CHAN_MAX 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) - ((u32)1 << MRF24J40_CHAN_MIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TX_FIFO_SIZE 128 /* From datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define RX_FIFO_SIZE 144 /* From datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SET_CHANNEL_DELAY_US 192 /* From datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) enum mrf24j40_modules { MRF24J40, MRF24J40MA, MRF24J40MC };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Device Private Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct mrf24j40 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct ieee802154_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct regmap *regmap_short;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct regmap *regmap_long;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* for writing txfifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct spi_message tx_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u8 tx_hdr_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct spi_transfer tx_hdr_trx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 tx_len_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct spi_transfer tx_len_trx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct spi_transfer tx_buf_trx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct sk_buff *tx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* post transmit message to send frame out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct spi_message tx_post_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u8 tx_post_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct spi_transfer tx_post_trx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* for protect/unprotect/read length rxfifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct spi_message rx_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u8 rx_buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct spi_transfer rx_trx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* receive handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct spi_message rx_buf_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u8 rx_addr_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct spi_transfer rx_addr_trx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u8 rx_lqi_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct spi_transfer rx_lqi_trx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u8 rx_fifo_buf[RX_FIFO_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct spi_transfer rx_fifo_buf_trx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* isr handling for reading intstat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct spi_message irq_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u8 irq_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct spi_transfer irq_trx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* regmap information for short address register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MRF24J40_SHORT_WRITE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MRF24J40_SHORT_READ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MRF24J40_SHORT_NUMREGS 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* regmap information for long address register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MRF24J40_LONG_ACCESS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MRF24J40_LONG_NUMREGS 0x38F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Read/Write SPI Commands for Short and Long Address registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MRF24J40_READSHORT(reg) ((reg) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* The datasheet indicates the theoretical maximum for SCK to be 10MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MAX_SPI_SPEED_HZ 10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define printdev(X) (&X->spi->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mrf24j40_short_reg_writeable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case REG_RXMCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case REG_PANIDL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case REG_PANIDH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) case REG_SADRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) case REG_SADRH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case REG_EADR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case REG_EADR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case REG_EADR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case REG_EADR3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case REG_EADR4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case REG_EADR5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case REG_EADR6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case REG_EADR7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case REG_RXFLUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case REG_ORDER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case REG_TXMCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) case REG_ACKTMOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case REG_ESLOTG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case REG_SYMTICKL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case REG_SYMTICKH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case REG_PACON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) case REG_PACON1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case REG_PACON2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case REG_TXBCON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) case REG_TXNCON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) case REG_TXG1CON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case REG_TXG2CON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) case REG_ESLOTG23:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case REG_ESLOTG45:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case REG_ESLOTG67:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case REG_TXPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) case REG_WAKECON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case REG_FROMOFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case REG_TXBCON1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case REG_GATECLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case REG_TXTIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case REG_HSYMTMRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) case REG_HSYMTMRH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case REG_SOFTRST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case REG_SECCON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case REG_SECCON1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case REG_TXSTBL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case REG_RXSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case REG_INTCON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case REG_TRISGPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case REG_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) case REG_RFCTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case REG_SECCR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) case REG_SLPACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) case REG_BBREG0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case REG_BBREG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case REG_BBREG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case REG_BBREG3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) case REG_BBREG4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case REG_BBREG6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case REG_CCAEDTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) mrf24j40_short_reg_readable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) bool rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* all writeable are also readable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) rc = mrf24j40_short_reg_writeable(dev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* readonly regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case REG_TXSTAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case REG_INTSTAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) mrf24j40_short_reg_volatile(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* can be changed during runtime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case REG_TXSTAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case REG_INTSTAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case REG_RXFLUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) case REG_TXNCON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) case REG_SOFTRST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case REG_RFCTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) case REG_TXBCON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) case REG_TXG1CON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case REG_TXG2CON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) case REG_TXBCON1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case REG_SECCON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case REG_RXSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case REG_SLPACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) case REG_SECCR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) case REG_BBREG6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* use them in spi_async and regmap so it's volatile */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) case REG_BBREG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) mrf24j40_short_reg_precious(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* don't clear irq line on read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) case REG_INTSTAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const struct regmap_config mrf24j40_short_regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .name = "mrf24j40_short",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .reg_bits = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .pad_bits = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .write_flag_mask = MRF24J40_SHORT_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .read_flag_mask = MRF24J40_SHORT_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .max_register = MRF24J40_SHORT_NUMREGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .writeable_reg = mrf24j40_short_reg_writeable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .readable_reg = mrf24j40_short_reg_readable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .volatile_reg = mrf24j40_short_reg_volatile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .precious_reg = mrf24j40_short_reg_precious,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) mrf24j40_long_reg_writeable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case REG_RFCON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case REG_RFCON1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case REG_RFCON2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) case REG_RFCON3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case REG_RFCON5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) case REG_RFCON6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) case REG_RFCON7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case REG_RFCON8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) case REG_SLPCAL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) case REG_SLPCON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) case REG_SLPCON1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) case REG_WAKETIMEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case REG_WAKETIMEH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) case REG_REMCNTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) case REG_REMCNTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case REG_MAINCNT0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case REG_MAINCNT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) case REG_MAINCNT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case REG_MAINCNT3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) case REG_TESTMODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case REG_ASSOEAR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case REG_ASSOEAR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case REG_ASSOEAR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case REG_ASSOEAR3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case REG_ASSOEAR4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) case REG_ASSOEAR5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case REG_ASSOEAR6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case REG_ASSOEAR7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case REG_ASSOSAR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case REG_ASSOSAR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case REG_UNONCE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) case REG_UNONCE1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case REG_UNONCE2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) case REG_UNONCE3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) case REG_UNONCE4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case REG_UNONCE5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case REG_UNONCE6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case REG_UNONCE7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case REG_UNONCE8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case REG_UNONCE9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case REG_UNONCE10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case REG_UNONCE11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case REG_UNONCE12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) mrf24j40_long_reg_readable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) bool rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* all writeable are also readable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) rc = mrf24j40_long_reg_writeable(dev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* readonly regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case REG_SLPCAL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) case REG_SLPCAL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case REG_RFSTATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case REG_RSSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mrf24j40_long_reg_volatile(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* can be changed during runtime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case REG_SLPCAL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case REG_SLPCAL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) case REG_SLPCAL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) case REG_RFSTATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case REG_RSSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case REG_MAINCNT3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static const struct regmap_config mrf24j40_long_regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .name = "mrf24j40_long",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .reg_bits = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .pad_bits = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .write_flag_mask = MRF24J40_LONG_ACCESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .read_flag_mask = MRF24J40_LONG_ACCESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .max_register = MRF24J40_LONG_NUMREGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .writeable_reg = mrf24j40_long_reg_writeable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .readable_reg = mrf24j40_long_reg_readable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .volatile_reg = mrf24j40_long_reg_volatile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int mrf24j40_long_regmap_write(void *context, const void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct spi_device *spi = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u8 buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (count > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* regmap supports read/write mask only in frist byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * long write access need to set the 12th bit, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * make special handling for write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) memcpy(buf, data, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) buf[1] |= (1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return spi_write(spi, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) mrf24j40_long_regmap_read(void *context, const void *reg, size_t reg_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) void *val, size_t val_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct spi_device *spi = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return spi_write_then_read(spi, reg, reg_size, val, val_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static const struct regmap_bus mrf24j40_long_regmap_bus = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .write = mrf24j40_long_regmap_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .read = mrf24j40_long_regmap_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .reg_format_endian_default = REGMAP_ENDIAN_BIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .val_format_endian_default = REGMAP_ENDIAN_BIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static void write_tx_buf_complete(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct mrf24j40 *devrec = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) __le16 fc = ieee802154_get_fc_from_skb(devrec->tx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u8 val = BIT_TXNTRIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (ieee802154_is_secen(fc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) val |= BIT_TXNSECEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (ieee802154_is_ackreq(fc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) val |= BIT_TXNACKREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) devrec->tx_post_msg.complete = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) devrec->tx_post_buf[0] = MRF24J40_WRITESHORT(REG_TXNCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) devrec->tx_post_buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ret = spi_async(devrec->spi, &devrec->tx_post_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dev_err(printdev(devrec), "SPI write Failed for transmit buf\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* This function relies on an undocumented write method. Once a write command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) and address is set, as many bytes of data as desired can be clocked into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) the device. The datasheet only shows setting one byte at a time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static int write_tx_buf(struct mrf24j40 *devrec, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) const u8 *data, size_t length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Range check the length. 2 bytes are used for the length fields.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (length > TX_FIFO_SIZE-2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) length = TX_FIFO_SIZE-2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) cmd = MRF24J40_WRITELONG(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) devrec->tx_hdr_buf[0] = cmd >> 8 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) devrec->tx_hdr_buf[1] = cmd & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) devrec->tx_len_buf[0] = 0x0; /* Header Length. Set to 0 for now. TODO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) devrec->tx_len_buf[1] = length; /* Total length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) devrec->tx_buf_trx.tx_buf = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) devrec->tx_buf_trx.len = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ret = spi_async(devrec->spi, &devrec->tx_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dev_err(printdev(devrec), "SPI write Failed for TX buf\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static int mrf24j40_tx(struct ieee802154_hw *hw, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct mrf24j40 *devrec = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) devrec->tx_skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return write_tx_buf(devrec, 0x000, skb->data, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int mrf24j40_ed(struct ieee802154_hw *hw, u8 *level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* TODO: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) pr_warn("mrf24j40: ed not implemented\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) *level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static int mrf24j40_start(struct ieee802154_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct mrf24j40 *devrec = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dev_dbg(printdev(devrec), "start\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* Clear TXNIE and RXIE. Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return regmap_update_bits(devrec->regmap_short, REG_INTCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) BIT_TXNIE | BIT_RXIE | BIT_SECIE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static void mrf24j40_stop(struct ieee802154_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct mrf24j40 *devrec = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) dev_dbg(printdev(devrec), "stop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Set TXNIE and RXIE. Disable Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) regmap_update_bits(devrec->regmap_short, REG_INTCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) BIT_TXNIE | BIT_RXIE, BIT_TXNIE | BIT_RXIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct mrf24j40 *devrec = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dev_dbg(printdev(devrec), "Set Channel %d\n", channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) WARN_ON(page != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) WARN_ON(channel < MRF24J40_CHAN_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) WARN_ON(channel > MRF24J40_CHAN_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Set Channel TODO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) val = (channel - 11) << RFCON0_CH_SHIFT | RFOPT_RECOMMEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ret = regmap_update_bits(devrec->regmap_long, REG_RFCON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) RFCON0_CH_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* RF Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) BIT_RFRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static int mrf24j40_filter(struct ieee802154_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct ieee802154_hw_addr_filt *filt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) unsigned long changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct mrf24j40 *devrec = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) dev_dbg(printdev(devrec), "filter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Short Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u8 addrh, addrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) addrh = le16_to_cpu(filt->short_addr) >> 8 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) addrl = le16_to_cpu(filt->short_addr) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) regmap_write(devrec->regmap_short, REG_SADRH, addrh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) regmap_write(devrec->regmap_short, REG_SADRL, addrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev_dbg(printdev(devrec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) "Set short addr to %04hx\n", filt->short_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* Device Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u8 i, addr[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) memcpy(addr, &filt->ieee_addr, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) regmap_write(devrec->regmap_short, REG_EADR0 + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) addr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) pr_debug("Set long addr to: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) pr_debug("%02hhx ", addr[7 - i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) pr_debug("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (changed & IEEE802154_AFILT_PANID_CHANGED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* PAN ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u8 panidl, panidh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) panidh = le16_to_cpu(filt->pan_id) >> 8 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) panidl = le16_to_cpu(filt->pan_id) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) regmap_write(devrec->regmap_short, REG_PANIDH, panidh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) regmap_write(devrec->regmap_short, REG_PANIDL, panidl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (changed & IEEE802154_AFILT_PANC_CHANGED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* Pan Coordinator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (filt->pan_coord)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) val = BIT_PANCOORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) BIT_PANCOORD, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * REG_ORDER is maintained as default (no beacon/superframe).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dev_dbg(printdev(devrec), "Set Pan Coord to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) filt->pan_coord ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static void mrf24j40_handle_rx_read_buf_unlock(struct mrf24j40 *devrec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Turn back on reception of packets off the air. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) devrec->rx_msg.complete = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) devrec->rx_buf[1] = 0x00; /* CLR RXDECINV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ret = spi_async(devrec->spi, &devrec->rx_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dev_err(printdev(devrec), "failed to unlock rx buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static void mrf24j40_handle_rx_read_buf_complete(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct mrf24j40 *devrec = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u8 len = devrec->rx_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) u8 rx_local_buf[RX_FIFO_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) memcpy(rx_local_buf, devrec->rx_fifo_buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) mrf24j40_handle_rx_read_buf_unlock(devrec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) skb = dev_alloc_skb(IEEE802154_MTU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) dev_err(printdev(devrec), "failed to allocate skb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) skb_put_data(skb, rx_local_buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ieee802154_rx_irqsafe(devrec->hw, skb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ", DUMP_PREFIX_OFFSET, 16, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) rx_local_buf, len, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) devrec->rx_lqi_buf[0], devrec->rx_lqi_buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static void mrf24j40_handle_rx_read_buf(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct mrf24j40 *devrec = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* if length is invalid read the full MTU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (!ieee802154_is_valid_psdu_len(devrec->rx_buf[2]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) devrec->rx_buf[2] = IEEE802154_MTU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) cmd = MRF24J40_READLONG(REG_RX_FIFO + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) devrec->rx_addr_buf[0] = cmd >> 8 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) devrec->rx_addr_buf[1] = cmd & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) devrec->rx_fifo_buf_trx.len = devrec->rx_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ret = spi_async(devrec->spi, &devrec->rx_buf_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) dev_err(printdev(devrec), "failed to read rx buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) mrf24j40_handle_rx_read_buf_unlock(devrec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static void mrf24j40_handle_rx_read_len(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct mrf24j40 *devrec = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* read the length of received frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) devrec->rx_msg.complete = mrf24j40_handle_rx_read_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) devrec->rx_trx.len = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) cmd = MRF24J40_READLONG(REG_RX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) devrec->rx_buf[0] = cmd >> 8 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) devrec->rx_buf[1] = cmd & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ret = spi_async(devrec->spi, &devrec->rx_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) dev_err(printdev(devrec), "failed to read rx buffer length\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) mrf24j40_handle_rx_read_buf_unlock(devrec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /* Turn off reception of packets off the air. This prevents the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * device from overwriting the buffer while we're reading it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) devrec->rx_msg.complete = mrf24j40_handle_rx_read_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) devrec->rx_trx.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) devrec->rx_buf[1] = BIT_RXDECINV; /* SET RXDECINV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return spi_async(devrec->spi, &devrec->rx_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) mrf24j40_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) u8 retries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct mrf24j40 *devrec = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* min_be */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) val = min_be << TXMCR_MIN_BE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* csma backoffs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) val |= retries << TXMCR_CSMA_RETRIES_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return regmap_update_bits(devrec->regmap_short, REG_TXMCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) TXMCR_MIN_BE_MASK | TXMCR_CSMA_RETRIES_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static int mrf24j40_set_cca_mode(struct ieee802154_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) const struct wpan_phy_cca *cca)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct mrf24j40 *devrec = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* mapping 802.15.4 to driver spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) switch (cca->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) case NL802154_CCA_ENERGY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) val = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) case NL802154_CCA_CARRIER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) case NL802154_CCA_ENERGY_CARRIER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) switch (cca->opt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) case NL802154_CCA_OPT_ENERGY_CARRIER_AND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) val = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return regmap_update_bits(devrec->regmap_short, REG_BBREG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) BBREG2_CCA_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) val << BBREG2_CCA_MODE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* array for representing ed levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static const s32 mrf24j40_ed_levels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) -9000, -8900, -8800, -8700, -8600, -8500, -8400, -8300, -8200, -8100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) -8000, -7900, -7800, -7700, -7600, -7500, -7400, -7300, -7200, -7100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) -7000, -6900, -6800, -6700, -6600, -6500, -6400, -6300, -6200, -6100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) -6000, -5900, -5800, -5700, -5600, -5500, -5400, -5300, -5200, -5100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) -5000, -4900, -4800, -4700, -4600, -4500, -4400, -4300, -4200, -4100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) -4000, -3900, -3800, -3700, -3600, -3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* map ed levels to register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static const s32 mrf24j40_ed_levels_map[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) { -9000, 0 }, { -8900, 1 }, { -8800, 2 }, { -8700, 5 }, { -8600, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) { -8500, 13 }, { -8400, 18 }, { -8300, 23 }, { -8200, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) { -8100, 32 }, { -8000, 37 }, { -7900, 43 }, { -7800, 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) { -7700, 53 }, { -7600, 58 }, { -7500, 63 }, { -7400, 68 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) { -7300, 73 }, { -7200, 78 }, { -7100, 83 }, { -7000, 89 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) { -6900, 95 }, { -6800, 100 }, { -6700, 107 }, { -6600, 111 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) { -6500, 117 }, { -6400, 121 }, { -6300, 125 }, { -6200, 129 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) { -6100, 133 }, { -6000, 138 }, { -5900, 143 }, { -5800, 148 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) { -5700, 153 }, { -5600, 159 }, { -5500, 165 }, { -5400, 170 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) { -5300, 176 }, { -5200, 183 }, { -5100, 188 }, { -5000, 193 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) { -4900, 198 }, { -4800, 203 }, { -4700, 207 }, { -4600, 212 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) { -4500, 216 }, { -4400, 221 }, { -4300, 225 }, { -4200, 228 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) { -4100, 233 }, { -4000, 239 }, { -3900, 245 }, { -3800, 250 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) { -3700, 253 }, { -3600, 254 }, { -3500, 255 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static int mrf24j40_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct mrf24j40 *devrec = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) for (i = 0; i < ARRAY_SIZE(mrf24j40_ed_levels_map); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (mrf24j40_ed_levels_map[i][0] == mbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return regmap_write(devrec->regmap_short, REG_CCAEDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) mrf24j40_ed_levels_map[i][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static const s32 mrf24j40ma_powers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) 0, -50, -120, -190, -280, -370, -490, -630, -1000, -1050, -1120, -1190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) -1280, -1370, -1490, -1630, -2000, -2050, -2120, -2190, -2280, -2370,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) -2490, -2630, -3000, -3050, -3120, -3190, -3280, -3370, -3490, -3630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static int mrf24j40_set_txpower(struct ieee802154_hw *hw, s32 mbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct mrf24j40 *devrec = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) s32 small_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (0 >= mbm && mbm > -1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) val = TXPWRL_0 << TXPWRL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) small_scale = mbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) } else if (-1000 >= mbm && mbm > -2000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) val = TXPWRL_10 << TXPWRL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) small_scale = mbm + 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) } else if (-2000 >= mbm && mbm > -3000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) val = TXPWRL_20 << TXPWRL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) small_scale = mbm + 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) } else if (-3000 >= mbm && mbm > -4000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) val = TXPWRL_30 << TXPWRL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) small_scale = mbm + 3000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) switch (small_scale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) val |= (TXPWRS_0 << TXPWRS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) case -50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) val |= (TXPWRS_0_5 << TXPWRS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) case -120:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) val |= (TXPWRS_1_2 << TXPWRS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) case -190:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) val |= (TXPWRS_1_9 << TXPWRS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) case -280:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) val |= (TXPWRS_2_8 << TXPWRS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) case -370:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) val |= (TXPWRS_3_7 << TXPWRS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) case -490:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) val |= (TXPWRS_4_9 << TXPWRS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) case -630:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) val |= (TXPWRS_6_3 << TXPWRS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return regmap_update_bits(devrec->regmap_long, REG_RFCON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) TXPWRL_MASK | TXPWRS_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static int mrf24j40_set_promiscuous_mode(struct ieee802154_hw *hw, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct mrf24j40 *devrec = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* set PROMI, ERRPKT and NOACKRSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /* clear PROMI, ERRPKT and NOACKRSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static const struct ieee802154_ops mrf24j40_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .xmit_async = mrf24j40_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .ed = mrf24j40_ed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .start = mrf24j40_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .stop = mrf24j40_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .set_channel = mrf24j40_set_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .set_hw_addr_filt = mrf24j40_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .set_csma_params = mrf24j40_csma_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .set_cca_mode = mrf24j40_set_cca_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .set_cca_ed_level = mrf24j40_set_cca_ed_level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .set_txpower = mrf24j40_set_txpower,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .set_promiscuous_mode = mrf24j40_set_promiscuous_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static void mrf24j40_intstat_complete(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct mrf24j40 *devrec = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) u8 intstat = devrec->irq_buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) enable_irq(devrec->spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* Ignore Rx security decryption */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (intstat & BIT_SECIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) regmap_write_async(devrec->regmap_short, REG_SECCON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) BIT_SECIGNORE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* Check for TX complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (intstat & BIT_TXNIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) ieee802154_xmit_complete(devrec->hw, devrec->tx_skb, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* Check for Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (intstat & BIT_RXIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) mrf24j40_handle_rx(devrec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static irqreturn_t mrf24j40_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct mrf24j40 *devrec = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) disable_irq_nosync(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) devrec->irq_buf[0] = MRF24J40_READSHORT(REG_INTSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) devrec->irq_buf[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* Read the interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) ret = spi_async(devrec->spi, &devrec->irq_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) enable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static int mrf24j40_hw_init(struct mrf24j40 *devrec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) u32 irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /* Initialize the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) From datasheet section 3.2: Initialization. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) ret = regmap_write(devrec->regmap_short, REG_SOFTRST, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) goto err_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) ret = regmap_write(devrec->regmap_short, REG_PACON2, 0x98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) goto err_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ret = regmap_write(devrec->regmap_short, REG_TXSTBL, 0x95);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) goto err_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ret = regmap_write(devrec->regmap_long, REG_RFCON0, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) goto err_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ret = regmap_write(devrec->regmap_long, REG_RFCON1, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) goto err_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) ret = regmap_write(devrec->regmap_long, REG_RFCON2, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) goto err_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ret = regmap_write(devrec->regmap_long, REG_RFCON6, 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) goto err_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) ret = regmap_write(devrec->regmap_long, REG_RFCON7, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) goto err_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) ret = regmap_write(devrec->regmap_long, REG_RFCON8, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) goto err_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) ret = regmap_write(devrec->regmap_long, REG_SLPCON1, 0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) goto err_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) ret = regmap_write(devrec->regmap_short, REG_BBREG2, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) goto err_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) ret = regmap_write(devrec->regmap_short, REG_CCAEDTH, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) goto err_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) ret = regmap_write(devrec->regmap_short, REG_BBREG6, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) goto err_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) goto err_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) goto err_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) udelay(192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x03, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) goto err_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (spi_get_device_id(devrec->spi)->driver_data == MRF24J40MC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* Enable external amplifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) * From MRF24J40MC datasheet section 1.3: Operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) regmap_update_bits(devrec->regmap_long, REG_TESTMODE, 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /* Set GPIO3 as output. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) regmap_update_bits(devrec->regmap_short, REG_TRISGPIO, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) /* Set GPIO3 HIGH to enable U5 voltage regulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) regmap_update_bits(devrec->regmap_short, REG_GPIO, 0x08, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* Reduce TX pwr to meet FCC requirements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) * From MRF24J40MC datasheet section 3.1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) regmap_write(devrec->regmap_long, REG_RFCON3, 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) irq_type = irq_get_trigger_type(devrec->spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (irq_type == IRQ_TYPE_EDGE_RISING ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) irq_type == IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) dev_warn(&devrec->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) "Using edge triggered irq's are not recommended, because it can cause races and result in a non-functional driver!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) switch (irq_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) /* set interrupt polarity to rising */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) ret = regmap_update_bits(devrec->regmap_long, REG_SLPCON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) BIT_INTEDGE, BIT_INTEDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) goto err_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) /* default is falling edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) err_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) mrf24j40_setup_tx_spi_messages(struct mrf24j40 *devrec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) spi_message_init(&devrec->tx_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) devrec->tx_msg.context = devrec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) devrec->tx_msg.complete = write_tx_buf_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) devrec->tx_hdr_trx.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) devrec->tx_hdr_trx.tx_buf = devrec->tx_hdr_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) spi_message_add_tail(&devrec->tx_hdr_trx, &devrec->tx_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) devrec->tx_len_trx.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) devrec->tx_len_trx.tx_buf = devrec->tx_len_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) spi_message_add_tail(&devrec->tx_len_trx, &devrec->tx_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) spi_message_add_tail(&devrec->tx_buf_trx, &devrec->tx_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) spi_message_init(&devrec->tx_post_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) devrec->tx_post_msg.context = devrec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) devrec->tx_post_trx.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) devrec->tx_post_trx.tx_buf = devrec->tx_post_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) spi_message_add_tail(&devrec->tx_post_trx, &devrec->tx_post_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) mrf24j40_setup_rx_spi_messages(struct mrf24j40 *devrec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) spi_message_init(&devrec->rx_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) devrec->rx_msg.context = devrec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) devrec->rx_trx.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) devrec->rx_trx.tx_buf = devrec->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) devrec->rx_trx.rx_buf = devrec->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) spi_message_add_tail(&devrec->rx_trx, &devrec->rx_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) spi_message_init(&devrec->rx_buf_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) devrec->rx_buf_msg.context = devrec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) devrec->rx_buf_msg.complete = mrf24j40_handle_rx_read_buf_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) devrec->rx_addr_trx.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) devrec->rx_addr_trx.tx_buf = devrec->rx_addr_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) spi_message_add_tail(&devrec->rx_addr_trx, &devrec->rx_buf_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) devrec->rx_fifo_buf_trx.rx_buf = devrec->rx_fifo_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) spi_message_add_tail(&devrec->rx_fifo_buf_trx, &devrec->rx_buf_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) devrec->rx_lqi_trx.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) devrec->rx_lqi_trx.rx_buf = devrec->rx_lqi_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) spi_message_add_tail(&devrec->rx_lqi_trx, &devrec->rx_buf_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) mrf24j40_setup_irq_spi_messages(struct mrf24j40 *devrec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) spi_message_init(&devrec->irq_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) devrec->irq_msg.context = devrec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) devrec->irq_msg.complete = mrf24j40_intstat_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) devrec->irq_trx.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) devrec->irq_trx.tx_buf = devrec->irq_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) devrec->irq_trx.rx_buf = devrec->irq_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) spi_message_add_tail(&devrec->irq_trx, &devrec->irq_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) static void mrf24j40_phy_setup(struct mrf24j40 *devrec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) ieee802154_random_extended_addr(&devrec->hw->phy->perm_extended_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) devrec->hw->phy->current_channel = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* mrf24j40 supports max_minbe 0 - 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) devrec->hw->phy->supported.max_minbe = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /* datasheet doesn't say anything about max_be, but we have min_be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * So we assume the max_be default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) devrec->hw->phy->supported.min_maxbe = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) devrec->hw->phy->supported.max_maxbe = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) devrec->hw->phy->cca.mode = NL802154_CCA_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) devrec->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) BIT(NL802154_CCA_CARRIER) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) BIT(NL802154_CCA_ENERGY_CARRIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) devrec->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) devrec->hw->phy->cca_ed_level = -6900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) devrec->hw->phy->supported.cca_ed_levels = mrf24j40_ed_levels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) devrec->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(mrf24j40_ed_levels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) switch (spi_get_device_id(devrec->spi)->driver_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) case MRF24J40:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) case MRF24J40MA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) devrec->hw->phy->supported.tx_powers = mrf24j40ma_powers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) devrec->hw->phy->supported.tx_powers_size = ARRAY_SIZE(mrf24j40ma_powers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) devrec->hw->phy->flags |= WPAN_PHY_FLAG_TXPOWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static int mrf24j40_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) int ret = -ENOMEM, irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) struct ieee802154_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) struct mrf24j40 *devrec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) dev_info(&spi->dev, "probe(). IRQ: %d\n", spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* Register with the 802154 subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) hw = ieee802154_alloc_hw(sizeof(*devrec), &mrf24j40_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) goto err_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) devrec = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) devrec->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) spi_set_drvdata(spi, devrec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) devrec->hw = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) devrec->hw->parent = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) devrec->hw->phy->supported.channels[0] = CHANNEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) devrec->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AFILT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) IEEE802154_HW_CSMA_PARAMS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) IEEE802154_HW_PROMISCUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) devrec->hw->phy->flags = WPAN_PHY_FLAG_CCA_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) WPAN_PHY_FLAG_CCA_ED_LEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) mrf24j40_setup_tx_spi_messages(devrec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) mrf24j40_setup_rx_spi_messages(devrec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) mrf24j40_setup_irq_spi_messages(devrec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) devrec->regmap_short = devm_regmap_init_spi(spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) &mrf24j40_short_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (IS_ERR(devrec->regmap_short)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) ret = PTR_ERR(devrec->regmap_short);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) dev_err(&spi->dev, "Failed to allocate short register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) goto err_register_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) devrec->regmap_long = devm_regmap_init(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) &mrf24j40_long_regmap_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) spi, &mrf24j40_long_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (IS_ERR(devrec->regmap_long)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) ret = PTR_ERR(devrec->regmap_long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) dev_err(&spi->dev, "Failed to allocate long register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) goto err_register_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (spi->max_speed_hz > MAX_SPI_SPEED_HZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) dev_warn(&spi->dev, "spi clock above possible maximum: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) MAX_SPI_SPEED_HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) goto err_register_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ret = mrf24j40_hw_init(devrec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) goto err_register_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) mrf24j40_phy_setup(devrec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /* request IRQF_TRIGGER_LOW as fallback default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) irq_type = irq_get_trigger_type(spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (!irq_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) irq_type = IRQF_TRIGGER_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ret = devm_request_irq(&spi->dev, spi->irq, mrf24j40_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) irq_type, dev_name(&spi->dev), devrec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) dev_err(printdev(devrec), "Unable to get IRQ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) goto err_register_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) dev_dbg(printdev(devrec), "registered mrf24j40\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) ret = ieee802154_register_hw(devrec->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) goto err_register_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) err_register_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ieee802154_free_hw(devrec->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) err_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static int mrf24j40_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) struct mrf24j40 *devrec = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) dev_dbg(printdev(devrec), "remove\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) ieee802154_unregister_hw(devrec->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) ieee802154_free_hw(devrec->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /* TODO: Will ieee802154_free_device() wait until ->xmit() is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * complete? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) static const struct of_device_id mrf24j40_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) { .compatible = "microchip,mrf24j40", .data = (void *)MRF24J40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) { .compatible = "microchip,mrf24j40ma", .data = (void *)MRF24J40MA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) { .compatible = "microchip,mrf24j40mc", .data = (void *)MRF24J40MC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) MODULE_DEVICE_TABLE(of, mrf24j40_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static const struct spi_device_id mrf24j40_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) { "mrf24j40", MRF24J40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) { "mrf24j40ma", MRF24J40MA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) { "mrf24j40mc", MRF24J40MC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) MODULE_DEVICE_TABLE(spi, mrf24j40_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static struct spi_driver mrf24j40_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .of_match_table = of_match_ptr(mrf24j40_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .name = "mrf24j40",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .id_table = mrf24j40_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .probe = mrf24j40_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .remove = mrf24j40_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) module_spi_driver(mrf24j40_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) MODULE_AUTHOR("Alan Ott");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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