^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for NXP MCR20A 802.15.4 Wireless-PAN Networking controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 Xue Liu <liuxuenetmail@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _MCR20A_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _MCR20A_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* Direct Accress Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DAR_IRQ_STS1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DAR_IRQ_STS2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DAR_IRQ_STS3 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DAR_PHY_CTRL1 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DAR_PHY_CTRL2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DAR_PHY_CTRL3 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DAR_RX_FRM_LEN 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DAR_PHY_CTRL4 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DAR_SRC_CTRL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DAR_SRC_ADDRS_SUM_LSB 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DAR_SRC_ADDRS_SUM_MSB 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DAR_CCA1_ED_FNL 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DAR_EVENT_TMR_LSB 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DAR_EVENT_TMR_MSB 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DAR_EVENT_TMR_USB 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DAR_TIMESTAMP_LSB 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DAR_TIMESTAMP_MSB 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DAR_TIMESTAMP_USB 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DAR_T3CMP_LSB 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DAR_T3CMP_MSB 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DAR_T3CMP_USB 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DAR_T2PRIMECMP_LSB 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DAR_T2PRIMECMP_MSB 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DAR_T1CMP_LSB 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DAR_T1CMP_MSB 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DAR_T1CMP_USB 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DAR_T2CMP_LSB 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DAR_T2CMP_MSB 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DAR_T2CMP_USB 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DAR_T4CMP_LSB 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DAR_T4CMP_MSB 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DAR_T4CMP_USB 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DAR_PLL_INT0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DAR_PLL_FRAC0_LSB 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DAR_PLL_FRAC0_MSB 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DAR_PA_PWR 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DAR_SEQ_STATE 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DAR_LQI_VALUE 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DAR_RSSI_CCA_CONT 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*------------------ 0x27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DAR_ASM_CTRL1 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DAR_ASM_CTRL2 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DAR_ASM_DATA_0 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DAR_ASM_DATA_1 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DAR_ASM_DATA_2 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DAR_ASM_DATA_3 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DAR_ASM_DATA_4 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DAR_ASM_DATA_5 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DAR_ASM_DATA_6 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DAR_ASM_DATA_7 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DAR_ASM_DATA_8 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DAR_ASM_DATA_9 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DAR_ASM_DATA_A 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DAR_ASM_DATA_B 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DAR_ASM_DATA_C 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DAR_ASM_DATA_D 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DAR_ASM_DATA_E 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DAR_ASM_DATA_F 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*----------------------- 0x3A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DAR_OVERWRITE_VER 0x3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DAR_CLK_OUT_CTRL 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DAR_PWR_MODES 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IAR_INDEX 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IAR_DATA 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Indirect Resgister Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IAR_PART_ID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IAR_XTAL_TRIM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IAR_PMC_LP_TRIM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IAR_MACPANID0_LSB 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IAR_MACPANID0_MSB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IAR_MACSHORTADDRS0_LSB 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IAR_MACSHORTADDRS0_MSB 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IAR_MACLONGADDRS0_0 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IAR_MACLONGADDRS0_8 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IAR_MACLONGADDRS0_16 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IAR_MACLONGADDRS0_24 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IAR_MACLONGADDRS0_32 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IAR_MACLONGADDRS0_40 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IAR_MACLONGADDRS0_48 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IAR_MACLONGADDRS0_56 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IAR_RX_FRAME_FILTER 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IAR_PLL_INT1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IAR_PLL_FRAC1_LSB 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IAR_PLL_FRAC1_MSB 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IAR_MACPANID1_LSB 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IAR_MACPANID1_MSB 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IAR_MACSHORTADDRS1_LSB 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IAR_MACSHORTADDRS1_MSB 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IAR_MACLONGADDRS1_0 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IAR_MACLONGADDRS1_8 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IAR_MACLONGADDRS1_16 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IAR_MACLONGADDRS1_24 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IAR_MACLONGADDRS1_32 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IAR_MACLONGADDRS1_40 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IAR_MACLONGADDRS1_48 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IAR_MACLONGADDRS1_56 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IAR_DUAL_PAN_CTRL 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IAR_DUAL_PAN_DWELL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IAR_DUAL_PAN_STS 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IAR_CCA1_THRESH 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IAR_CCA1_ED_OFFSET_COMP 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IAR_LQI_OFFSET_COMP 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IAR_CCA_CTRL 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IAR_CCA2_CORR_PEAKS 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IAR_CCA2_CORR_THRESH 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IAR_TMR_PRESCALE 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*-------------------- 0x29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IAR_GPIO_DATA 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IAR_GPIO_DIR 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IAR_GPIO_PUL_EN 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IAR_GPIO_PUL_SEL 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IAR_GPIO_DS 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*------------------ 0x2F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IAR_ANT_PAD_CTRL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IAR_MISC_PAD_CTRL 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IAR_BSM_CTRL 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*------------------- 0x33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IAR_RNG 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IAR_RX_BYTE_COUNT 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IAR_RX_WTR_MARK 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IAR_SOFT_RESET 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IAR_TXDELAY 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IAR_ACKDELAY 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IAR_SEQ_MGR_CTRL 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IAR_SEQ_MGR_STS 0x3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IAR_SEQ_T_STS 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IAR_ABORT_STS 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IAR_CCCA_BUSY_CNT 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IAR_SRC_ADDR_CHECKSUM1 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IAR_SRC_ADDR_CHECKSUM2 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IAR_SRC_TBL_VALID1 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IAR_SRC_TBL_VALID2 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IAR_FILTERFAIL_CODE1 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IAR_FILTERFAIL_CODE2 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IAR_SLOT_PRELOAD 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*-------------------- 0x46 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IAR_CORR_VT 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IAR_SYNC_CTRL 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IAR_PN_LSB_0 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IAR_PN_LSB_1 0x4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IAR_PN_MSB_0 0x4B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IAR_PN_MSB_1 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IAR_CORR_NVAL 0x4D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IAR_TX_MODE_CTRL 0x4E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IAR_SNF_THR 0x4F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IAR_FAD_THR 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IAR_ANT_AGC_CTRL 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IAR_AGC_THR1 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IAR_AGC_THR2 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IAR_AGC_HYS 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IAR_AFC 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*------------------- 0x56 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*------------------- 0x57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IAR_PHY_STS 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IAR_RX_MAX_CORR 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IAR_RX_MAX_PREAMBLE 0x5A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IAR_RSSI 0x5B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*------------------- 0x5C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*------------------- 0x5D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IAR_PLL_DIG_CTRL 0x5E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IAR_VCO_CAL 0x5F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IAR_VCO_BEST_DIFF 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IAR_VCO_BIAS 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IAR_KMOD_CTRL 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IAR_KMOD_CAL 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IAR_PA_CAL 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IAR_PA_PWRCAL 0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IAR_ATT_RSSI1 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IAR_ATT_RSSI2 0x67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IAR_RSSI_OFFSET 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IAR_RSSI_SLOPE 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IAR_RSSI_CAL1 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IAR_RSSI_CAL2 0x6B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*------------------- 0x6C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*------------------- 0x6D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IAR_XTAL_CTRL 0x6E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IAR_XTAL_COMP_MIN 0x6F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IAR_XTAL_COMP_MAX 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IAR_XTAL_GM 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*------------------- 0x72 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*------------------- 0x73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IAR_LNA_TUNE 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IAR_LNA_AGCGAIN 0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*------------------- 0x76 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*------------------- 0x77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IAR_CHF_PMA_GAIN 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IAR_CHF_IBUF 0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IAR_CHF_QBUF 0x7A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IAR_CHF_IRIN 0x7B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IAR_CHF_QRIN 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IAR_CHF_IL 0x7D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IAR_CHF_QL 0x7E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IAR_CHF_CC1 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IAR_CHF_CCL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IAR_CHF_CC2 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IAR_CHF_IROUT 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IAR_CHF_QROUT 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*------------------- 0x84 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*------------------- 0x85 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IAR_RSSI_CTRL 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*------------------- 0x87 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*------------------- 0x88 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IAR_PA_BIAS 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IAR_PA_TUNING 0x8A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*------------------- 0x8B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*------------------- 0x8C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IAR_PMC_HP_TRIM 0x8D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IAR_VREGA_TRIM 0x8E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*------------------- 0x8F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*------------------- 0x90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IAR_VCO_CTRL1 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IAR_VCO_CTRL2 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*------------------- 0x93 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*------------------- 0x94 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IAR_ANA_SPARE_OUT1 0x95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IAR_ANA_SPARE_OUT2 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IAR_ANA_SPARE_IN 0x97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IAR_MISCELLANEOUS 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*------------------- 0x99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IAR_SEQ_MGR_OVRD0 0x9A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IAR_SEQ_MGR_OVRD1 0x9B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IAR_SEQ_MGR_OVRD2 0x9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IAR_SEQ_MGR_OVRD3 0x9D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IAR_SEQ_MGR_OVRD4 0x9E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IAR_SEQ_MGR_OVRD5 0x9F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IAR_SEQ_MGR_OVRD6 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IAR_SEQ_MGR_OVRD7 0xA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*------------------- 0xA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IAR_TESTMODE_CTRL 0xA3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define IAR_DTM_CTRL1 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define IAR_DTM_CTRL2 0xA5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define IAR_ATM_CTRL1 0xA6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IAR_ATM_CTRL2 0xA7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IAR_ATM_CTRL3 0xA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*------------------- 0xA9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IAR_LIM_FE_TEST_CTRL 0xAA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IAR_CHF_TEST_CTRL 0xAB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IAR_VCO_TEST_CTRL 0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IAR_PLL_TEST_CTRL 0xAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define IAR_PA_TEST_CTRL 0xAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IAR_PMC_TEST_CTRL 0xAF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IAR_SCAN_DTM_PROTECT_1 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IAR_SCAN_DTM_PROTECT_0 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* IRQSTS1 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define DAR_IRQSTS1_RX_FRM_PEND BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define DAR_IRQSTS1_PLL_UNLOCK_IRQ BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define DAR_IRQSTS1_FILTERFAIL_IRQ BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define DAR_IRQSTS1_RXWTRMRKIRQ BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define DAR_IRQSTS1_CCAIRQ BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define DAR_IRQSTS1_RXIRQ BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define DAR_IRQSTS1_TXIRQ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define DAR_IRQSTS1_SEQIRQ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* IRQSTS2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DAR_IRQSTS2_CRCVALID BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define DAR_IRQSTS2_CCA BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define DAR_IRQSTS2_SRCADDR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define DAR_IRQSTS2_PI BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define DAR_IRQSTS2_TMRSTATUS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DAR_IRQSTS2_ASM_IRQ BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DAR_IRQSTS2_PB_ERR_IRQ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DAR_IRQSTS2_WAKE_IRQ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* IRQSTS3 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define DAR_IRQSTS3_TMR4MSK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define DAR_IRQSTS3_TMR3MSK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define DAR_IRQSTS3_TMR2MSK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define DAR_IRQSTS3_TMR1MSK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define DAR_IRQSTS3_TMR4IRQ BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define DAR_IRQSTS3_TMR3IRQ BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define DAR_IRQSTS3_TMR2IRQ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define DAR_IRQSTS3_TMR1IRQ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* PHY_CTRL1 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define DAR_PHY_CTRL1_TMRTRIGEN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define DAR_PHY_CTRL1_SLOTTED BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define DAR_PHY_CTRL1_CCABFRTX BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define DAR_PHY_CTRL1_CCABFRTX_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define DAR_PHY_CTRL1_RXACKRQD BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define DAR_PHY_CTRL1_AUTOACK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define DAR_PHY_CTRL1_XCVSEQ_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* PHY_CTRL2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define DAR_PHY_CTRL2_CRC_MSK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define DAR_PHY_CTRL2_PLL_UNLOCK_MSK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define DAR_PHY_CTRL2_FILTERFAIL_MSK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define DAR_PHY_CTRL2_RX_WMRK_MSK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define DAR_PHY_CTRL2_CCAMSK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DAR_PHY_CTRL2_RXMSK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DAR_PHY_CTRL2_TXMSK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define DAR_PHY_CTRL2_SEQMSK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* PHY_CTRL3 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define DAR_PHY_CTRL3_TMR4CMP_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define DAR_PHY_CTRL3_TMR3CMP_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define DAR_PHY_CTRL3_TMR2CMP_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define DAR_PHY_CTRL3_TMR1CMP_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define DAR_PHY_CTRL3_ASM_MSK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define DAR_PHY_CTRL3_PB_ERR_MSK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define DAR_PHY_CTRL3_WAKE_MSK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* RX_FRM_LEN bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define DAR_RX_FRAME_LENGTH_MASK (0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* PHY_CTRL4 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define DAR_PHY_CTRL4_TRCV_MSK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define DAR_PHY_CTRL4_TC3TMOUT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define DAR_PHY_CTRL4_PANCORDNTR0 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define DAR_PHY_CTRL4_CCATYPE (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define DAR_PHY_CTRL4_CCATYPE_SHIFT (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define DAR_PHY_CTRL4_CCATYPE_MASK (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define DAR_PHY_CTRL4_TMRLOAD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define DAR_PHY_CTRL4_PROMISCUOUS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define DAR_PHY_CTRL4_TC2PRIME_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* SRC_CTRL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define DAR_SRC_CTRL_INDEX (0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define DAR_SRC_CTRL_INDEX_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define DAR_SRC_CTRL_ACK_FRM_PND BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define DAR_SRC_CTRL_SRCADDR_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define DAR_SRC_CTRL_INDEX_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define DAR_SRC_CTRL_INDEX_DISABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* DAR_ASM_CTRL1 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define DAR_ASM_CTRL1_CLEAR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define DAR_ASM_CTRL1_START BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define DAR_ASM_CTRL1_SELFTST BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define DAR_ASM_CTRL1_CTR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define DAR_ASM_CTRL1_CBC BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define DAR_ASM_CTRL1_AES BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define DAR_ASM_CTRL1_LOAD_MAC BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* DAR_ASM_CTRL2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define DAR_ASM_CTRL2_DATA_REG_TYPE_SEL (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define DAR_ASM_CTRL2_DATA_REG_TYPE_SEL_SHIFT (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define DAR_ASM_CTRL2_TSTPAS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* DAR_CLK_OUT_CTRL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define DAR_CLK_OUT_CTRL_EXTEND BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define DAR_CLK_OUT_CTRL_HIZ BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define DAR_CLK_OUT_CTRL_SR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define DAR_CLK_OUT_CTRL_DS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define DAR_CLK_OUT_CTRL_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define DAR_CLK_OUT_CTRL_DIV (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* DAR_PWR_MODES bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define DAR_PWR_MODES_XTAL_READY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define DAR_PWR_MODES_XTALEN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define DAR_PWR_MODES_ASM_CLK_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define DAR_PWR_MODES_AUTODOZE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define DAR_PWR_MODES_PMC_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* RX_FRAME_FILTER bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define IAR_RX_FRAME_FLT_FRM_VER (0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define IAR_RX_FRAME_FLT_FRM_VER_SHIFT (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define IAR_RX_FRAME_FLT_ACTIVE_PROMISCUOUS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define IAR_RX_FRAME_FLT_NS_FT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define IAR_RX_FRAME_FLT_CMD_FT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define IAR_RX_FRAME_FLT_ACK_FT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define IAR_RX_FRAME_FLT_DATA_FT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define IAR_RX_FRAME_FLT_BEACON_FT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* DUAL_PAN_CTRL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK (0xF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define IAR_DUAL_PAN_CTRL_CURRENT_NETWORK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define IAR_DUAL_PAN_CTRL_PANCORDNTR1 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define IAR_DUAL_PAN_CTRL_DUAL_PAN_AUTO BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define IAR_DUAL_PAN_CTRL_ACTIVE_NETWORK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* DUAL_PAN_STS bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define IAR_DUAL_PAN_STS_RECD_ON_PAN1 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define IAR_DUAL_PAN_STS_RECD_ON_PAN0 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define IAR_DUAL_PAN_STS_DUAL_PAN_REMAIN (0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* CCA_CTRL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define IAR_CCA_CTRL_AGC_FRZ_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define IAR_CCA_CTRL_CONT_RSSI_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define IAR_CCA_CTRL_LQI_RSSI_NOT_CORR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define IAR_CCA_CTRL_CCA3_AND_NOT_OR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define IAR_CCA_CTRL_POWER_COMP_EN_LQI BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define IAR_CCA_CTRL_POWER_COMP_EN_ED BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define IAR_CCA_CTRL_POWER_COMP_EN_CCA1 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* ANT_PAD_CTRL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define IAR_ANT_PAD_CTRL_ANTX_POL (0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define IAR_ANT_PAD_CTRL_ANTX_POL_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define IAR_ANT_PAD_CTRL_ANTX_CTRLMODE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define IAR_ANT_PAD_CTRL_ANTX_HZ BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define IAR_ANT_PAD_CTRL_ANTX_EN (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* MISC_PAD_CTRL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define IAR_MISC_PAD_CTRL_MISO_HIZ_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define IAR_MISC_PAD_CTRL_IRQ_B_OD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define IAR_MISC_PAD_CTRL_NON_GPIO_DS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define IAR_MISC_PAD_CTRL_ANTX_CURR (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* ANT_AGC_CTRL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define IAR_ANT_AGC_CTRL_FAD_EN_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define IAR_ANT_AGC_CTRL_FAD_EN_MASK (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define IAR_ANT_AGC_CTRL_ANTX_SHIFT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define IAR_ANT_AGC_CTRL_ANTX_MASK BIT(AR_ANT_AGC_CTRL_ANTX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* BSM_CTRL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define BSM_CTRL_BSM_EN (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* SOFT_RESET bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define IAR_SOFT_RESET_SOG_RST BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define IAR_SOFT_RESET_REGS_RST BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define IAR_SOFT_RESET_PLL_RST BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define IAR_SOFT_RESET_TX_RST BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define IAR_SOFT_RESET_RX_RST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define IAR_SOFT_RESET_SEQ_MGR_RST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* SEQ_MGR_CTRL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define IAR_SEQ_MGR_CTRL_SEQ_STATE_CTRL (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define IAR_SEQ_MGR_CTRL_SEQ_STATE_CTRL_SHIFT (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define IAR_SEQ_MGR_CTRL_NO_RX_RECYCLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define IAR_SEQ_MGR_CTRL_LATCH_PREAMBLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define IAR_SEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define IAR_SEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define IAR_SEQ_MGR_CTRL_PSM_LOCK_DIS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define IAR_SEQ_MGR_CTRL_PLL_ABORT_OVRD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* SEQ_MGR_STS bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define IAR_SEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define IAR_SEQ_MGR_STS_RX_MODE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define IAR_SEQ_MGR_STS_RX_TIMEOUT_PENDING BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define IAR_SEQ_MGR_STS_NEW_SEQ_INHIBIT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define IAR_SEQ_MGR_STS_SEQ_IDLE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define IAR_SEQ_MGR_STS_XCVSEQ_ACTUAL (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* ABORT_STS bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define IAR_ABORT_STS_PLL_ABORTED BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define IAR_ABORT_STS_TC3_ABORTED BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define IAR_ABORT_STS_SW_ABORTED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* IAR_FILTERFAIL_CODE2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define IAR_FILTERFAIL_CODE2_PAN_SEL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define IAR_FILTERFAIL_CODE2_9_8 (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* PHY_STS bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define IAR_PHY_STS_PLL_UNLOCK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define IAR_PHY_STS_PLL_LOCK_ERR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define IAR_PHY_STS_PLL_LOCK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define IAR_PHY_STS_CRCVALID BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define IAR_PHY_STS_FILTERFAIL_FLAG_SEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define IAR_PHY_STS_SFD_DET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define IAR_PHY_STS_PREAMBLE_DET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* TESTMODE_CTRL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define IAR_TEST_MODE_CTRL_HOT_ANT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define IAR_TEST_MODE_CTRL_IDEAL_RSSI_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define IAR_TEST_MODE_CTRL_IDEAL_PFC_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define IAR_TEST_MODE_CTRL_CONTINUOUS_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define IAR_TEST_MODE_CTRL_FPGA_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* DTM_CTRL1 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define IAR_DTM_CTRL1_ATM_LOCKED BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define IAR_DTM_CTRL1_DTM_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define IAR_DTM_CTRL1_PAGE5 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define IAR_DTM_CTRL1_PAGE4 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define IAR_DTM_CTRL1_PAGE3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define IAR_DTM_CTRL1_PAGE2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define IAR_DTM_CTRL1_PAGE1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define IAR_DTM_CTRL1_PAGE0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* TX_MODE_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define IAR_TX_MODE_CTRL_TX_INV BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define IAR_TX_MODE_CTRL_BT_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define IAR_TX_MODE_CTRL_DTS2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define IAR_TX_MODE_CTRL_DTS1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define IAR_TX_MODE_CTRL_DTS0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define TX_MODE_CTRL_DTS_MASK (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #endif /* _MCR20A_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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