^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * http://www.cascoda.com/products/ca-821x/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016, Cascoda, Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This code is dual-licensed under both GPLv2 and 3-clause BSD. What follows is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the license notice for both respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * modify it under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * as published by the Free Software Foundation; either version 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * of the License, or (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * modification, are permitted provided that the following conditions are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * 1. Redistributions of source code must retain the above copyright notice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 2. Redistributions in binary form must reproduce the above copyright notice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * this list of conditions and the following disclaimer in the documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * and/or other materials provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * 3. Neither the name of the copyright holder nor the names of its contributors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * may be used to endorse or promote products derived from this software without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/cdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/ieee802154.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/kfifo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/poll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include <net/ieee802154_netdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include <net/mac802154.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DRIVER_NAME "ca8210"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* external clock frequencies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ONE_MHZ 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TWO_MHZ (2 * ONE_MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define FOUR_MHZ (4 * ONE_MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define EIGHT_MHZ (8 * ONE_MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SIXTEEN_MHZ (16 * ONE_MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* spi constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CA8210_SPI_BUF_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CA8210_SYNC_TIMEOUT 1000 /* Timeout for synchronous commands [ms] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* test interface constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CA8210_TEST_INT_FILE_NAME "ca8210_test"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CA8210_TEST_INT_FIFO_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* MAC status enumerations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MAC_SUCCESS (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MAC_ERROR (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MAC_CANCELLED (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MAC_READY_FOR_POLL (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MAC_COUNTER_ERROR (0xDB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MAC_IMPROPER_KEY_TYPE (0xDC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MAC_IMPROPER_SECURITY_LEVEL (0xDD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MAC_UNSUPPORTED_LEGACY (0xDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MAC_UNSUPPORTED_SECURITY (0xDF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MAC_BEACON_LOST (0xE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MAC_CHANNEL_ACCESS_FAILURE (0xE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MAC_DENIED (0xE2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MAC_DISABLE_TRX_FAILURE (0xE3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MAC_SECURITY_ERROR (0xE4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MAC_FRAME_TOO_LONG (0xE5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MAC_INVALID_GTS (0xE6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MAC_INVALID_HANDLE (0xE7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MAC_INVALID_PARAMETER (0xE8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MAC_NO_ACK (0xE9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MAC_NO_BEACON (0xEA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MAC_NO_DATA (0xEB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MAC_NO_SHORT_ADDRESS (0xEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MAC_OUT_OF_CAP (0xED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MAC_PAN_ID_CONFLICT (0xEE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MAC_REALIGNMENT (0xEF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MAC_TRANSACTION_EXPIRED (0xF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MAC_TRANSACTION_OVERFLOW (0xF1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MAC_TX_ACTIVE (0xF2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MAC_UNAVAILABLE_KEY (0xF3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MAC_UNSUPPORTED_ATTRIBUTE (0xF4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MAC_INVALID_ADDRESS (0xF5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MAC_ON_TIME_TOO_LONG (0xF6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MAC_PAST_TIME (0xF7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MAC_TRACKING_OFF (0xF8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MAC_INVALID_INDEX (0xF9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MAC_LIMIT_REACHED (0xFA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MAC_READ_ONLY (0xFB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MAC_SCAN_IN_PROGRESS (0xFC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MAC_SUPERFRAME_OVERLAP (0xFD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MAC_SYSTEM_ERROR (0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* HWME attribute IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define HWME_EDTHRESHOLD (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HWME_EDVALUE (0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define HWME_SYSCLKOUT (0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HWME_LQILIMIT (0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* TDME attribute IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TDME_CHANNEL (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TDME_ATM_CONFIG (0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MAX_HWME_ATTRIBUTE_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MAX_TDME_ATTRIBUTE_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* PHY/MAC PIB Attribute Enumerations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PHY_CURRENT_CHANNEL (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PHY_TRANSMIT_POWER (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PHY_CCA_MODE (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MAC_ASSOCIATION_PERMIT (0x41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MAC_AUTO_REQUEST (0x42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MAC_BATT_LIFE_EXT (0x43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MAC_BATT_LIFE_EXT_PERIODS (0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MAC_BEACON_PAYLOAD (0x45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MAC_BEACON_PAYLOAD_LENGTH (0x46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MAC_BEACON_ORDER (0x47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MAC_GTS_PERMIT (0x4d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MAC_MAX_CSMA_BACKOFFS (0x4e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MAC_MIN_BE (0x4f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MAC_PAN_ID (0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MAC_PROMISCUOUS_MODE (0x51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MAC_RX_ON_WHEN_IDLE (0x52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MAC_SHORT_ADDRESS (0x53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MAC_SUPERFRAME_ORDER (0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MAC_ASSOCIATED_PAN_COORD (0x56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MAC_MAX_BE (0x57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MAC_MAX_FRAME_RETRIES (0x59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MAC_RESPONSE_WAIT_TIME (0x5A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MAC_SECURITY_ENABLED (0x5D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MAC_AUTO_REQUEST_SECURITY_LEVEL (0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MAC_AUTO_REQUEST_KEY_ID_MODE (0x79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define NS_IEEE_ADDRESS (0xFF) /* Non-standard IEEE address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* MAC Address Mode Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MAC_MODE_NO_ADDR (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MAC_MODE_SHORT_ADDR (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MAC_MODE_LONG_ADDR (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* MAC constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MAX_BEACON_OVERHEAD (75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MAX_BEACON_PAYLOAD_LENGTH (IEEE802154_MTU - MAX_BEACON_OVERHEAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MAX_ATTRIBUTE_SIZE (122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MAX_DATA_SIZE (114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CA8210_VALID_CHANNELS (0x07FFF800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* MAC workarounds for V1.1 and MPW silicon (V0.x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CA8210_MAC_WORKAROUNDS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CA8210_MAC_MPW (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* memory manipulation macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define LS_BYTE(x) ((u8)((x) & 0xFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define MS_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* message ID codes in SPI commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* downstream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MCPS_DATA_REQUEST (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MLME_ASSOCIATE_REQUEST (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MLME_ASSOCIATE_RESPONSE (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MLME_DISASSOCIATE_REQUEST (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MLME_GET_REQUEST (0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MLME_ORPHAN_RESPONSE (0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MLME_RESET_REQUEST (0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MLME_RX_ENABLE_REQUEST (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MLME_SCAN_REQUEST (0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MLME_SET_REQUEST (0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MLME_START_REQUEST (0x0B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MLME_POLL_REQUEST (0x0D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define HWME_SET_REQUEST (0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define HWME_GET_REQUEST (0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TDME_SETSFR_REQUEST (0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TDME_GETSFR_REQUEST (0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TDME_SET_REQUEST (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* upstream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MCPS_DATA_INDICATION (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MCPS_DATA_CONFIRM (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MLME_RESET_CONFIRM (0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MLME_SET_CONFIRM (0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MLME_START_CONFIRM (0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define HWME_SET_CONFIRM (0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define HWME_GET_CONFIRM (0x13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define HWME_WAKEUP_INDICATION (0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define TDME_SETSFR_CONFIRM (0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* SPI command IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* bit indicating a confirm or indication from slave to master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SPI_S2M (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* bit indicating a synchronous message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SPI_SYN (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* SPI command definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SPI_IDLE (0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SPI_NACK (0xF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SPI_MCPS_DATA_REQUEST (MCPS_DATA_REQUEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SPI_MCPS_DATA_INDICATION (MCPS_DATA_INDICATION + SPI_S2M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SPI_MCPS_DATA_CONFIRM (MCPS_DATA_CONFIRM + SPI_S2M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SPI_MLME_ASSOCIATE_REQUEST (MLME_ASSOCIATE_REQUEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SPI_MLME_RESET_REQUEST (MLME_RESET_REQUEST + SPI_SYN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SPI_MLME_SET_REQUEST (MLME_SET_REQUEST + SPI_SYN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SPI_MLME_START_REQUEST (MLME_START_REQUEST + SPI_SYN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SPI_MLME_RESET_CONFIRM (MLME_RESET_CONFIRM + SPI_S2M + SPI_SYN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SPI_MLME_SET_CONFIRM (MLME_SET_CONFIRM + SPI_S2M + SPI_SYN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SPI_MLME_START_CONFIRM (MLME_START_CONFIRM + SPI_S2M + SPI_SYN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SPI_HWME_SET_REQUEST (HWME_SET_REQUEST + SPI_SYN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SPI_HWME_GET_REQUEST (HWME_GET_REQUEST + SPI_SYN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SPI_HWME_SET_CONFIRM (HWME_SET_CONFIRM + SPI_S2M + SPI_SYN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SPI_HWME_GET_CONFIRM (HWME_GET_CONFIRM + SPI_S2M + SPI_SYN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SPI_HWME_WAKEUP_INDICATION (HWME_WAKEUP_INDICATION + SPI_S2M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SPI_TDME_SETSFR_REQUEST (TDME_SETSFR_REQUEST + SPI_SYN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SPI_TDME_SET_REQUEST (TDME_SET_REQUEST + SPI_SYN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SPI_TDME_SETSFR_CONFIRM (TDME_SETSFR_CONFIRM + SPI_S2M + SPI_SYN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* TDME SFR addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Page 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CA8210_SFR_PACFG (0xB1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CA8210_SFR_MACCON (0xD8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CA8210_SFR_PACFGIB (0xFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Page 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CA8210_SFR_LOTXCAL (0xBF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CA8210_SFR_PTHRH (0xD1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CA8210_SFR_PRECFG (0xD3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CA8210_SFR_LNAGX40 (0xE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CA8210_SFR_LNAGX41 (0xE2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CA8210_SFR_LNAGX42 (0xE3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CA8210_SFR_LNAGX43 (0xE4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CA8210_SFR_LNAGX44 (0xE5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CA8210_SFR_LNAGX45 (0xE6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CA8210_SFR_LNAGX46 (0xE7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CA8210_SFR_LNAGX47 (0xE9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define PACFGIB_DEFAULT_CURRENT (0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define PTHRH_DEFAULT_THRESHOLD (0x5A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define LNAGX40_DEFAULT_GAIN (0x29) /* 10dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define LNAGX41_DEFAULT_GAIN (0x54) /* 21dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define LNAGX42_DEFAULT_GAIN (0x6C) /* 27dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define LNAGX43_DEFAULT_GAIN (0x7A) /* 30dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define LNAGX44_DEFAULT_GAIN (0x84) /* 33dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define LNAGX45_DEFAULT_GAIN (0x8B) /* 34dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define LNAGX46_DEFAULT_GAIN (0x92) /* 36dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define LNAGX47_DEFAULT_GAIN (0x96) /* 37dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define CA8210_IOCTL_HARD_RESET (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Structs/Enums */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * struct cas_control - spi transfer structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * @msg: spi_message for each exchange
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * @transfer: spi_transfer for each exchange
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * @tx_buf: source array for transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * @tx_in_buf: array storing bytes received during transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * @priv: pointer to private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * This structure stores all the necessary data passed around during a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * spi exchange.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct cas_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct spi_transfer transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u8 tx_buf[CA8210_SPI_BUF_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u8 tx_in_buf[CA8210_SPI_BUF_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct ca8210_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * struct ca8210_test - ca8210 test interface structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * @ca8210_dfs_spi_int: pointer to the entry in the debug fs for this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * @up_fifo: fifo for upstream messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * This structure stores all the data pertaining to the debug interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct ca8210_test {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct dentry *ca8210_dfs_spi_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct kfifo up_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) wait_queue_head_t readq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * struct ca8210_priv - ca8210 private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * @spi: pointer to the ca8210 spi device object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * @hw: pointer to the ca8210 ieee802154_hw object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * @hw_registered: true if hw has been registered with ieee802154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * @lock: spinlock protecting the private data area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * @mlme_workqueue: workqueue for triggering MLME Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * @irq_workqueue: workqueue for irq processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * @tx_skb: current socket buffer to transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * @nextmsduhandle: msdu handle to pass to the 15.4 MAC layer for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * next transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * @clk: external clock provided by the ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * @last_dsn: sequence number of last data packet received, for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * resend detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * @test: test interface data section for this instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * @async_tx_pending: true if an asynchronous transmission was started and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * is not complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * @sync_command_response: pointer to buffer to fill with sync response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * @ca8210_is_awake: nonzero if ca8210 is initialised, ready for comms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * @sync_down: counts number of downstream synchronous commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * @sync_up: counts number of upstream synchronous commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * @spi_transfer_complete completion object for a single spi_transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * @sync_exchange_complete completion object for a complete synchronous API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * exchange
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * @promiscuous whether the ca8210 is in promiscuous mode or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * @retries: records how many times the current pending spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * transfer has been retried
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct ca8210_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct ieee802154_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) bool hw_registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct workqueue_struct *mlme_workqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct workqueue_struct *irq_workqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct sk_buff *tx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u8 nextmsduhandle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int last_dsn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct ca8210_test test;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) bool async_tx_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u8 *sync_command_response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct completion ca8210_is_awake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int sync_down, sync_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct completion spi_transfer_complete, sync_exchange_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) bool promiscuous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * struct work_priv_container - link between a work object and the relevant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * device's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * @work: work object being executed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * @priv: device's private data section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct work_priv_container {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct ca8210_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * struct ca8210_platform_data - ca8210 platform data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * @extclockenable: true if the external clock is to be enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * @extclockfreq: frequency of the external clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * @extclockgpio: ca8210 output gpio of the external clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * @gpio_reset: gpio number of ca8210 reset line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * @gpio_irq: gpio number of ca8210 interrupt line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * @irq_id: identifier for the ca8210 irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct ca8210_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) bool extclockenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned int extclockfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned int extclockgpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int gpio_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int gpio_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int irq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * struct fulladdr - full MAC addressing information structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * @mode: address mode (none, short, extended)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * @pan_id: 16-bit LE pan id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * @address: LE address, variable length as specified by mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct fulladdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u8 pan_id[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u8 address[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * union macaddr: generic MAC address container
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * @short_addr: 16-bit short address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * @ieee_address: 64-bit extended address as LE byte array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) union macaddr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u16 short_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u8 ieee_address[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * struct secspec: security specification for SAP commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * @security_level: 0-7, controls level of authentication & encryption
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * @key_id_mode: 0-3, specifies how to obtain key
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * @key_source: extended key retrieval data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * @key_index: single-byte key identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct secspec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u8 security_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u8 key_id_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u8 key_source[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u8 key_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* downlink functions parameter set definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct mcps_data_request_pset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u8 src_addr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct fulladdr dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u8 msdu_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u8 msdu_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u8 tx_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u8 msdu[MAX_DATA_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct mlme_set_request_pset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u8 pib_attribute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u8 pib_attribute_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u8 pib_attribute_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u8 pib_attribute_value[MAX_ATTRIBUTE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct hwme_set_request_pset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u8 hw_attribute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u8 hw_attribute_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u8 hw_attribute_value[MAX_HWME_ATTRIBUTE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct hwme_get_request_pset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u8 hw_attribute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct tdme_setsfr_request_pset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u8 sfr_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u8 sfr_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u8 sfr_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* uplink functions parameter set definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct hwme_set_confirm_pset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u8 hw_attribute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct hwme_get_confirm_pset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u8 hw_attribute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u8 hw_attribute_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u8 hw_attribute_value[MAX_HWME_ATTRIBUTE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct tdme_setsfr_confirm_pset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u8 sfr_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u8 sfr_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct mac_message {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u8 command_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u8 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct mcps_data_request_pset data_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct mlme_set_request_pset set_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct hwme_set_request_pset hwme_set_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct hwme_get_request_pset hwme_get_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct tdme_setsfr_request_pset tdme_set_sfr_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct hwme_set_confirm_pset hwme_set_cnf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct hwme_get_confirm_pset hwme_get_cnf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct tdme_setsfr_confirm_pset tdme_set_sfr_cnf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u8 u8param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u8 payload[148];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) } pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) union pa_cfg_sfr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u8 bias_current_trim : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u8 /* reserved */ : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u8 buffer_capacitor_trim : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u8 boost : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u8 paib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct preamble_cfg_sfr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u8 timeout_symbols : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u8 acquisition_symbols : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u8 search_symbols : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static int (*cascoda_api_upstream)(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) const u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) void *device_ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * link_to_linux_err() - Translates an 802.15.4 return code into the closest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * linux error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * @link_status: 802.15.4 status code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * Return: 0 or Linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int link_to_linux_err(int link_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (link_status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* status is already a Linux code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return link_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) switch (link_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) case MAC_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) case MAC_REALIGNMENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) case MAC_IMPROPER_KEY_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return -EKEYREJECTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case MAC_IMPROPER_SECURITY_LEVEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) case MAC_UNSUPPORTED_LEGACY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) case MAC_DENIED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case MAC_BEACON_LOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case MAC_NO_ACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case MAC_NO_BEACON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return -ENETUNREACH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case MAC_CHANNEL_ACCESS_FAILURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) case MAC_TX_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) case MAC_SCAN_IN_PROGRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case MAC_DISABLE_TRX_FAILURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) case MAC_OUT_OF_CAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case MAC_FRAME_TOO_LONG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return -EMSGSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case MAC_INVALID_GTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case MAC_PAST_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return -EBADSLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case MAC_INVALID_HANDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case MAC_INVALID_PARAMETER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) case MAC_UNSUPPORTED_ATTRIBUTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case MAC_ON_TIME_TOO_LONG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) case MAC_INVALID_INDEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case MAC_NO_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) case MAC_NO_SHORT_ADDRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) case MAC_PAN_ID_CONFLICT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return -EADDRINUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) case MAC_TRANSACTION_EXPIRED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) case MAC_TRANSACTION_OVERFLOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return -ENOBUFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) case MAC_UNAVAILABLE_KEY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return -ENOKEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) case MAC_INVALID_ADDRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case MAC_TRACKING_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case MAC_SUPERFRAME_OVERLAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case MAC_LIMIT_REACHED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return -EDQUOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) case MAC_READ_ONLY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return -EROFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * ca8210_test_int_driver_write() - Writes a message to the test interface to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * read by the userspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * @buf: Buffer containing upstream message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * @len: length of message to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * @spi: SPI device of message originator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static int ca8210_test_int_driver_write(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) const u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) void *spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct ca8210_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct ca8210_test *test = &priv->test;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) char *fifo_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) dev_dbg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) "test_interface: Buffering upstream message:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dev_dbg(&priv->spi->dev, "%#03x\n", buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) fifo_buffer = kmemdup(buf, len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (!fifo_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) kfifo_in(&test->up_fifo, &fifo_buffer, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) wake_up_interruptible(&priv->test.readq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* SPI Operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static int ca8210_net_rx(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct ieee802154_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u8 *command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) size_t len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static u8 mlme_reset_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) u8 set_default_pib,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) void *device_ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static int ca8210_spi_transfer(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) const u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) size_t len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * ca8210_reset_send() - Hard resets the ca8210 for a given time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * @spi: Pointer to target ca8210 spi device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * @ms: Milliseconds to hold the reset line low for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static void ca8210_reset_send(struct spi_device *spi, unsigned int ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct ca8210_platform_data *pdata = spi->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct ca8210_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) gpio_set_value(pdata->gpio_reset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) reinit_completion(&priv->ca8210_is_awake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) msleep(ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) gpio_set_value(pdata->gpio_reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) priv->promiscuous = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* Wait until wakeup indication seen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) status = wait_for_completion_interruptible_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) &priv->ca8210_is_awake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) msecs_to_jiffies(CA8210_SYNC_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dev_crit(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) &spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) "Fatal: No wakeup from ca8210 after reset!\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) dev_dbg(&spi->dev, "Reset the device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * ca8210_mlme_reset_worker() - Resets the MLME, Called when the MAC OVERFLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * condition happens.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * @work: Pointer to work being executed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static void ca8210_mlme_reset_worker(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct work_priv_container *wpc = container_of(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct work_priv_container,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct ca8210_priv *priv = wpc->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) mlme_reset_request_sync(0, priv->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) kfree(wpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * ca8210_rx_done() - Calls various message dispatches responding to a received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * @arg: Pointer to the cas_control object for the relevant spi transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * Presents a received SAP command from the ca8210 to the Cascoda EVBME, test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * interface and network driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static void ca8210_rx_done(struct cas_control *cas_ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct work_priv_container *mlme_reset_wpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct ca8210_priv *priv = cas_ctl->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) buf = cas_ctl->tx_in_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) len = buf[1] + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (len > CA8210_SPI_BUF_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dev_crit(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) "Received packet len (%u) erroneously long\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (buf[0] & SPI_SYN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (priv->sync_command_response) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) memcpy(priv->sync_command_response, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) complete(&priv->sync_exchange_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (cascoda_api_upstream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) cascoda_api_upstream(buf, len, priv->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) priv->sync_up++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (cascoda_api_upstream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) cascoda_api_upstream(buf, len, priv->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ca8210_net_rx(priv->hw, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (buf[0] == SPI_MCPS_DATA_CONFIRM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (buf[3] == MAC_TRANSACTION_OVERFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) dev_info(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) "Waiting for transaction overflow to stabilise...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) msleep(2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dev_info(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) "Resetting MAC...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) mlme_reset_wpc = kmalloc(sizeof(*mlme_reset_wpc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (!mlme_reset_wpc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) INIT_WORK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) &mlme_reset_wpc->work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ca8210_mlme_reset_worker
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) mlme_reset_wpc->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) queue_work(priv->mlme_workqueue, &mlme_reset_wpc->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) } else if (buf[0] == SPI_HWME_WAKEUP_INDICATION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) dev_notice(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) "Wakeup indication received, reason:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) switch (buf[2]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dev_notice(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) "Transceiver woken up from Power Up / System Reset\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dev_notice(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) "Watchdog Timer Time-Out\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) dev_notice(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) "Transceiver woken up from Power-Off by Sleep Timer Time-Out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dev_notice(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) "Transceiver woken up from Power-Off by GPIO Activity\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dev_notice(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) "Transceiver woken up from Standby by Sleep Timer Time-Out\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) dev_notice(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) "Transceiver woken up from Standby by GPIO Activity\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) dev_notice(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) "Sleep-Timer Time-Out in Active Mode\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) dev_warn(&priv->spi->dev, "Wakeup reason unknown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) complete(&priv->ca8210_is_awake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) finish:;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static int ca8210_remove(struct spi_device *spi_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * ca8210_spi_transfer_complete() - Called when a single spi transfer has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * @context: Pointer to the cas_control object for the finished transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static void ca8210_spi_transfer_complete(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct cas_control *cas_ctl = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct ca8210_priv *priv = cas_ctl->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) bool duplex_rx = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) u8 retry_buffer[CA8210_SPI_BUF_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) cas_ctl->tx_in_buf[0] == SPI_NACK ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) (cas_ctl->tx_in_buf[0] == SPI_IDLE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) cas_ctl->tx_in_buf[1] == SPI_NACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* ca8210 is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) dev_info(&priv->spi->dev, "ca8210 was busy during attempted write\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (cas_ctl->tx_buf[0] == SPI_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) dev_warn(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) "IRQ servicing NACKd, dropping transfer\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) kfree(cas_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (priv->retries > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) dev_err(&priv->spi->dev, "too many retries!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) kfree(cas_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ca8210_remove(priv->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) memcpy(retry_buffer, cas_ctl->tx_buf, CA8210_SPI_BUF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) kfree(cas_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ca8210_spi_transfer(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) priv->spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) retry_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) CA8210_SPI_BUF_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) priv->retries++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dev_info(&priv->spi->dev, "retried spi write\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) } else if (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) cas_ctl->tx_in_buf[0] != SPI_IDLE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) cas_ctl->tx_in_buf[0] != SPI_NACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) duplex_rx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (duplex_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dev_dbg(&priv->spi->dev, "READ CMD DURING TX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) for (i = 0; i < cas_ctl->tx_in_buf[1] + 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dev_dbg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) "%#03x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) cas_ctl->tx_in_buf[i]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ca8210_rx_done(cas_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) complete(&priv->spi_transfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) kfree(cas_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) priv->retries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * ca8210_spi_transfer() - Initiate duplex spi transfer with ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * @spi: Pointer to spi device for transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * @buf: Octet array to send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * @len: length of the buffer being sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static int ca8210_spi_transfer(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) const u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) size_t len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) int i, status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct ca8210_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct cas_control *cas_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (!spi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) pr_crit("NULL spi device passed to %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) reinit_completion(&priv->spi_transfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) dev_dbg(&spi->dev, "%s called\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) cas_ctl = kmalloc(sizeof(*cas_ctl), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (!cas_ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) cas_ctl->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) memset(cas_ctl->tx_buf, SPI_IDLE, CA8210_SPI_BUF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) memset(cas_ctl->tx_in_buf, SPI_IDLE, CA8210_SPI_BUF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) memcpy(cas_ctl->tx_buf, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) dev_dbg(&spi->dev, "%#03x\n", cas_ctl->tx_buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) spi_message_init(&cas_ctl->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) cas_ctl->transfer.tx_nbits = 1; /* 1 MOSI line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) cas_ctl->transfer.rx_nbits = 1; /* 1 MISO line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) cas_ctl->transfer.speed_hz = 0; /* Use device setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) cas_ctl->transfer.bits_per_word = 0; /* Use device setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) cas_ctl->transfer.tx_buf = cas_ctl->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) cas_ctl->transfer.rx_buf = cas_ctl->tx_in_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) cas_ctl->transfer.delay.value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) cas_ctl->transfer.delay.unit = SPI_DELAY_UNIT_USECS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) cas_ctl->transfer.cs_change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) cas_ctl->transfer.len = sizeof(struct mac_message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) cas_ctl->msg.complete = ca8210_spi_transfer_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) cas_ctl->msg.context = cas_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) spi_message_add_tail(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) &cas_ctl->transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) &cas_ctl->msg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) status = spi_async(spi, &cas_ctl->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dev_crit(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) &spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) "status %d from spi_sync in write\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * ca8210_spi_exchange() - Exchange API/SAP commands with the radio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * @buf: Octet array of command being sent downstream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * @len: length of buf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * @response: buffer for storing synchronous response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * @device_ref: spi_device pointer for ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * Effectively calls ca8210_spi_transfer to write buf[] to the spi, then for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * synchronous commands waits for the corresponding response to be read from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * the spi before returning. The response is written to the response parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static int ca8210_spi_exchange(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) const u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) u8 *response,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) void *device_ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct spi_device *spi = device_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct ca8210_priv *priv = spi->dev.driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) long wait_remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if ((buf[0] & SPI_SYN) && response) { /* if sync wait for confirm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) reinit_completion(&priv->sync_exchange_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) priv->sync_command_response = response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) reinit_completion(&priv->spi_transfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) status = ca8210_spi_transfer(priv->spi, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) dev_warn(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) &spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) "spi write failed, returned %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (status == -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (((buf[0] & SPI_SYN) && response))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) complete(&priv->sync_exchange_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) wait_remaining = wait_for_completion_interruptible_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) &priv->spi_transfer_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) msecs_to_jiffies(1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (wait_remaining == -ERESTARTSYS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) status = -ERESTARTSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) } else if (wait_remaining == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) &spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) "SPI downstream transfer timed out!\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) status = -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) } while (status < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (!((buf[0] & SPI_SYN) && response))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) wait_remaining = wait_for_completion_interruptible_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) &priv->sync_exchange_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) msecs_to_jiffies(CA8210_SYNC_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (wait_remaining == -ERESTARTSYS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) status = -ERESTARTSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) } else if (wait_remaining == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) &spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) "Synchronous confirm timeout\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) status = -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) priv->sync_command_response = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * ca8210_interrupt_handler() - Called when an irq is received from the ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * @irq: Id of the irq being handled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * @dev_id: Pointer passed by the system, pointing to the ca8210's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * This function is called when the irq line from the ca8210 is asserted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * signifying that the ca8210 has a message to send upstream to us. Starts the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * asynchronous spi read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * Return: irq return code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static irqreturn_t ca8210_interrupt_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct ca8210_priv *priv = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) dev_dbg(&priv->spi->dev, "irq: Interrupt occurred\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) status = ca8210_spi_transfer(priv->spi, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (status && (status != -EBUSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) dev_warn(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) "spi read failed, returned %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) } while (status == -EBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static int (*cascoda_api_downstream)(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) const u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) u8 *response,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) void *device_ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ) = ca8210_spi_exchange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /* Cascoda API / 15.4 SAP Primitives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * tdme_setsfr_request_sync() - TDME_SETSFR_request/confirm according to API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * @sfr_page: SFR Page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * @sfr_address: SFR Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * @sfr_value: SFR Value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) * @device_ref: Nondescript pointer to target device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) * Return: 802.15.4 status code of TDME-SETSFR.confirm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static u8 tdme_setsfr_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) u8 sfr_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) u8 sfr_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) u8 sfr_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) void *device_ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) struct mac_message command, response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct spi_device *spi = device_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) command.command_id = SPI_TDME_SETSFR_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) command.length = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) command.pdata.tdme_set_sfr_req.sfr_page = sfr_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) command.pdata.tdme_set_sfr_req.sfr_address = sfr_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) command.pdata.tdme_set_sfr_req.sfr_value = sfr_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) response.command_id = SPI_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) ret = cascoda_api_downstream(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) &command.command_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) command.length + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) &response.command_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) device_ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) dev_crit(&spi->dev, "cascoda_api_downstream returned %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return MAC_SYSTEM_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (response.command_id != SPI_TDME_SETSFR_CONFIRM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) dev_crit(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) &spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) "sync response to SPI_TDME_SETSFR_REQUEST was not SPI_TDME_SETSFR_CONFIRM, it was %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) response.command_id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return MAC_SYSTEM_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return response.pdata.tdme_set_sfr_cnf.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * tdme_chipinit() - TDME Chip Register Default Initialisation Macro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * @device_ref: Nondescript pointer to target device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * Return: 802.15.4 status code of API calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) static u8 tdme_chipinit(void *device_ref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) u8 status = MAC_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) u8 sfr_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct spi_device *spi = device_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct preamble_cfg_sfr pre_cfg_value = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .timeout_symbols = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .acquisition_symbols = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .search_symbols = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /* LNA Gain Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) status = tdme_setsfr_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) 1, (sfr_address = CA8210_SFR_LNAGX40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) LNAGX40_DEFAULT_GAIN, device_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) status = tdme_setsfr_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) 1, (sfr_address = CA8210_SFR_LNAGX41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) LNAGX41_DEFAULT_GAIN, device_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) status = tdme_setsfr_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) 1, (sfr_address = CA8210_SFR_LNAGX42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) LNAGX42_DEFAULT_GAIN, device_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) status = tdme_setsfr_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) 1, (sfr_address = CA8210_SFR_LNAGX43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) LNAGX43_DEFAULT_GAIN, device_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) status = tdme_setsfr_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) 1, (sfr_address = CA8210_SFR_LNAGX44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) LNAGX44_DEFAULT_GAIN, device_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) status = tdme_setsfr_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) 1, (sfr_address = CA8210_SFR_LNAGX45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) LNAGX45_DEFAULT_GAIN, device_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) status = tdme_setsfr_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) 1, (sfr_address = CA8210_SFR_LNAGX46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) LNAGX46_DEFAULT_GAIN, device_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) status = tdme_setsfr_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) 1, (sfr_address = CA8210_SFR_LNAGX47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) LNAGX47_DEFAULT_GAIN, device_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) /* Preamble Timing Config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) status = tdme_setsfr_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) 1, (sfr_address = CA8210_SFR_PRECFG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) *((u8 *)&pre_cfg_value), device_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) /* Preamble Threshold High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) status = tdme_setsfr_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) 1, (sfr_address = CA8210_SFR_PTHRH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) PTHRH_DEFAULT_THRESHOLD, device_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /* Tx Output Power 8 dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) status = tdme_setsfr_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) 0, (sfr_address = CA8210_SFR_PACFGIB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) PACFGIB_DEFAULT_CURRENT, device_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) finish:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (status != MAC_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) &spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) "failed to set sfr at %#03x, status = %#03x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) sfr_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * tdme_channelinit() - TDME Channel Register Default Initialisation Macro (Tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * @channel: 802.15.4 channel to initialise chip for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * @device_ref: Nondescript pointer to target device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * Return: 802.15.4 status code of API calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) static u8 tdme_channelinit(u8 channel, void *device_ref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /* Transceiver front-end local oscillator tx two-point calibration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * value. Tuned for the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) u8 txcalval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (channel >= 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) txcalval = 0xA7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) else if (channel >= 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) txcalval = 0xA8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) else if (channel >= 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) txcalval = 0xA9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) else if (channel >= 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) txcalval = 0xAA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) else if (channel >= 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) txcalval = 0xAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) else if (channel >= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) txcalval = 0xAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) else if (channel >= 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) txcalval = 0xAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) else if (channel >= 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) txcalval = 0xAE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) txcalval = 0xAF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return tdme_setsfr_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) CA8210_SFR_LOTXCAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) txcalval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) device_ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) ); /* LO Tx Cal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * tdme_checkpibattribute() - Checks Attribute Values that are not checked in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) * @pib_attribute: Attribute Number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) * @pib_attribute_length: Attribute length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * @pib_attribute_value: Pointer to Attribute Value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) * @device_ref: Nondescript pointer to target device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * Return: 802.15.4 status code of checks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static u8 tdme_checkpibattribute(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) u8 pib_attribute,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) u8 pib_attribute_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) const void *pib_attribute_value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) u8 status = MAC_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) value = *((u8 *)pib_attribute_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) switch (pib_attribute) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /* PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) case PHY_TRANSMIT_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (value > 0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) status = MAC_INVALID_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) case PHY_CCA_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (value > 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) status = MAC_INVALID_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) /* MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) case MAC_BATT_LIFE_EXT_PERIODS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (value < 6 || value > 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) status = MAC_INVALID_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) case MAC_BEACON_PAYLOAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (pib_attribute_length > MAX_BEACON_PAYLOAD_LENGTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) status = MAC_INVALID_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) case MAC_BEACON_PAYLOAD_LENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (value > MAX_BEACON_PAYLOAD_LENGTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) status = MAC_INVALID_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) case MAC_BEACON_ORDER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (value > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) status = MAC_INVALID_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) case MAC_MAX_BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (value < 3 || value > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) status = MAC_INVALID_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) case MAC_MAX_CSMA_BACKOFFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (value > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) status = MAC_INVALID_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) case MAC_MAX_FRAME_RETRIES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (value > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) status = MAC_INVALID_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) case MAC_MIN_BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (value > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) status = MAC_INVALID_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) case MAC_RESPONSE_WAIT_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (value < 2 || value > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) status = MAC_INVALID_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) case MAC_SUPERFRAME_ORDER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (value > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) status = MAC_INVALID_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) /* boolean */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) case MAC_ASSOCIATED_PAN_COORD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) case MAC_ASSOCIATION_PERMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) case MAC_AUTO_REQUEST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) case MAC_BATT_LIFE_EXT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) case MAC_GTS_PERMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) case MAC_PROMISCUOUS_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) case MAC_RX_ON_WHEN_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) case MAC_SECURITY_ENABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (value > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) status = MAC_INVALID_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /* MAC SEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) case MAC_AUTO_REQUEST_SECURITY_LEVEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (value > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) status = MAC_INVALID_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) case MAC_AUTO_REQUEST_KEY_ID_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (value > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) status = MAC_INVALID_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * tdme_settxpower() - Sets the tx power for MLME_SET phyTransmitPower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * @txp: Transmit Power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) * @device_ref: Nondescript pointer to target device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) * Normalised to 802.15.4 Definition (6-bit, signed):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) * Bit 7-6: not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) * Bit 5-0: tx power (-32 - +31 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * Return: 802.15.4 status code of api calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static u8 tdme_settxpower(u8 txp, void *device_ref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) s8 txp_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) u8 txp_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) union pa_cfg_sfr pa_cfg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) /* extend from 6 to 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) txp_ext = 0x3F & txp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (txp_ext & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) txp_ext += 0xC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) txp_val = (s8)txp_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (CA8210_MAC_MPW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (txp_val > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /* 8 dBm: ptrim = 5, itrim = +3 => +4 dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) pa_cfg_val.bias_current_trim = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) pa_cfg_val.buffer_capacitor_trim = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) pa_cfg_val.boost = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /* 0 dBm: ptrim = 7, itrim = +3 => -6 dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) pa_cfg_val.bias_current_trim = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) pa_cfg_val.buffer_capacitor_trim = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) pa_cfg_val.boost = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) /* write PACFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) status = tdme_setsfr_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) CA8210_SFR_PACFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) pa_cfg_val.paib,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) device_ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /* Look-Up Table for Setting Current and Frequency Trim values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) * for desired Output Power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (txp_val > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) pa_cfg_val.paib = 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) } else if (txp_val == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) pa_cfg_val.paib = 0x32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) } else if (txp_val == 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) pa_cfg_val.paib = 0x22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) } else if (txp_val == 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) pa_cfg_val.paib = 0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) } else if (txp_val == 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) pa_cfg_val.paib = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) } else if (txp_val == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) pa_cfg_val.paib = 0x0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) } else if (txp_val == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) pa_cfg_val.paib = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) } else if (txp_val == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) pa_cfg_val.paib = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) } else if (txp_val == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) pa_cfg_val.paib = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) } else if (txp_val == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) pa_cfg_val.paib = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) } else { /* < 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) pa_cfg_val.paib = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) /* write PACFGIB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) status = tdme_setsfr_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) CA8210_SFR_PACFGIB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) pa_cfg_val.paib,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) device_ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) * mcps_data_request() - mcps_data_request (Send Data) according to API Spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * @src_addr_mode: Source Addressing Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) * @dst_address_mode: Destination Addressing Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) * @dst_pan_id: Destination PAN ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) * @dst_addr: Pointer to Destination Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) * @msdu_length: length of Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * @msdu: Pointer to Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) * @msdu_handle: Handle of Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) * @tx_options: Tx Options Bit Field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) * @security: Pointer to Security Structure or NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) * @device_ref: Nondescript pointer to target device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) * Return: 802.15.4 status code of action
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) static u8 mcps_data_request(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) u8 src_addr_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) u8 dst_address_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) u16 dst_pan_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) union macaddr *dst_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) u8 msdu_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) u8 *msdu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) u8 msdu_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) u8 tx_options,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) struct secspec *security,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) void *device_ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) struct secspec *psec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) struct mac_message command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) command.command_id = SPI_MCPS_DATA_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) command.pdata.data_req.src_addr_mode = src_addr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) command.pdata.data_req.dst.mode = dst_address_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (dst_address_mode != MAC_MODE_NO_ADDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) command.pdata.data_req.dst.pan_id[0] = LS_BYTE(dst_pan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) command.pdata.data_req.dst.pan_id[1] = MS_BYTE(dst_pan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (dst_address_mode == MAC_MODE_SHORT_ADDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) command.pdata.data_req.dst.address[0] = LS_BYTE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) dst_addr->short_address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) command.pdata.data_req.dst.address[1] = MS_BYTE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) dst_addr->short_address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) } else { /* MAC_MODE_LONG_ADDR*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) memcpy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) command.pdata.data_req.dst.address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) dst_addr->ieee_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) command.pdata.data_req.msdu_length = msdu_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) command.pdata.data_req.msdu_handle = msdu_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) command.pdata.data_req.tx_options = tx_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) memcpy(command.pdata.data_req.msdu, msdu, msdu_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) psec = (struct secspec *)(command.pdata.data_req.msdu + msdu_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) command.length = sizeof(struct mcps_data_request_pset) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) MAX_DATA_SIZE + msdu_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (!security || security->security_level == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) psec->security_level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) command.length += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) *psec = *security;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) command.length += sizeof(struct secspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (ca8210_spi_transfer(device_ref, &command.command_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) command.length + 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) return MAC_SYSTEM_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return MAC_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) * mlme_reset_request_sync() - MLME_RESET_request/confirm according to API Spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) * @set_default_pib: Set defaults in PIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) * @device_ref: Nondescript pointer to target device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) * Return: 802.15.4 status code of MLME-RESET.confirm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) static u8 mlme_reset_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) u8 set_default_pib,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) void *device_ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) struct mac_message command, response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) struct spi_device *spi = device_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) command.command_id = SPI_MLME_RESET_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) command.length = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) command.pdata.u8param = set_default_pib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) if (cascoda_api_downstream(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) &command.command_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) command.length + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) &response.command_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) device_ref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) dev_err(&spi->dev, "cascoda_api_downstream failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) return MAC_SYSTEM_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (response.command_id != SPI_MLME_RESET_CONFIRM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) return MAC_SYSTEM_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) status = response.pdata.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /* reset COORD Bit for Channel Filtering as Coordinator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) if (CA8210_MAC_WORKAROUNDS && set_default_pib && !status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) status = tdme_setsfr_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) CA8210_SFR_MACCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) device_ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) * mlme_set_request_sync() - MLME_SET_request/confirm according to API Spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) * @pib_attribute: Attribute Number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) * @pib_attribute_index: Index within Attribute if an Array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) * @pib_attribute_length: Attribute length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) * @pib_attribute_value: Pointer to Attribute Value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) * @device_ref: Nondescript pointer to target device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) * Return: 802.15.4 status code of MLME-SET.confirm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) static u8 mlme_set_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) u8 pib_attribute,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) u8 pib_attribute_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) u8 pib_attribute_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) const void *pib_attribute_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) void *device_ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) struct mac_message command, response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) /* pre-check the validity of pib_attribute values that are not checked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) * in MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) if (tdme_checkpibattribute(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) pib_attribute, pib_attribute_length, pib_attribute_value)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) return MAC_INVALID_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (pib_attribute == PHY_CURRENT_CHANNEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) status = tdme_channelinit(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) *((u8 *)pib_attribute_value),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) device_ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (pib_attribute == PHY_TRANSMIT_POWER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) return tdme_settxpower(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) *((u8 *)pib_attribute_value),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) device_ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) command.command_id = SPI_MLME_SET_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) command.length = sizeof(struct mlme_set_request_pset) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) MAX_ATTRIBUTE_SIZE + pib_attribute_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) command.pdata.set_req.pib_attribute = pib_attribute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) command.pdata.set_req.pib_attribute_index = pib_attribute_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) command.pdata.set_req.pib_attribute_length = pib_attribute_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) memcpy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) command.pdata.set_req.pib_attribute_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) pib_attribute_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) pib_attribute_length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (cascoda_api_downstream(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) &command.command_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) command.length + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) &response.command_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) device_ref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) return MAC_SYSTEM_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if (response.command_id != SPI_MLME_SET_CONFIRM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) return MAC_SYSTEM_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) return response.pdata.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) * hwme_set_request_sync() - HWME_SET_request/confirm according to API Spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) * @hw_attribute: Attribute Number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) * @hw_attribute_length: Attribute length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) * @hw_attribute_value: Pointer to Attribute Value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) * @device_ref: Nondescript pointer to target device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) * Return: 802.15.4 status code of HWME-SET.confirm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) static u8 hwme_set_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) u8 hw_attribute,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) u8 hw_attribute_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) u8 *hw_attribute_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) void *device_ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) struct mac_message command, response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) command.command_id = SPI_HWME_SET_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) command.length = 2 + hw_attribute_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) command.pdata.hwme_set_req.hw_attribute = hw_attribute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) command.pdata.hwme_set_req.hw_attribute_length = hw_attribute_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) memcpy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) command.pdata.hwme_set_req.hw_attribute_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) hw_attribute_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) hw_attribute_length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) if (cascoda_api_downstream(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) &command.command_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) command.length + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) &response.command_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) device_ref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) return MAC_SYSTEM_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (response.command_id != SPI_HWME_SET_CONFIRM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) return MAC_SYSTEM_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return response.pdata.hwme_set_cnf.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) * hwme_get_request_sync() - HWME_GET_request/confirm according to API Spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) * @hw_attribute: Attribute Number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) * @hw_attribute_length: Attribute length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) * @hw_attribute_value: Pointer to Attribute Value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) * @device_ref: Nondescript pointer to target device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) * Return: 802.15.4 status code of HWME-GET.confirm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) static u8 hwme_get_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) u8 hw_attribute,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) u8 *hw_attribute_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) u8 *hw_attribute_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) void *device_ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) struct mac_message command, response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) command.command_id = SPI_HWME_GET_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) command.length = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) command.pdata.hwme_get_req.hw_attribute = hw_attribute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (cascoda_api_downstream(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) &command.command_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) command.length + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) &response.command_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) device_ref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) return MAC_SYSTEM_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) if (response.command_id != SPI_HWME_GET_CONFIRM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) return MAC_SYSTEM_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (response.pdata.hwme_get_cnf.status == MAC_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) *hw_attribute_length =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) response.pdata.hwme_get_cnf.hw_attribute_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) memcpy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) hw_attribute_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) response.pdata.hwme_get_cnf.hw_attribute_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) *hw_attribute_length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) return response.pdata.hwme_get_cnf.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) /* Network driver operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) * ca8210_async_xmit_complete() - Called to announce that an asynchronous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) * transmission has finished
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) * @hw: ieee802154_hw of ca8210 that has finished exchange
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) * @msduhandle: Identifier of transmission that has completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) * @status: Returned 802.15.4 status code of the transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) static int ca8210_async_xmit_complete(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) struct ieee802154_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) u8 msduhandle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) u8 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) struct ca8210_priv *priv = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) if (priv->nextmsduhandle != msduhandle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) "Unexpected msdu_handle on data confirm, Expected %d, got %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) priv->nextmsduhandle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) msduhandle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) priv->async_tx_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) priv->nextmsduhandle++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) "Link transmission unsuccessful, status = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) if (status != MAC_TRANSACTION_OVERFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) dev_kfree_skb_any(priv->tx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) ieee802154_wake_queue(priv->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) ieee802154_xmit_complete(priv->hw, priv->tx_skb, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) * ca8210_skb_rx() - Contructs a properly framed socket buffer from a received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) * MCPS_DATA_indication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) * @hw: ieee802154_hw that MCPS_DATA_indication was received by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) * @len: length of MCPS_DATA_indication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) * @data_ind: Octet array of MCPS_DATA_indication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) * Called by the spi driver whenever a SAP command is received, this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) * will ascertain whether the command is of interest to the network driver and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) * take necessary action.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) static int ca8210_skb_rx(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) struct ieee802154_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) u8 *data_ind
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) struct ieee802154_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) int msdulen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) int hlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) u8 mpdulinkquality = data_ind[23];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) struct ca8210_priv *priv = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) /* Allocate mtu size buffer for every rx packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) skb = dev_alloc_skb(IEEE802154_MTU + sizeof(hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) skb_reserve(skb, sizeof(hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) msdulen = data_ind[22]; /* msdu_length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) if (msdulen > IEEE802154_MTU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) "received erroneously large msdu length!\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) return -EMSGSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) dev_dbg(&priv->spi->dev, "skb buffer length = %d\n", msdulen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) if (priv->promiscuous)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) goto copy_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) /* Populate hdr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) hdr.sec.level = data_ind[29 + msdulen];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) dev_dbg(&priv->spi->dev, "security level: %#03x\n", hdr.sec.level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (hdr.sec.level > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) hdr.sec.key_id_mode = data_ind[30 + msdulen];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) memcpy(&hdr.sec.extended_src, &data_ind[31 + msdulen], 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) hdr.sec.key_id = data_ind[39 + msdulen];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) hdr.source.mode = data_ind[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) dev_dbg(&priv->spi->dev, "srcAddrMode: %#03x\n", hdr.source.mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) hdr.source.pan_id = *(u16 *)&data_ind[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) dev_dbg(&priv->spi->dev, "srcPanId: %#06x\n", hdr.source.pan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) memcpy(&hdr.source.extended_addr, &data_ind[3], 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) hdr.dest.mode = data_ind[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) dev_dbg(&priv->spi->dev, "dstAddrMode: %#03x\n", hdr.dest.mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) hdr.dest.pan_id = *(u16 *)&data_ind[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) dev_dbg(&priv->spi->dev, "dstPanId: %#06x\n", hdr.dest.pan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) memcpy(&hdr.dest.extended_addr, &data_ind[14], 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) /* Fill in FC implicitly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) hdr.fc.type = 1; /* Data frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) if (hdr.sec.level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) hdr.fc.security_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) hdr.fc.security_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (data_ind[1] != data_ind[12] || data_ind[2] != data_ind[13])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) hdr.fc.intra_pan = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) hdr.fc.intra_pan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) hdr.fc.dest_addr_mode = hdr.dest.mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) hdr.fc.source_addr_mode = hdr.source.mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) /* Add hdr to front of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) hlen = ieee802154_hdr_push(skb, &hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) if (hlen < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) dev_crit(&priv->spi->dev, "failed to push mac hdr onto skb!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) return hlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) skb_reset_mac_header(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) skb->mac_len = hlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) copy_payload:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) /* Add <msdulen> bytes of space to the back of the buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) /* Copy msdu to skb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) skb_put_data(skb, &data_ind[29], msdulen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) ieee802154_rx_irqsafe(hw, skb, mpdulinkquality);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) * ca8210_net_rx() - Acts upon received SAP commands relevant to the network
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) * driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) * @hw: ieee802154_hw that command was received by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) * @command: Octet array of received command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) * @len: length of the received command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) * Called by the spi driver whenever a SAP command is received, this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) * will ascertain whether the command is of interest to the network driver and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) * take necessary action.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) static int ca8210_net_rx(struct ieee802154_hw *hw, u8 *command, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) struct ca8210_priv *priv = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) dev_dbg(&priv->spi->dev, "%s: CmdID = %d\n", __func__, command[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) if (command[0] == SPI_MCPS_DATA_INDICATION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) /* Received data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) if (command[26] == priv->last_dsn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) dev_dbg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) "DSN %d resend received, ignoring...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) command[26]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) priv->last_dsn = command[26];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) return ca8210_skb_rx(hw, len - 2, command + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) } else if (command[0] == SPI_MCPS_DATA_CONFIRM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) status = command[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) if (priv->async_tx_pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) return ca8210_async_xmit_complete(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) command[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) * ca8210_skb_tx() - Transmits a given socket buffer using the ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) * @skb: Socket buffer to transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) * @msduhandle: Data identifier to pass to the 802.15.4 MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) * @priv: Pointer to private data section of target ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) static int ca8210_skb_tx(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) u8 msduhandle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) struct ca8210_priv *priv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) struct ieee802154_hdr header = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) struct secspec secspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) unsigned int mac_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) dev_dbg(&priv->spi->dev, "%s called\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) /* Get addressing info from skb - ieee802154 layer creates a full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) * packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) mac_len = ieee802154_hdr_peek_addrs(skb, &header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) secspec.security_level = header.sec.level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) secspec.key_id_mode = header.sec.key_id_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) if (secspec.key_id_mode == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) memcpy(secspec.key_source, &header.sec.short_src, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) else if (secspec.key_id_mode == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) memcpy(secspec.key_source, &header.sec.extended_src, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) secspec.key_index = header.sec.key_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) /* Pass to Cascoda API */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) status = mcps_data_request(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) header.source.mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) header.dest.mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) header.dest.pan_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) (union macaddr *)&header.dest.extended_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) skb->len - mac_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) &skb->data[mac_len],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) msduhandle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) header.fc.ack_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) &secspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) priv->spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) return link_to_linux_err(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) * ca8210_start() - Starts the network driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) * @hw: ieee802154_hw of ca8210 being started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) static int ca8210_start(struct ieee802154_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) u8 rx_on_when_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) u8 lqi_threshold = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) struct ca8210_priv *priv = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) priv->last_dsn = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) /* Turn receiver on when idle for now just to test rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) rx_on_when_idle = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) status = mlme_set_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) MAC_RX_ON_WHEN_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) &rx_on_when_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) priv->spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) dev_crit(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) "Setting rx_on_when_idle failed, status = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) return link_to_linux_err(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) status = hwme_set_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) HWME_LQILIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) &lqi_threshold,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) priv->spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) dev_crit(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) "Setting lqilimit failed, status = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) return link_to_linux_err(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) * ca8210_stop() - Stops the network driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) * @hw: ieee802154_hw of ca8210 being stopped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) static void ca8210_stop(struct ieee802154_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) * ca8210_xmit_async() - Asynchronously transmits a given socket buffer using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) * the ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) * @hw: ieee802154_hw of ca8210 to transmit from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) * @skb: Socket buffer to transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) static int ca8210_xmit_async(struct ieee802154_hw *hw, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) struct ca8210_priv *priv = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) dev_dbg(&priv->spi->dev, "calling %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) priv->tx_skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) priv->async_tx_pending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) status = ca8210_skb_tx(skb, priv->nextmsduhandle, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) * ca8210_get_ed() - Returns the measured energy on the current channel at this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) * instant in time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) * @hw: ieee802154_hw of target ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) * @level: Measured Energy Detect level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) static int ca8210_get_ed(struct ieee802154_hw *hw, u8 *level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) u8 lenvar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) struct ca8210_priv *priv = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) return link_to_linux_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) hwme_get_request_sync(HWME_EDVALUE, &lenvar, level, priv->spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) * ca8210_set_channel() - Sets the current operating 802.15.4 channel of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) * ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) * @hw: ieee802154_hw of target ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) * @page: Channel page to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) * @channel: Channel number to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) static int ca8210_set_channel(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) struct ieee802154_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) u8 page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) u8 channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) struct ca8210_priv *priv = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) status = mlme_set_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) PHY_CURRENT_CHANNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) &channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) priv->spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) "error setting channel, MLME-SET.confirm status = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) return link_to_linux_err(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) * ca8210_set_hw_addr_filt() - Sets the address filtering parameters of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) * ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) * @hw: ieee802154_hw of target ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) * @filt: Filtering parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) * @changed: Bitmap representing which parameters to change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) * Effectively just sets the actual addressing information identifying this node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) * as all filtering is performed by the ca8210 as detailed in the IEEE 802.15.4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) * 2006 specification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) static int ca8210_set_hw_addr_filt(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) struct ieee802154_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) struct ieee802154_hw_addr_filt *filt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) unsigned long changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) u8 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) struct ca8210_priv *priv = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) if (changed & IEEE802154_AFILT_PANID_CHANGED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) status = mlme_set_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) MAC_PAN_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) &filt->pan_id, priv->spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) "error setting pan id, MLME-SET.confirm status = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) return link_to_linux_err(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) status = mlme_set_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) MAC_SHORT_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) &filt->short_addr, priv->spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) "error setting short address, MLME-SET.confirm status = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) return link_to_linux_err(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) status = mlme_set_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) NS_IEEE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) &filt->ieee_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) priv->spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) "error setting ieee address, MLME-SET.confirm status = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) return link_to_linux_err(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) /* TODO: Should use MLME_START to set coord bit? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) * ca8210_set_tx_power() - Sets the transmit power of the ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) * @hw: ieee802154_hw of target ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) * @mbm: Transmit power in mBm (dBm*100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) static int ca8210_set_tx_power(struct ieee802154_hw *hw, s32 mbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) struct ca8210_priv *priv = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) mbm /= 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) return link_to_linux_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) mlme_set_request_sync(PHY_TRANSMIT_POWER, 0, 1, &mbm, priv->spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) * ca8210_set_cca_mode() - Sets the clear channel assessment mode of the ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) * @hw: ieee802154_hw of target ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) * @cca: CCA mode to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) static int ca8210_set_cca_mode(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) struct ieee802154_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) const struct wpan_phy_cca *cca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) u8 cca_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) struct ca8210_priv *priv = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) cca_mode = cca->mode & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) if (cca_mode == 3 && cca->opt == NL802154_CCA_OPT_ENERGY_CARRIER_OR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) /* cca_mode 0 == CS OR ED, 3 == CS AND ED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) cca_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) status = mlme_set_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) PHY_CCA_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) &cca_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) priv->spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) "error setting cca mode, MLME-SET.confirm status = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) return link_to_linux_err(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) * ca8210_set_cca_ed_level() - Sets the CCA ED level of the ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) * @hw: ieee802154_hw of target ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) * @level: ED level to set (in mbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) * Sets the minimum threshold of measured energy above which the ca8210 will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) * back off and retry a transmission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) static int ca8210_set_cca_ed_level(struct ieee802154_hw *hw, s32 level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) u8 ed_threshold = (level / 100) * 2 + 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) struct ca8210_priv *priv = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) status = hwme_set_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) HWME_EDTHRESHOLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) &ed_threshold,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) priv->spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) "error setting ed threshold, HWME-SET.confirm status = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) return link_to_linux_err(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) * ca8210_set_csma_params() - Sets the CSMA parameters of the ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) * @hw: ieee802154_hw of target ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) * @min_be: Minimum backoff exponent when backing off a transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) * @max_be: Maximum backoff exponent when backing off a transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) * @retries: Number of times to retry after backing off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) static int ca8210_set_csma_params(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) struct ieee802154_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) u8 min_be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) u8 max_be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) u8 retries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) struct ca8210_priv *priv = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) status = mlme_set_request_sync(MAC_MIN_BE, 0, 1, &min_be, priv->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) "error setting min be, MLME-SET.confirm status = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) return link_to_linux_err(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) status = mlme_set_request_sync(MAC_MAX_BE, 0, 1, &max_be, priv->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) "error setting max be, MLME-SET.confirm status = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) return link_to_linux_err(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) status = mlme_set_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) MAC_MAX_CSMA_BACKOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) &retries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) priv->spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) "error setting max csma backoffs, MLME-SET.confirm status = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) return link_to_linux_err(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) * ca8210_set_frame_retries() - Sets the maximum frame retries of the ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) * @hw: ieee802154_hw of target ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) * @retries: Number of retries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) * Sets the number of times to retry a transmission if no acknowledgment was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) * was received from the other end when one was requested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) static int ca8210_set_frame_retries(struct ieee802154_hw *hw, s8 retries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) struct ca8210_priv *priv = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) status = mlme_set_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) MAC_MAX_FRAME_RETRIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) &retries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) priv->spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) "error setting frame retries, MLME-SET.confirm status = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) return link_to_linux_err(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) static int ca8210_set_promiscuous_mode(struct ieee802154_hw *hw, const bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) struct ca8210_priv *priv = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) status = mlme_set_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) MAC_PROMISCUOUS_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) (const void *)&on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) priv->spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) "error setting promiscuous mode, MLME-SET.confirm status = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) priv->promiscuous = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) return link_to_linux_err(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) static const struct ieee802154_ops ca8210_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) .start = ca8210_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .stop = ca8210_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .xmit_async = ca8210_xmit_async,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .ed = ca8210_get_ed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .set_channel = ca8210_set_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .set_hw_addr_filt = ca8210_set_hw_addr_filt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .set_txpower = ca8210_set_tx_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .set_cca_mode = ca8210_set_cca_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .set_cca_ed_level = ca8210_set_cca_ed_level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .set_csma_params = ca8210_set_csma_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) .set_frame_retries = ca8210_set_frame_retries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) .set_promiscuous_mode = ca8210_set_promiscuous_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) /* Test/EVBME Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) * ca8210_test_int_open() - Opens the test interface to the userspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) * @inodp: inode representation of file interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) * @filp: file interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) static int ca8210_test_int_open(struct inode *inodp, struct file *filp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) struct ca8210_priv *priv = inodp->i_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) filp->private_data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) * ca8210_test_check_upstream() - Checks a command received from the upstream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) * testing interface for required action
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) * @buf: Buffer containing command to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) * @device_ref: Nondescript pointer to target device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) static int ca8210_test_check_upstream(u8 *buf, void *device_ref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) u8 response[CA8210_SPI_BUF_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) if (buf[0] == SPI_MLME_SET_REQUEST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) ret = tdme_checkpibattribute(buf[2], buf[4], buf + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) response[0] = SPI_MLME_SET_CONFIRM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) response[1] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) response[2] = MAC_INVALID_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) response[3] = buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) response[4] = buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) if (cascoda_api_upstream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) cascoda_api_upstream(response, 5, device_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) if (buf[0] == SPI_MLME_ASSOCIATE_REQUEST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) return tdme_channelinit(buf[2], device_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) } else if (buf[0] == SPI_MLME_START_REQUEST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) return tdme_channelinit(buf[4], device_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) } else if (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) (buf[0] == SPI_MLME_SET_REQUEST) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) (buf[2] == PHY_CURRENT_CHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) return tdme_channelinit(buf[5], device_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) } else if (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) (buf[0] == SPI_TDME_SET_REQUEST) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) (buf[2] == TDME_CHANNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) return tdme_channelinit(buf[4], device_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) } else if (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) (CA8210_MAC_WORKAROUNDS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) (buf[0] == SPI_MLME_RESET_REQUEST) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) (buf[2] == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) /* reset COORD Bit for Channel Filtering as Coordinator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) return tdme_setsfr_request_sync(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) CA8210_SFR_MACCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) device_ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) } /* End of EVBMECheckSerialCommand() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) * ca8210_test_int_user_write() - Called by a process in userspace to send a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) * message to the ca8210 drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) * @filp: file interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) * @in_buf: Buffer containing message to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) * @len: length of message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) * @off: file offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) static ssize_t ca8210_test_int_user_write(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) struct file *filp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) const char __user *in_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) loff_t *off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) struct ca8210_priv *priv = filp->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) u8 command[CA8210_SPI_BUF_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) memset(command, SPI_IDLE, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) if (len > CA8210_SPI_BUF_SIZE || len < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) dev_warn(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) "userspace requested erroneous write length (%zu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) return -EBADE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) ret = copy_from_user(command, in_buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) "%d bytes could not be copied from userspace\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) if (len != command[1] + 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) "write len does not match packet length field\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) return -EBADE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) ret = ca8210_test_check_upstream(command, priv->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) ret = ca8210_spi_exchange(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) command[1] + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) priv->spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) /* effectively 0 bytes were written successfully */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) "spi exchange failed\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) if (command[0] & SPI_SYN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) priv->sync_down++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) * ca8210_test_int_user_read() - Called by a process in userspace to read a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) * message from the ca8210 drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) * @filp: file interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) * @buf: Buffer to write message to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) * @len: length of message to read (ignored)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) * @offp: file offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) * If the O_NONBLOCK flag was set when opening the file then this function will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) * not block, i.e. it will return if the fifo is empty. Otherwise the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) * will block, i.e. wait until new data arrives.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) * Return: number of bytes read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) static ssize_t ca8210_test_int_user_read(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) struct file *filp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) char __user *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) loff_t *offp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) int i, cmdlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) struct ca8210_priv *priv = filp->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) unsigned char *fifo_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) unsigned long bytes_not_copied;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) if (filp->f_flags & O_NONBLOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) /* Non-blocking mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) if (kfifo_is_empty(&priv->test.up_fifo))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) /* Blocking mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) wait_event_interruptible(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) priv->test.readq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) !kfifo_is_empty(&priv->test.up_fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) if (kfifo_out(&priv->test.up_fifo, &fifo_buffer, 4) != 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) "test_interface: Wrong number of elements popped from upstream fifo\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) cmdlen = fifo_buffer[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) bytes_not_copied = cmdlen + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) bytes_not_copied = copy_to_user(buf, fifo_buffer, bytes_not_copied);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) if (bytes_not_copied > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) &priv->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) "%lu bytes could not be copied to user space!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) bytes_not_copied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) dev_dbg(&priv->spi->dev, "test_interface: Cmd len = %d\n", cmdlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) dev_dbg(&priv->spi->dev, "test_interface: Read\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) for (i = 0; i < cmdlen + 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) dev_dbg(&priv->spi->dev, "%#03x\n", fifo_buffer[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) kfree(fifo_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) return cmdlen + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) * ca8210_test_int_ioctl() - Called by a process in userspace to enact an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) * arbitrary action
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) * @filp: file interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) * @ioctl_num: which action to enact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) * @ioctl_param: arbitrary parameter for the action
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) * Return: status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) static long ca8210_test_int_ioctl(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) struct file *filp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) unsigned int ioctl_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) unsigned long ioctl_param
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) struct ca8210_priv *priv = filp->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) switch (ioctl_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) case CA8210_IOCTL_HARD_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) ca8210_reset_send(priv->spi, ioctl_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) * ca8210_test_int_poll() - Called by a process in userspace to determine which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) * actions are currently possible for the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) * @filp: file interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) * @ptable: poll table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) * Return: set of poll return flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) static __poll_t ca8210_test_int_poll(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) struct file *filp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) struct poll_table_struct *ptable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) __poll_t return_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) struct ca8210_priv *priv = filp->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) poll_wait(filp, &priv->test.readq, ptable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) if (!kfifo_is_empty(&priv->test.up_fifo))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) return_flags |= (EPOLLIN | EPOLLRDNORM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) if (wait_event_interruptible(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) priv->test.readq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) !kfifo_is_empty(&priv->test.up_fifo))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) return EPOLLERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) return return_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) static const struct file_operations test_int_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) .read = ca8210_test_int_user_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) .write = ca8210_test_int_user_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) .open = ca8210_test_int_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) .release = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) .unlocked_ioctl = ca8210_test_int_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) .poll = ca8210_test_int_poll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) /* Init/Deinit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) * ca8210_get_platform_data() - Populate a ca8210_platform_data object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) * @spi_device: Pointer to ca8210 spi device object to get data for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) * @pdata: Pointer to ca8210_platform_data object to populate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) static int ca8210_get_platform_data(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) struct spi_device *spi_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) struct ca8210_platform_data *pdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) if (!spi_device->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) pdata->extclockenable = of_property_read_bool(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) spi_device->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) "extclock-enable"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) if (pdata->extclockenable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) ret = of_property_read_u32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) spi_device->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) "extclock-freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) &pdata->extclockfreq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) ret = of_property_read_u32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) spi_device->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) "extclock-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) &pdata->extclockgpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) * ca8210_config_extern_clk() - Configure the external clock provided by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) * ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) * @pdata: Pointer to ca8210_platform_data containing clock parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) * @spi: Pointer to target ca8210 spi device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) * @on: True to turn the clock on, false to turn off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) * The external clock is configured with a frequency and output pin taken from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) * the platform data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) static int ca8210_config_extern_clk(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) struct ca8210_platform_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) struct spi_device *spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) bool on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) u8 clkparam[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) dev_info(&spi->dev, "Switching external clock on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) switch (pdata->extclockfreq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) case SIXTEEN_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) clkparam[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) case EIGHT_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) clkparam[0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) case FOUR_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) clkparam[0] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) case TWO_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) clkparam[0] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) case ONE_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) clkparam[0] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) dev_crit(&spi->dev, "Invalid extclock-freq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) clkparam[1] = pdata->extclockgpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) dev_info(&spi->dev, "Switching external clock off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) clkparam[0] = 0; /* off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) clkparam[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) return link_to_linux_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) hwme_set_request_sync(HWME_SYSCLKOUT, 2, clkparam, spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) * ca8210_register_ext_clock() - Register ca8210's external clock with kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) * @spi: Pointer to target ca8210 spi device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) static int ca8210_register_ext_clock(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) struct device_node *np = spi->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) struct ca8210_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) struct ca8210_platform_data *pdata = spi->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) priv->clk = clk_register_fixed_rate(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) &spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) np->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) pdata->extclockfreq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) if (IS_ERR(priv->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) dev_crit(&spi->dev, "Failed to register external clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) ret = of_clk_add_provider(np, of_clk_src_simple_get, priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) clk_unregister(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) dev_crit(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) &spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) "Failed to register external clock as clock provider\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) dev_info(&spi->dev, "External clock set as clock provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) * ca8210_unregister_ext_clock() - Unregister ca8210's external clock with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) * kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) * @spi: Pointer to target ca8210 spi device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) static void ca8210_unregister_ext_clock(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) struct ca8210_priv *priv = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) if (!priv->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) of_clk_del_provider(spi->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) clk_unregister(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) dev_info(&spi->dev, "External clock unregistered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) * ca8210_reset_init() - Initialise the reset input to the ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) * @spi: Pointer to target ca8210 spi device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) static int ca8210_reset_init(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) struct ca8210_platform_data *pdata = spi->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) pdata->gpio_reset = of_get_named_gpio(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) spi->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) "reset-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) ret = gpio_direction_output(pdata->gpio_reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) dev_crit(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) &spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) "Reset GPIO %d did not set to output mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) pdata->gpio_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) * ca8210_interrupt_init() - Initialise the irq output from the ca8210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) * @spi: Pointer to target ca8210 spi device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) static int ca8210_interrupt_init(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) struct ca8210_platform_data *pdata = spi->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) pdata->gpio_irq = of_get_named_gpio(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) spi->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) "irq-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) pdata->irq_id = gpio_to_irq(pdata->gpio_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) if (pdata->irq_id < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) dev_crit(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) &spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) "Could not get irq for gpio pin %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) pdata->gpio_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) gpio_free(pdata->gpio_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) return pdata->irq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) ret = request_irq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) pdata->irq_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) ca8210_interrupt_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) IRQF_TRIGGER_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) "ca8210-irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) spi_get_drvdata(spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) dev_crit(&spi->dev, "request_irq %d failed\n", pdata->irq_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) gpio_unexport(pdata->gpio_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) gpio_free(pdata->gpio_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) * ca8210_dev_com_init() - Initialise the spi communication component
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) * @priv: Pointer to private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) static int ca8210_dev_com_init(struct ca8210_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) priv->mlme_workqueue = alloc_ordered_workqueue(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) "MLME work queue",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) WQ_UNBOUND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) if (!priv->mlme_workqueue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) dev_crit(&priv->spi->dev, "alloc of mlme_workqueue failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) priv->irq_workqueue = alloc_ordered_workqueue(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) "ca8210 irq worker",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) WQ_UNBOUND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) if (!priv->irq_workqueue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) dev_crit(&priv->spi->dev, "alloc of irq_workqueue failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) destroy_workqueue(priv->mlme_workqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) * ca8210_dev_com_clear() - Deinitialise the spi communication component
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) * @priv: Pointer to private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) static void ca8210_dev_com_clear(struct ca8210_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) flush_workqueue(priv->mlme_workqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) destroy_workqueue(priv->mlme_workqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) flush_workqueue(priv->irq_workqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) destroy_workqueue(priv->irq_workqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) #define CA8210_MAX_TX_POWERS (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) static const s32 ca8210_tx_powers[CA8210_MAX_TX_POWERS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) 800, 700, 600, 500, 400, 300, 200, 100, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) #define CA8210_MAX_ED_LEVELS (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) static const s32 ca8210_ed_levels[CA8210_MAX_ED_LEVELS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) -10300, -10250, -10200, -10150, -10100, -10050, -10000, -9950, -9900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) -9850, -9800, -9750, -9700, -9650, -9600, -9550, -9500, -9450, -9400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) -9350, -9300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) * ca8210_hw_setup() - Populate the ieee802154_hw phy attributes with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) * ca8210's defaults
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) * @ca8210_hw: Pointer to ieee802154_hw to populate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) static void ca8210_hw_setup(struct ieee802154_hw *ca8210_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) /* Support channels 11-26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) ca8210_hw->phy->supported.channels[0] = CA8210_VALID_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) ca8210_hw->phy->supported.tx_powers_size = CA8210_MAX_TX_POWERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) ca8210_hw->phy->supported.tx_powers = ca8210_tx_powers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) ca8210_hw->phy->supported.cca_ed_levels_size = CA8210_MAX_ED_LEVELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) ca8210_hw->phy->supported.cca_ed_levels = ca8210_ed_levels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) ca8210_hw->phy->current_channel = 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) ca8210_hw->phy->current_page = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) ca8210_hw->phy->transmit_power = 800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) ca8210_hw->phy->cca.mode = NL802154_CCA_ENERGY_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) ca8210_hw->phy->cca.opt = NL802154_CCA_OPT_ENERGY_CARRIER_AND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) ca8210_hw->phy->cca_ed_level = -9800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) ca8210_hw->phy->symbol_duration = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) ca8210_hw->phy->lifs_period = 40 * ca8210_hw->phy->symbol_duration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) ca8210_hw->phy->sifs_period = 12 * ca8210_hw->phy->symbol_duration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) ca8210_hw->flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) IEEE802154_HW_AFILT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) IEEE802154_HW_OMIT_CKSUM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) IEEE802154_HW_FRAME_RETRIES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) IEEE802154_HW_PROMISCUOUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) IEEE802154_HW_CSMA_PARAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) ca8210_hw->phy->flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) WPAN_PHY_FLAG_TXPOWER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) WPAN_PHY_FLAG_CCA_ED_LEVEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) WPAN_PHY_FLAG_CCA_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) * ca8210_test_interface_init() - Initialise the test file interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) * @priv: Pointer to private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) * Provided as an alternative to the standard linux network interface, the test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) * interface exposes a file in the filesystem (ca8210_test) that allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) * 802.15.4 SAP Commands and Cascoda EVBME commands to be sent directly to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) * the stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) static int ca8210_test_interface_init(struct ca8210_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) struct ca8210_test *test = &priv->test;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) char node_name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) snprintf(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) node_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) sizeof(node_name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) "ca8210@%d_%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) priv->spi->master->bus_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) priv->spi->chip_select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) test->ca8210_dfs_spi_int = debugfs_create_file(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) node_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) 0600, /* S_IRUSR | S_IWUSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) &test_int_fops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) debugfs_create_symlink("ca8210", NULL, node_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) init_waitqueue_head(&test->readq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) return kfifo_alloc(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) &test->up_fifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) CA8210_TEST_INT_FIFO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) GFP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) * ca8210_test_interface_clear() - Deinitialise the test file interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) * @priv: Pointer to private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) static void ca8210_test_interface_clear(struct ca8210_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) struct ca8210_test *test = &priv->test;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) debugfs_remove(test->ca8210_dfs_spi_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) kfifo_free(&test->up_fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) dev_info(&priv->spi->dev, "Test interface removed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) * ca8210_remove() - Shut down a ca8210 upon being disconnected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) * @priv: Pointer to private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) static int ca8210_remove(struct spi_device *spi_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) struct ca8210_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) struct ca8210_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) dev_info(&spi_device->dev, "Removing ca8210\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) pdata = spi_device->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) if (pdata->extclockenable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) ca8210_unregister_ext_clock(spi_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) ca8210_config_extern_clk(pdata, spi_device, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) free_irq(pdata->irq_id, spi_device->dev.driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) kfree(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) spi_device->dev.platform_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) /* get spi_device private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) priv = spi_get_drvdata(spi_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) if (priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) dev_info(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) &spi_device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) "sync_down = %d, sync_up = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) priv->sync_down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) priv->sync_up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) ca8210_dev_com_clear(spi_device->dev.driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) if (priv->hw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) if (priv->hw_registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) ieee802154_unregister_hw(priv->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) ieee802154_free_hw(priv->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) priv->hw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) dev_info(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) &spi_device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) "Unregistered & freed ieee802154_hw.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) if (IS_ENABLED(CONFIG_IEEE802154_CA8210_DEBUGFS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) ca8210_test_interface_clear(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) * ca8210_probe() - Set up a connected ca8210 upon being detected by the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) * @priv: Pointer to private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) * Return: 0 or linux error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) static int ca8210_probe(struct spi_device *spi_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) struct ca8210_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) struct ieee802154_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) struct ca8210_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) dev_info(&spi_device->dev, "Inserting ca8210\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) /* allocate ieee802154_hw and private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) hw = ieee802154_alloc_hw(sizeof(struct ca8210_priv), &ca8210_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) if (!hw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) dev_crit(&spi_device->dev, "ieee802154_alloc_hw failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) priv = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) priv->hw = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) priv->spi = spi_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) hw->parent = &spi_device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) priv->async_tx_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) priv->hw_registered = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) priv->sync_up = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) priv->sync_down = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) priv->promiscuous = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) priv->retries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) init_completion(&priv->ca8210_is_awake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) init_completion(&priv->spi_transfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) init_completion(&priv->sync_exchange_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) spi_set_drvdata(priv->spi, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) if (IS_ENABLED(CONFIG_IEEE802154_CA8210_DEBUGFS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) cascoda_api_upstream = ca8210_test_int_driver_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) ca8210_test_interface_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) cascoda_api_upstream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) ca8210_hw_setup(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) ieee802154_random_extended_addr(&hw->phy->perm_extended_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) pdata = kmalloc(sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) priv->spi->dev.platform_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) ret = ca8210_get_platform_data(priv->spi, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) dev_crit(&spi_device->dev, "ca8210_get_platform_data failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) ret = ca8210_dev_com_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) dev_crit(&spi_device->dev, "ca8210_dev_com_init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) ret = ca8210_reset_init(priv->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) dev_crit(&spi_device->dev, "ca8210_reset_init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) ret = ca8210_interrupt_init(priv->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) dev_crit(&spi_device->dev, "ca8210_interrupt_init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) ca8210_reset_send(priv->spi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) ret = tdme_chipinit(priv->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) dev_crit(&spi_device->dev, "tdme_chipinit failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) if (pdata->extclockenable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) ret = ca8210_config_extern_clk(pdata, priv->spi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) dev_crit(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) &spi_device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) "ca8210_config_extern_clk failed\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) ret = ca8210_register_ext_clock(priv->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) dev_crit(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) &spi_device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) "ca8210_register_ext_clock failed\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) ret = ieee802154_register_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) dev_crit(&spi_device->dev, "ieee802154_register_hw failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) priv->hw_registered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) msleep(100); /* wait for pending spi transfers to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) ca8210_remove(spi_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) return link_to_linux_err(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) static const struct of_device_id ca8210_of_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) {.compatible = "cascoda,ca8210", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) MODULE_DEVICE_TABLE(of, ca8210_of_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) static struct spi_driver ca8210_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) .of_match_table = of_match_ptr(ca8210_of_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) .probe = ca8210_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) .remove = ca8210_remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) module_spi_driver(ca8210_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) MODULE_AUTHOR("Harry Morris <h.morris@cascoda.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) MODULE_DESCRIPTION("CA-8210 SoftMAC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) MODULE_LICENSE("Dual BSD/GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) MODULE_VERSION("1.0");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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