Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * AT86RF230/RF231 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2009-2012 Siemens AG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Written by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #ifndef _AT86RF230_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define _AT86RF230_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define RG_TRX_STATUS	(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define SR_TRX_STATUS		0x01, 0x1f, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define SR_RESERVED_01_3	0x01, 0x20, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SR_CCA_STATUS		0x01, 0x40, 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SR_CCA_DONE		0x01, 0x80, 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define RG_TRX_STATE	(0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SR_TRX_CMD		0x02, 0x1f, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SR_TRAC_STATUS		0x02, 0xe0, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define RG_TRX_CTRL_0	(0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SR_CLKM_CTRL		0x03, 0x07, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SR_CLKM_SHA_SEL		0x03, 0x08, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SR_PAD_IO_CLKM		0x03, 0x30, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SR_PAD_IO		0x03, 0xc0, 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define RG_TRX_CTRL_1	(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SR_IRQ_POLARITY		0x04, 0x01, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SR_IRQ_MASK_MODE	0x04, 0x02, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SR_SPI_CMD_MODE		0x04, 0x0c, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SR_RX_BL_CTRL		0x04, 0x10, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SR_TX_AUTO_CRC_ON	0x04, 0x20, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SR_IRQ_2_EXT_EN		0x04, 0x40, 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SR_PA_EXT_EN		0x04, 0x80, 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define RG_PHY_TX_PWR	(0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SR_TX_PWR_23X		0x05, 0x0f, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SR_PA_LT_230		0x05, 0x30, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SR_PA_BUF_LT_230	0x05, 0xc0, 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SR_TX_PWR_212		0x05, 0x1f, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SR_GC_PA_212		0x05, 0x60, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SR_PA_BOOST_LT_212	0x05, 0x80, 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define RG_PHY_RSSI	(0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SR_RSSI			0x06, 0x1f, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SR_RND_VALUE		0x06, 0x60, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SR_RX_CRC_VALID		0x06, 0x80, 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define RG_PHY_ED_LEVEL	(0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SR_ED_LEVEL		0x07, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define RG_PHY_CC_CCA	(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SR_CHANNEL		0x08, 0x1f, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SR_CCA_MODE		0x08, 0x60, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SR_CCA_REQUEST		0x08, 0x80, 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define RG_CCA_THRES	(0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SR_CCA_ED_THRES		0x09, 0x0f, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SR_RESERVED_09_1	0x09, 0xf0, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define RG_RX_CTRL	(0x0a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SR_PDT_THRES		0x0a, 0x0f, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SR_RESERVED_0a_1	0x0a, 0xf0, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define RG_SFD_VALUE	(0x0b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SR_SFD_VALUE		0x0b, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define RG_TRX_CTRL_2	(0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SR_OQPSK_DATA_RATE	0x0c, 0x03, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SR_SUB_MODE		0x0c, 0x04, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SR_BPSK_QPSK		0x0c, 0x08, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define SR_OQPSK_SUB1_RC_EN	0x0c, 0x10, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define SR_RESERVED_0c_5	0x0c, 0x60, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define SR_RX_SAFE_MODE		0x0c, 0x80, 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define RG_ANT_DIV	(0x0d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define SR_ANT_CTRL		0x0d, 0x03, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define SR_ANT_EXT_SW_EN	0x0d, 0x04, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define SR_ANT_DIV_EN		0x0d, 0x08, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define SR_RESERVED_0d_2	0x0d, 0x70, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define SR_ANT_SEL		0x0d, 0x80, 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define RG_IRQ_MASK	(0x0e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define SR_IRQ_MASK		0x0e, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define RG_IRQ_STATUS	(0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define SR_IRQ_0_PLL_LOCK	0x0f, 0x01, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define SR_IRQ_1_PLL_UNLOCK	0x0f, 0x02, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define SR_IRQ_2_RX_START	0x0f, 0x04, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define SR_IRQ_3_TRX_END	0x0f, 0x08, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define SR_IRQ_4_CCA_ED_DONE	0x0f, 0x10, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define SR_IRQ_5_AMI		0x0f, 0x20, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define SR_IRQ_6_TRX_UR		0x0f, 0x40, 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define SR_IRQ_7_BAT_LOW	0x0f, 0x80, 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define RG_VREG_CTRL	(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define SR_RESERVED_10_6	0x10, 0x03, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define SR_DVDD_OK		0x10, 0x04, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define SR_DVREG_EXT		0x10, 0x08, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define SR_RESERVED_10_3	0x10, 0x30, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define SR_AVDD_OK		0x10, 0x40, 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define SR_AVREG_EXT		0x10, 0x80, 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define RG_BATMON	(0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define SR_BATMON_VTH		0x11, 0x0f, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define SR_BATMON_HR		0x11, 0x10, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define SR_BATMON_OK		0x11, 0x20, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define SR_RESERVED_11_1	0x11, 0xc0, 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define RG_XOSC_CTRL	(0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define SR_XTAL_TRIM		0x12, 0x0f, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define SR_XTAL_MODE		0x12, 0xf0, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RG_RX_SYN	(0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SR_RX_PDT_LEVEL		0x15, 0x0f, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SR_RESERVED_15_2	0x15, 0x70, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SR_RX_PDT_DIS		0x15, 0x80, 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RG_XAH_CTRL_1	(0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SR_RESERVED_17_8	0x17, 0x01, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SR_AACK_PROM_MODE	0x17, 0x02, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SR_AACK_ACK_TIME	0x17, 0x04, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SR_RESERVED_17_5	0x17, 0x08, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SR_AACK_UPLD_RES_FT	0x17, 0x10, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SR_AACK_FLTR_RES_FT	0x17, 0x20, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SR_CSMA_LBT_MODE	0x17, 0x40, 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SR_RESERVED_17_1	0x17, 0x80, 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RG_FTN_CTRL	(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SR_RESERVED_18_2	0x18, 0x7f, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SR_FTN_START		0x18, 0x80, 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RG_PLL_CF	(0x1a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SR_RESERVED_1a_2	0x1a, 0x7f, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SR_PLL_CF_START		0x1a, 0x80, 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RG_PLL_DCU	(0x1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SR_RESERVED_1b_3	0x1b, 0x3f, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SR_RESERVED_1b_2	0x1b, 0x40, 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SR_PLL_DCU_START	0x1b, 0x80, 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RG_PART_NUM	(0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SR_PART_NUM		0x1c, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RG_VERSION_NUM	(0x1d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SR_VERSION_NUM		0x1d, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RG_MAN_ID_0	(0x1e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SR_MAN_ID_0		0x1e, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RG_MAN_ID_1	(0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SR_MAN_ID_1		0x1f, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RG_SHORT_ADDR_0	(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SR_SHORT_ADDR_0		0x20, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RG_SHORT_ADDR_1	(0x21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SR_SHORT_ADDR_1		0x21, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RG_PAN_ID_0	(0x22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SR_PAN_ID_0		0x22, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RG_PAN_ID_1	(0x23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SR_PAN_ID_1		0x23, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define RG_IEEE_ADDR_0	(0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SR_IEEE_ADDR_0		0x24, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RG_IEEE_ADDR_1	(0x25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SR_IEEE_ADDR_1		0x25, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RG_IEEE_ADDR_2	(0x26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SR_IEEE_ADDR_2		0x26, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RG_IEEE_ADDR_3	(0x27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SR_IEEE_ADDR_3		0x27, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RG_IEEE_ADDR_4	(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SR_IEEE_ADDR_4		0x28, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RG_IEEE_ADDR_5	(0x29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SR_IEEE_ADDR_5		0x29, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RG_IEEE_ADDR_6	(0x2a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SR_IEEE_ADDR_6		0x2a, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define RG_IEEE_ADDR_7	(0x2b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SR_IEEE_ADDR_7		0x2b, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define RG_XAH_CTRL_0	(0x2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SR_SLOTTED_OPERATION	0x2c, 0x01, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SR_MAX_CSMA_RETRIES	0x2c, 0x0e, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SR_MAX_FRAME_RETRIES	0x2c, 0xf0, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define RG_CSMA_SEED_0	(0x2d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SR_CSMA_SEED_0		0x2d, 0xff, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define RG_CSMA_SEED_1	(0x2e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SR_CSMA_SEED_1		0x2e, 0x07, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SR_AACK_I_AM_COORD	0x2e, 0x08, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SR_AACK_DIS_ACK		0x2e, 0x10, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SR_AACK_SET_PD		0x2e, 0x20, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SR_AACK_FVN_MODE	0x2e, 0xc0, 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define RG_CSMA_BE	(0x2f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SR_MIN_BE		0x2f, 0x0f, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SR_MAX_BE		0x2f, 0xf0, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CMD_REG		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CMD_REG_MASK	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CMD_WRITE	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CMD_FB		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IRQ_BAT_LOW	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IRQ_TRX_UR	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IRQ_AMI		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IRQ_CCA_ED	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IRQ_TRX_END	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IRQ_RX_START	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IRQ_PLL_UNL	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IRQ_PLL_LOCK	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IRQ_ACTIVE_HIGH	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IRQ_ACTIVE_LOW	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define STATE_P_ON		0x00	/* BUSY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define STATE_BUSY_RX		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define STATE_BUSY_TX		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define STATE_FORCE_TRX_OFF	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define STATE_FORCE_TX_ON	0x04	/* IDLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* 0x05 */				/* INVALID_PARAMETER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define STATE_RX_ON		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* 0x07 */				/* SUCCESS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define STATE_TRX_OFF		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define STATE_TX_ON		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* 0x0a - 0x0e */			/* 0x0a - UNSUPPORTED_ATTRIBUTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define STATE_SLEEP		0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define STATE_PREP_DEEP_SLEEP	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define STATE_BUSY_RX_AACK	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define STATE_BUSY_TX_ARET	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define STATE_RX_AACK_ON	0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define STATE_TX_ARET_ON	0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define STATE_RX_ON_NOCLK	0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define STATE_RX_AACK_ON_NOCLK	0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define STATE_BUSY_RX_AACK_NOCLK 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define STATE_TRANSITION_IN_PROGRESS 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TRX_STATE_MASK		(0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TRAC_MASK(x)		((x & 0xe0) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TRAC_SUCCESS			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TRAC_SUCCESS_DATA_PENDING	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TRAC_SUCCESS_WAIT_FOR_ACK	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TRAC_CHANNEL_ACCESS_FAILURE	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TRAC_NO_ACK			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TRAC_INVALID			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #endif /* !_AT86RF230_H */