^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AT86RF230/RF231 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009-2012 Siemens AG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Written by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Alexander Aring <aar@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/hrtimer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spi/at86rf230.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/ieee802154.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <net/mac802154.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <net/cfg802154.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "at86rf230.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct at86rf230_local;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* at86rf2xx chip depend data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * All timings are in us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct at86rf2xx_chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u16 t_sleep_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u16 t_channel_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u16 t_reset_to_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u16 t_off_to_aack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u16 t_off_to_tx_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u16 t_off_to_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u16 t_sleep_to_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u16 t_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u16 t_p_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int rssi_base_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int (*set_channel)(struct at86rf230_local *, u8, u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int (*set_txpower)(struct at86rf230_local *, s32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AT86RF2XX_MAX_BUF (127 + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* tx retries to access the TX_ON state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * if it's above then force change will be started.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * We assume the max_frame_retries (7) value of 802.15.4 here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AT86RF2XX_MAX_TX_RETRIES 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* We use the recommended 5 minutes timeout to recalibrate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AT86RF2XX_CAL_LOOP_TIMEOUT (5 * 60 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct at86rf230_state_change {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct at86rf230_local *lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct hrtimer timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct spi_transfer trx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 buf[AT86RF2XX_MAX_BUF];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void (*complete)(void *context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 from_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u8 to_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) bool free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct at86rf230_trac {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u64 success;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u64 success_data_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u64 success_wait_for_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u64 channel_access_failure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u64 no_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u64 invalid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct at86rf230_local {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct ieee802154_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct at86rf2xx_chip_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int slp_tr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) bool sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct completion state_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct at86rf230_state_change state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned long cal_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) bool is_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) bool is_tx_from_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) bool was_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 tx_retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct sk_buff *tx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct at86rf230_state_change tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct at86rf230_trac trac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AT86RF2XX_NUMREGS 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) at86rf230_async_state_change(struct at86rf230_local *lp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct at86rf230_state_change *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) const u8 state, void (*complete)(void *context));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) at86rf230_sleep(struct at86rf230_local *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (gpio_is_valid(lp->slp_tr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) gpio_set_value(lp->slp_tr, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) usleep_range(lp->data->t_off_to_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) lp->data->t_off_to_sleep + 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) lp->sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) at86rf230_awake(struct at86rf230_local *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (gpio_is_valid(lp->slp_tr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) gpio_set_value(lp->slp_tr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) usleep_range(lp->data->t_sleep_to_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) lp->data->t_sleep_to_off + 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) lp->sleep = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) __at86rf230_write(struct at86rf230_local *lp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int addr, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) bool sleep = lp->sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* awake for register setting if sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) at86rf230_awake(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret = regmap_write(lp->regmap, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* sleep again if was sleeping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) at86rf230_sleep(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) __at86rf230_read(struct at86rf230_local *lp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int addr, unsigned int *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bool sleep = lp->sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* awake for register setting if sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) at86rf230_awake(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = regmap_read(lp->regmap, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* sleep again if was sleeping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) at86rf230_sleep(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) at86rf230_read_subreg(struct at86rf230_local *lp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned int addr, unsigned int mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned int shift, unsigned int *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) rc = __at86rf230_read(lp, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) *data = (*data & mask) >> shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) at86rf230_write_subreg(struct at86rf230_local *lp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int addr, unsigned int mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int shift, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) bool sleep = lp->sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* awake for register setting if sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) at86rf230_awake(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ret = regmap_update_bits(lp->regmap, addr, mask, data << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* sleep again if was sleeping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) at86rf230_sleep(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) at86rf230_slp_tr_rising_edge(struct at86rf230_local *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) gpio_set_value(lp->slp_tr, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) gpio_set_value(lp->slp_tr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) at86rf230_reg_writeable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case RG_TRX_STATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) case RG_TRX_CTRL_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) case RG_TRX_CTRL_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case RG_PHY_TX_PWR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) case RG_PHY_ED_LEVEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case RG_PHY_CC_CCA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) case RG_CCA_THRES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case RG_RX_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case RG_SFD_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case RG_TRX_CTRL_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) case RG_ANT_DIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) case RG_IRQ_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) case RG_VREG_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case RG_BATMON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case RG_XOSC_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case RG_RX_SYN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case RG_XAH_CTRL_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case RG_FTN_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case RG_PLL_CF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case RG_PLL_DCU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case RG_SHORT_ADDR_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case RG_SHORT_ADDR_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case RG_PAN_ID_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case RG_PAN_ID_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case RG_IEEE_ADDR_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case RG_IEEE_ADDR_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case RG_IEEE_ADDR_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case RG_IEEE_ADDR_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case RG_IEEE_ADDR_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case RG_IEEE_ADDR_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case RG_IEEE_ADDR_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case RG_IEEE_ADDR_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case RG_XAH_CTRL_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) case RG_CSMA_SEED_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case RG_CSMA_SEED_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case RG_CSMA_BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) at86rf230_reg_readable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) bool rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* all writeable are also readable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) rc = at86rf230_reg_writeable(dev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* readonly regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case RG_TRX_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case RG_PHY_RSSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) case RG_IRQ_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case RG_PART_NUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case RG_VERSION_NUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) case RG_MAN_ID_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) case RG_MAN_ID_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) at86rf230_reg_volatile(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* can be changed during runtime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) case RG_TRX_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case RG_TRX_STATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case RG_PHY_RSSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case RG_PHY_ED_LEVEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case RG_IRQ_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case RG_VREG_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case RG_PLL_CF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case RG_PLL_DCU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) at86rf230_reg_precious(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* don't clear irq line on read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case RG_IRQ_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const struct regmap_config at86rf230_regmap_spi_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .write_flag_mask = CMD_REG | CMD_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .read_flag_mask = CMD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .max_register = AT86RF2XX_NUMREGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .writeable_reg = at86rf230_reg_writeable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .readable_reg = at86rf230_reg_readable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .volatile_reg = at86rf230_reg_volatile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .precious_reg = at86rf230_reg_precious,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) at86rf230_async_error_recover_complete(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct at86rf230_state_change *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct at86rf230_local *lp = ctx->lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ctx->free)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) kfree(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (lp->was_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) lp->was_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_kfree_skb_any(lp->tx_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ieee802154_wake_queue(lp->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) at86rf230_async_error_recover(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct at86rf230_state_change *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct at86rf230_local *lp = ctx->lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (lp->is_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) lp->was_tx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) lp->is_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) at86rf230_async_state_change(lp, ctx, STATE_RX_AACK_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) at86rf230_async_error_recover_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) at86rf230_async_error(struct at86rf230_local *lp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct at86rf230_state_change *ctx, int rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dev_err(&lp->spi->dev, "spi_async error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) at86rf230_async_state_change(lp, ctx, STATE_FORCE_TRX_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) at86rf230_async_error_recover);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Generic function to get some register value in async mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) at86rf230_async_read_reg(struct at86rf230_local *lp, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct at86rf230_state_change *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) void (*complete)(void *context))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u8 *tx_buf = ctx->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) tx_buf[0] = (reg & CMD_REG_MASK) | CMD_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ctx->msg.complete = complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) rc = spi_async(lp->spi, &ctx->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) at86rf230_async_error(lp, ctx, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) at86rf230_async_write_reg(struct at86rf230_local *lp, u8 reg, u8 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct at86rf230_state_change *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) void (*complete)(void *context))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ctx->buf[0] = (reg & CMD_REG_MASK) | CMD_REG | CMD_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ctx->buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ctx->msg.complete = complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) rc = spi_async(lp->spi, &ctx->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) at86rf230_async_error(lp, ctx, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) at86rf230_async_state_assert(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct at86rf230_state_change *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct at86rf230_local *lp = ctx->lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) const u8 *buf = ctx->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) const u8 trx_state = buf[1] & TRX_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Assert state change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (trx_state != ctx->to_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Special handling if transceiver state is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * STATE_BUSY_RX_AACK and a SHR was detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (trx_state == STATE_BUSY_RX_AACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Undocumented race condition. If we send a state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * change to STATE_RX_AACK_ON the transceiver could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * change his state automatically to STATE_BUSY_RX_AACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * if a SHR was detected. This is not an error, but we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * can't assert this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (ctx->to_state == STATE_RX_AACK_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* If we change to STATE_TX_ON without forcing and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * transceiver state is STATE_BUSY_RX_AACK, we wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * 'tFrame + tPAck' receiving time. In this time the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * PDU should be received. If the transceiver is still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * in STATE_BUSY_RX_AACK, we run a force state change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * to STATE_TX_ON. This is a timeout handling, if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * transceiver stucks in STATE_BUSY_RX_AACK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * Additional we do several retries to try to get into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * TX_ON state without forcing. If the retries are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * higher or equal than AT86RF2XX_MAX_TX_RETRIES we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * will do a force change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (ctx->to_state == STATE_TX_ON ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ctx->to_state == STATE_TRX_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u8 state = ctx->to_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (lp->tx_retry >= AT86RF2XX_MAX_TX_RETRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) state = STATE_FORCE_TRX_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) lp->tx_retry++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) at86rf230_async_state_change(lp, ctx, state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ctx->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_warn(&lp->spi->dev, "unexcept state change from 0x%02x to 0x%02x. Actual state: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ctx->from_state, ctx->to_state, trx_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (ctx->complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ctx->complete(context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static enum hrtimer_restart at86rf230_async_state_timer(struct hrtimer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct at86rf230_state_change *ctx =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) container_of(timer, struct at86rf230_state_change, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct at86rf230_local *lp = ctx->lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) at86rf230_async_state_assert);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return HRTIMER_NORESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Do state change timing delay. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) at86rf230_async_state_delay(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct at86rf230_state_change *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct at86rf230_local *lp = ctx->lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct at86rf2xx_chip_data *c = lp->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) bool force = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ktime_t tim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* The force state changes are will show as normal states in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * state status subregister. We change the to_state to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * corresponding one and remember if it was a force change, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * differs if we do a state change from STATE_BUSY_RX_AACK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) switch (ctx->to_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case STATE_FORCE_TX_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ctx->to_state = STATE_TX_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) force = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case STATE_FORCE_TRX_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ctx->to_state = STATE_TRX_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) force = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) switch (ctx->from_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) case STATE_TRX_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) switch (ctx->to_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) case STATE_RX_AACK_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) tim = c->t_off_to_aack * NSEC_PER_USEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* state change from TRX_OFF to RX_AACK_ON to do a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * calibration, we need to reset the timeout for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * next one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) lp->cal_timeout = jiffies + AT86RF2XX_CAL_LOOP_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) goto change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) case STATE_TX_ARET_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) case STATE_TX_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) tim = c->t_off_to_tx_on * NSEC_PER_USEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* state change from TRX_OFF to TX_ON or ARET_ON to do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * a calibration, we need to reset the timeout for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * next one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) lp->cal_timeout = jiffies + AT86RF2XX_CAL_LOOP_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) goto change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) case STATE_BUSY_RX_AACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) switch (ctx->to_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) case STATE_TRX_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) case STATE_TX_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Wait for worst case receiving time if we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * didn't make a force change from BUSY_RX_AACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * to TX_ON or TRX_OFF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (!force) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) tim = (c->t_frame + c->t_p_ack) * NSEC_PER_USEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) goto change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* Default value, means RESET state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) case STATE_P_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) switch (ctx->to_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) case STATE_TRX_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) tim = c->t_reset_to_off * NSEC_PER_USEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) goto change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* Default delay is 1us in the most cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) at86rf230_async_state_timer(&ctx->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) change:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) hrtimer_start(&ctx->timer, tim, HRTIMER_MODE_REL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) at86rf230_async_state_change_start(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct at86rf230_state_change *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct at86rf230_local *lp = ctx->lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) u8 *buf = ctx->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) const u8 trx_state = buf[1] & TRX_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* Check for "possible" STATE_TRANSITION_IN_PROGRESS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (trx_state == STATE_TRANSITION_IN_PROGRESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) at86rf230_async_state_change_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* Check if we already are in the state which we change in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (trx_state == ctx->to_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (ctx->complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ctx->complete(context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* Set current state to the context of state change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ctx->from_state = trx_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Going into the next step for a state change which do a timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * relevant delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) at86rf230_async_write_reg(lp, RG_TRX_STATE, ctx->to_state, ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) at86rf230_async_state_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) at86rf230_async_state_change(struct at86rf230_local *lp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct at86rf230_state_change *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) const u8 state, void (*complete)(void *context))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* Initialization for the state change context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ctx->to_state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ctx->complete = complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) at86rf230_async_state_change_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) at86rf230_sync_state_change_complete(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct at86rf230_state_change *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct at86rf230_local *lp = ctx->lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) complete(&lp->state_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* This function do a sync framework above the async state change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * Some callbacks of the IEEE 802.15.4 driver interface need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * handled synchronously.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) at86rf230_sync_state_change(struct at86rf230_local *lp, unsigned int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) unsigned long rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) at86rf230_async_state_change(lp, &lp->state, state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) at86rf230_sync_state_change_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) rc = wait_for_completion_timeout(&lp->state_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) msecs_to_jiffies(100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) at86rf230_async_error(lp, &lp->state, -ETIMEDOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) at86rf230_tx_complete(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct at86rf230_state_change *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct at86rf230_local *lp = ctx->lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ieee802154_xmit_complete(lp->hw, lp->tx_skb, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) kfree(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) at86rf230_tx_on(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct at86rf230_state_change *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct at86rf230_local *lp = ctx->lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) at86rf230_async_state_change(lp, ctx, STATE_RX_AACK_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) at86rf230_tx_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) at86rf230_tx_trac_check(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct at86rf230_state_change *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct at86rf230_local *lp = ctx->lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (IS_ENABLED(CONFIG_IEEE802154_AT86RF230_DEBUGFS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u8 trac = TRAC_MASK(ctx->buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) switch (trac) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) case TRAC_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) lp->trac.success++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case TRAC_SUCCESS_DATA_PENDING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) lp->trac.success_data_pending++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) case TRAC_CHANNEL_ACCESS_FAILURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) lp->trac.channel_access_failure++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) case TRAC_NO_ACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) lp->trac.no_ack++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) case TRAC_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) lp->trac.invalid++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) WARN_ONCE(1, "received tx trac status %d\n", trac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) at86rf230_async_state_change(lp, ctx, STATE_TX_ON, at86rf230_tx_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) at86rf230_rx_read_frame_complete(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct at86rf230_state_change *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct at86rf230_local *lp = ctx->lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) const u8 *buf = ctx->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u8 len, lqi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) len = buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (!ieee802154_is_valid_psdu_len(len)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dev_vdbg(&lp->spi->dev, "corrupted frame received\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) len = IEEE802154_MTU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) lqi = buf[2 + len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) skb = dev_alloc_skb(IEEE802154_MTU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev_vdbg(&lp->spi->dev, "failed to allocate sk_buff\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) kfree(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) skb_put_data(skb, buf + 2, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ieee802154_rx_irqsafe(lp->hw, skb, lqi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) kfree(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) at86rf230_rx_trac_check(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct at86rf230_state_change *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct at86rf230_local *lp = ctx->lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) u8 *buf = ctx->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (IS_ENABLED(CONFIG_IEEE802154_AT86RF230_DEBUGFS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) u8 trac = TRAC_MASK(buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) switch (trac) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) case TRAC_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) lp->trac.success++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) case TRAC_SUCCESS_WAIT_FOR_ACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) lp->trac.success_wait_for_ack++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) case TRAC_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) lp->trac.invalid++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) WARN_ONCE(1, "received rx trac status %d\n", trac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) buf[0] = CMD_FB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ctx->trx.len = AT86RF2XX_MAX_BUF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) ctx->msg.complete = at86rf230_rx_read_frame_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) rc = spi_async(lp->spi, &ctx->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ctx->trx.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) at86rf230_async_error(lp, ctx, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) at86rf230_irq_trx_end(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct at86rf230_state_change *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct at86rf230_local *lp = ctx->lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (lp->is_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) lp->is_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) at86rf230_async_read_reg(lp, RG_TRX_STATE, ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) at86rf230_tx_trac_check);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) at86rf230_async_read_reg(lp, RG_TRX_STATE, ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) at86rf230_rx_trac_check);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) at86rf230_irq_status(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct at86rf230_state_change *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct at86rf230_local *lp = ctx->lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) const u8 *buf = ctx->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) u8 irq = buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) enable_irq(lp->spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (irq & IRQ_TRX_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) at86rf230_irq_trx_end(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dev_err(&lp->spi->dev, "not supported irq %02x received\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) kfree(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) at86rf230_setup_spi_messages(struct at86rf230_local *lp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct at86rf230_state_change *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) state->lp = lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) state->irq = lp->spi->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) spi_message_init(&state->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) state->msg.context = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) state->trx.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) state->trx.tx_buf = state->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) state->trx.rx_buf = state->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) spi_message_add_tail(&state->trx, &state->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) hrtimer_init(&state->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) state->timer.function = at86rf230_async_state_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static irqreturn_t at86rf230_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct at86rf230_local *lp = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct at86rf230_state_change *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) disable_irq_nosync(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) ctx = kzalloc(sizeof(*ctx), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (!ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) enable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) at86rf230_setup_spi_messages(lp, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* tell on error handling to free ctx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ctx->free = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ctx->buf[0] = (RG_IRQ_STATUS & CMD_REG_MASK) | CMD_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ctx->msg.complete = at86rf230_irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) rc = spi_async(lp->spi, &ctx->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) at86rf230_async_error(lp, ctx, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) enable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) at86rf230_write_frame_complete(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct at86rf230_state_change *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct at86rf230_local *lp = ctx->lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ctx->trx.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (gpio_is_valid(lp->slp_tr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) at86rf230_slp_tr_rising_edge(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) at86rf230_async_write_reg(lp, RG_TRX_STATE, STATE_BUSY_TX, ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) at86rf230_write_frame(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct at86rf230_state_change *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct at86rf230_local *lp = ctx->lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct sk_buff *skb = lp->tx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) u8 *buf = ctx->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) lp->is_tx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) buf[0] = CMD_FB | CMD_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) buf[1] = skb->len + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) memcpy(buf + 2, skb->data, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ctx->trx.len = skb->len + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ctx->msg.complete = at86rf230_write_frame_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) rc = spi_async(lp->spi, &ctx->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ctx->trx.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) at86rf230_async_error(lp, ctx, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) at86rf230_xmit_tx_on(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct at86rf230_state_change *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct at86rf230_local *lp = ctx->lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) at86rf230_async_state_change(lp, ctx, STATE_TX_ARET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) at86rf230_write_frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) at86rf230_xmit_start(void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct at86rf230_state_change *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct at86rf230_local *lp = ctx->lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* check if we change from off state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (lp->is_tx_from_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) at86rf230_async_state_change(lp, ctx, STATE_TX_ARET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) at86rf230_write_frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) at86rf230_async_state_change(lp, ctx, STATE_TX_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) at86rf230_xmit_tx_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) at86rf230_xmit(struct ieee802154_hw *hw, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct at86rf230_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct at86rf230_state_change *ctx = &lp->tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) lp->tx_skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) lp->tx_retry = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* After 5 minutes in PLL and the same frequency we run again the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * calibration loops which is recommended by at86rf2xx datasheets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * The calibration is initiate by a state change from TRX_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * to TX_ON, the lp->cal_timeout should be reinit by state_delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * function then to start in the next 5 minutes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (time_is_before_jiffies(lp->cal_timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) lp->is_tx_from_off = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) at86rf230_async_state_change(lp, ctx, STATE_TRX_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) at86rf230_xmit_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) lp->is_tx_from_off = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) at86rf230_xmit_start(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) at86rf230_ed(struct ieee802154_hw *hw, u8 *level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) WARN_ON(!level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) *level = 0xbe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) at86rf230_start(struct ieee802154_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct at86rf230_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* reset trac stats on start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (IS_ENABLED(CONFIG_IEEE802154_AT86RF230_DEBUGFS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) memset(&lp->trac, 0, sizeof(struct at86rf230_trac));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) at86rf230_awake(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) enable_irq(lp->spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return at86rf230_sync_state_change(lp, STATE_RX_AACK_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) at86rf230_stop(struct ieee802154_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct at86rf230_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) u8 csma_seed[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) at86rf230_sync_state_change(lp, STATE_FORCE_TRX_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) disable_irq(lp->spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* It's recommended to set random new csma_seeds before sleep state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * Makes only sense in the stop callback, not doing this inside of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * at86rf230_sleep, this is also used when we don't transmit afterwards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * when calling start callback again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) get_random_bytes(csma_seed, ARRAY_SIZE(csma_seed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) at86rf230_write_subreg(lp, SR_CSMA_SEED_0, csma_seed[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) at86rf230_write_subreg(lp, SR_CSMA_SEED_1, csma_seed[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) at86rf230_sleep(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) at86rf23x_set_channel(struct at86rf230_local *lp, u8 page, u8 channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return at86rf230_write_subreg(lp, SR_CHANNEL, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define AT86RF2XX_MAX_ED_LEVELS 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static const s32 at86rf233_ed_levels[AT86RF2XX_MAX_ED_LEVELS + 1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) -9400, -9200, -9000, -8800, -8600, -8400, -8200, -8000, -7800, -7600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) -7400, -7200, -7000, -6800, -6600, -6400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static const s32 at86rf231_ed_levels[AT86RF2XX_MAX_ED_LEVELS + 1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) -9100, -8900, -8700, -8500, -8300, -8100, -7900, -7700, -7500, -7300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) -7100, -6900, -6700, -6500, -6300, -6100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static const s32 at86rf212_ed_levels_100[AT86RF2XX_MAX_ED_LEVELS + 1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) -10000, -9800, -9600, -9400, -9200, -9000, -8800, -8600, -8400, -8200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) -8000, -7800, -7600, -7400, -7200, -7000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static const s32 at86rf212_ed_levels_98[AT86RF2XX_MAX_ED_LEVELS + 1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) -9800, -9600, -9400, -9200, -9000, -8800, -8600, -8400, -8200, -8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) -7800, -7600, -7400, -7200, -7000, -6800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) at86rf212_update_cca_ed_level(struct at86rf230_local *lp, int rssi_base_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) unsigned int cca_ed_thres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) rc = at86rf230_read_subreg(lp, SR_CCA_ED_THRES, &cca_ed_thres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) switch (rssi_base_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) case -98:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) lp->hw->phy->supported.cca_ed_levels = at86rf212_ed_levels_98;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf212_ed_levels_98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) lp->hw->phy->cca_ed_level = at86rf212_ed_levels_98[cca_ed_thres];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) case -100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) lp->hw->phy->supported.cca_ed_levels = at86rf212_ed_levels_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf212_ed_levels_100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) lp->hw->phy->cca_ed_level = at86rf212_ed_levels_100[cca_ed_thres];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) at86rf212_set_channel(struct at86rf230_local *lp, u8 page, u8 channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (channel == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (page == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) lp->data->rssi_base_val = -100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) lp->data->rssi_base_val = -98;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) rc = at86rf212_update_cca_ed_level(lp, lp->data->rssi_base_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* This sets the symbol_duration according frequency on the 212.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * TODO move this handling while set channel and page in cfg802154.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * We can do that, this timings are according 802.15.4 standard.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) * If we do that in cfg802154, this is a more generic calculation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * This should also protected from ifs_timer. Means cancel timer and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * init with a new value. For now, this is okay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (channel == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (page == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* SUB:0 and BPSK:0 -> BPSK-20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) lp->hw->phy->symbol_duration = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /* SUB:1 and BPSK:0 -> BPSK-40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) lp->hw->phy->symbol_duration = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (page == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) /* SUB:0 and BPSK:1 -> OQPSK-100/200/400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) lp->hw->phy->symbol_duration = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) /* SUB:1 and BPSK:1 -> OQPSK-250/500/1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) lp->hw->phy->symbol_duration = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) lp->hw->phy->lifs_period = IEEE802154_LIFS_PERIOD *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) lp->hw->phy->symbol_duration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) lp->hw->phy->sifs_period = IEEE802154_SIFS_PERIOD *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) lp->hw->phy->symbol_duration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return at86rf230_write_subreg(lp, SR_CHANNEL, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) at86rf230_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) struct at86rf230_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) rc = lp->data->set_channel(lp, page, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /* Wait for PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) usleep_range(lp->data->t_channel_switch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) lp->data->t_channel_switch + 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) lp->cal_timeout = jiffies + AT86RF2XX_CAL_LOOP_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) at86rf230_set_hw_addr_filt(struct ieee802154_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct ieee802154_hw_addr_filt *filt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) unsigned long changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct at86rf230_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) u16 addr = le16_to_cpu(filt->short_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) dev_vdbg(&lp->spi->dev, "%s called for saddr\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) __at86rf230_write(lp, RG_SHORT_ADDR_0, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) __at86rf230_write(lp, RG_SHORT_ADDR_1, addr >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (changed & IEEE802154_AFILT_PANID_CHANGED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) u16 pan = le16_to_cpu(filt->pan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) dev_vdbg(&lp->spi->dev, "%s called for pan id\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) __at86rf230_write(lp, RG_PAN_ID_0, pan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) __at86rf230_write(lp, RG_PAN_ID_1, pan >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) u8 i, addr[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) memcpy(addr, &filt->ieee_addr, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) dev_vdbg(&lp->spi->dev, "%s called for IEEE addr\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) __at86rf230_write(lp, RG_IEEE_ADDR_0 + i, addr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (changed & IEEE802154_AFILT_PANC_CHANGED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) dev_vdbg(&lp->spi->dev, "%s called for panc change\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (filt->pan_coord)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define AT86RF23X_MAX_TX_POWERS 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static const s32 at86rf233_powers[AT86RF23X_MAX_TX_POWERS + 1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) 400, 370, 340, 300, 250, 200, 100, 0, -100, -200, -300, -400, -600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) -800, -1200, -1700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) static const s32 at86rf231_powers[AT86RF23X_MAX_TX_POWERS + 1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) 300, 280, 230, 180, 130, 70, 0, -100, -200, -300, -400, -500, -700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) -900, -1200, -1700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define AT86RF212_MAX_TX_POWERS 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static const s32 at86rf212_powers[AT86RF212_MAX_TX_POWERS + 1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) 500, 400, 300, 200, 100, 0, -100, -200, -300, -400, -500, -600, -700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) -800, -900, -1000, -1100, -1200, -1300, -1400, -1500, -1600, -1700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) -1800, -1900, -2000, -2100, -2200, -2300, -2400, -2500, -2600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) at86rf23x_set_txpower(struct at86rf230_local *lp, s32 mbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) for (i = 0; i < lp->hw->phy->supported.tx_powers_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (lp->hw->phy->supported.tx_powers[i] == mbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return at86rf230_write_subreg(lp, SR_TX_PWR_23X, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) at86rf212_set_txpower(struct at86rf230_local *lp, s32 mbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) for (i = 0; i < lp->hw->phy->supported.tx_powers_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (lp->hw->phy->supported.tx_powers[i] == mbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) return at86rf230_write_subreg(lp, SR_TX_PWR_212, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) at86rf230_set_txpower(struct ieee802154_hw *hw, s32 mbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) struct at86rf230_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return lp->data->set_txpower(lp, mbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) at86rf230_set_lbt(struct ieee802154_hw *hw, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct at86rf230_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return at86rf230_write_subreg(lp, SR_CSMA_LBT_MODE, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) at86rf230_set_cca_mode(struct ieee802154_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) const struct wpan_phy_cca *cca)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) struct at86rf230_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /* mapping 802.15.4 to driver spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) switch (cca->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) case NL802154_CCA_ENERGY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) case NL802154_CCA_CARRIER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) val = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) case NL802154_CCA_ENERGY_CARRIER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) switch (cca->opt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) case NL802154_CCA_OPT_ENERGY_CARRIER_AND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) val = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) case NL802154_CCA_OPT_ENERGY_CARRIER_OR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) return at86rf230_write_subreg(lp, SR_CCA_MODE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) at86rf230_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) struct at86rf230_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) for (i = 0; i < hw->phy->supported.cca_ed_levels_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (hw->phy->supported.cca_ed_levels[i] == mbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return at86rf230_write_subreg(lp, SR_CCA_ED_THRES, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) at86rf230_set_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) u8 retries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) struct at86rf230_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) rc = at86rf230_write_subreg(lp, SR_MIN_BE, min_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) rc = at86rf230_write_subreg(lp, SR_MAX_BE, max_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) return at86rf230_write_subreg(lp, SR_MAX_CSMA_RETRIES, retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) at86rf230_set_frame_retries(struct ieee802154_hw *hw, s8 retries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct at86rf230_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) return at86rf230_write_subreg(lp, SR_MAX_FRAME_RETRIES, retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) at86rf230_set_promiscuous_mode(struct ieee802154_hw *hw, const bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) struct at86rf230_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) rc = at86rf230_write_subreg(lp, SR_AACK_DIS_ACK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) rc = at86rf230_write_subreg(lp, SR_AACK_PROM_MODE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) rc = at86rf230_write_subreg(lp, SR_AACK_PROM_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) rc = at86rf230_write_subreg(lp, SR_AACK_DIS_ACK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) static const struct ieee802154_ops at86rf230_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .xmit_async = at86rf230_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .ed = at86rf230_ed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .set_channel = at86rf230_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .start = at86rf230_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .stop = at86rf230_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .set_hw_addr_filt = at86rf230_set_hw_addr_filt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .set_txpower = at86rf230_set_txpower,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .set_lbt = at86rf230_set_lbt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .set_cca_mode = at86rf230_set_cca_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .set_cca_ed_level = at86rf230_set_cca_ed_level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .set_csma_params = at86rf230_set_csma_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .set_frame_retries = at86rf230_set_frame_retries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .set_promiscuous_mode = at86rf230_set_promiscuous_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static struct at86rf2xx_chip_data at86rf233_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .t_sleep_cycle = 330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .t_channel_switch = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .t_reset_to_off = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .t_off_to_aack = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .t_off_to_tx_on = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .t_off_to_sleep = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .t_sleep_to_off = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .t_frame = 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .t_p_ack = 545,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .rssi_base_val = -94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .set_channel = at86rf23x_set_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .set_txpower = at86rf23x_set_txpower,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) static struct at86rf2xx_chip_data at86rf231_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .t_sleep_cycle = 330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .t_channel_switch = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .t_reset_to_off = 37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .t_off_to_aack = 110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .t_off_to_tx_on = 110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .t_off_to_sleep = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .t_sleep_to_off = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .t_frame = 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .t_p_ack = 545,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .rssi_base_val = -91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .set_channel = at86rf23x_set_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .set_txpower = at86rf23x_set_txpower,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) static struct at86rf2xx_chip_data at86rf212_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .t_sleep_cycle = 330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .t_channel_switch = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .t_reset_to_off = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .t_off_to_aack = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .t_off_to_tx_on = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .t_off_to_sleep = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .t_sleep_to_off = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .t_frame = 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .t_p_ack = 545,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .rssi_base_val = -100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .set_channel = at86rf212_set_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .set_txpower = at86rf212_set_txpower,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static int at86rf230_hw_init(struct at86rf230_local *lp, u8 xtal_trim)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) int rc, irq_type, irq_pol = IRQ_ACTIVE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) unsigned int dvdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) u8 csma_seed[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) rc = at86rf230_sync_state_change(lp, STATE_FORCE_TRX_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) irq_type = irq_get_trigger_type(lp->spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (irq_type == IRQ_TYPE_EDGE_FALLING ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) irq_type == IRQ_TYPE_LEVEL_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) irq_pol = IRQ_ACTIVE_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) rc = at86rf230_write_subreg(lp, SR_IRQ_POLARITY, irq_pol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) rc = at86rf230_write_subreg(lp, SR_RX_SAFE_MODE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) rc = at86rf230_write_subreg(lp, SR_IRQ_MASK, IRQ_TRX_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) /* reset values differs in at86rf231 and at86rf233 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) rc = at86rf230_write_subreg(lp, SR_IRQ_MASK_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) get_random_bytes(csma_seed, ARRAY_SIZE(csma_seed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_0, csma_seed[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_1, csma_seed[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) /* CLKM changes are applied immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) rc = at86rf230_write_subreg(lp, SR_CLKM_SHA_SEL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) /* Turn CLKM Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) rc = at86rf230_write_subreg(lp, SR_CLKM_CTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /* Wait the next SLEEP cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) usleep_range(lp->data->t_sleep_cycle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) lp->data->t_sleep_cycle + 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) /* xtal_trim value is calculated by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) * CL = 0.5 * (CX + CTRIM + CPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) * whereas:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) * CL = capacitor of used crystal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) * CX = connected capacitors at xtal pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) * CPAR = in all at86rf2xx datasheets this is a constant value 3 pF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * but this is different on each board setup. You need to fine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) * tuning this value via CTRIM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * CTRIM = variable capacitor setting. Resolution is 0.3 pF range is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) * 0 pF upto 4.5 pF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) * Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) * atben transceiver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) * CL = 8 pF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) * CX = 12 pF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) * CPAR = 3 pF (We assume the magic constant from datasheet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) * CTRIM = 0.9 pF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) * (12+0.9+3)/2 = 7.95 which is nearly at 8 pF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) * xtal_trim = 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * openlabs transceiver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) * CL = 16 pF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) * CX = 22 pF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) * CPAR = 3 pF (We assume the magic constant from datasheet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * CTRIM = 4.5 pF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) * (22+4.5+3)/2 = 14.75 which is the nearest value to 16 pF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) * xtal_trim = 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) rc = at86rf230_write_subreg(lp, SR_XTAL_TRIM, xtal_trim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) rc = at86rf230_read_subreg(lp, SR_DVDD_OK, &dvdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (!dvdd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) dev_err(&lp->spi->dev, "DVDD error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /* Force setting slotted operation bit to 0. Sometimes the atben
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) * sets this bit and I don't know why. We set this always force
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) * to zero while probing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) return at86rf230_write_subreg(lp, SR_SLOTTED_OPERATION, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) at86rf230_get_pdata(struct spi_device *spi, int *rstn, int *slp_tr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) u8 *xtal_trim)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) struct at86rf230_platform_data *pdata = spi->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) if (!IS_ENABLED(CONFIG_OF) || !spi->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) *rstn = pdata->rstn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) *slp_tr = pdata->slp_tr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) *xtal_trim = pdata->xtal_trim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) *rstn = of_get_named_gpio(spi->dev.of_node, "reset-gpio", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) *slp_tr = of_get_named_gpio(spi->dev.of_node, "sleep-gpio", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) ret = of_property_read_u8(spi->dev.of_node, "xtal-trim", xtal_trim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (ret < 0 && ret != -EINVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) at86rf230_detect_device(struct at86rf230_local *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) unsigned int part, version, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) u16 man_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) const char *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) rc = __at86rf230_read(lp, RG_MAN_ID_0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) man_id |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) rc = __at86rf230_read(lp, RG_MAN_ID_1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) man_id |= (val << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) rc = __at86rf230_read(lp, RG_PART_NUM, &part);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) rc = __at86rf230_read(lp, RG_VERSION_NUM, &version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (man_id != 0x001f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) dev_err(&lp->spi->dev, "Non-Atmel dev found (MAN_ID %02x %02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) man_id >> 8, man_id & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) lp->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) IEEE802154_HW_CSMA_PARAMS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) IEEE802154_HW_FRAME_RETRIES | IEEE802154_HW_AFILT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) IEEE802154_HW_PROMISCUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) lp->hw->phy->flags = WPAN_PHY_FLAG_TXPOWER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) WPAN_PHY_FLAG_CCA_ED_LEVEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) WPAN_PHY_FLAG_CCA_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) lp->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) BIT(NL802154_CCA_CARRIER) | BIT(NL802154_CCA_ENERGY_CARRIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) lp->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) BIT(NL802154_CCA_OPT_ENERGY_CARRIER_OR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) lp->hw->phy->cca.mode = NL802154_CCA_ENERGY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) switch (part) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) chip = "at86rf230";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) rc = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) goto not_supp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) chip = "at86rf231";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) lp->data = &at86rf231_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) lp->hw->phy->supported.channels[0] = 0x7FFF800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) lp->hw->phy->current_channel = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) lp->hw->phy->symbol_duration = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) lp->hw->phy->supported.tx_powers = at86rf231_powers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) lp->hw->phy->supported.tx_powers_size = ARRAY_SIZE(at86rf231_powers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) lp->hw->phy->supported.cca_ed_levels = at86rf231_ed_levels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf231_ed_levels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) chip = "at86rf212";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) lp->data = &at86rf212_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) lp->hw->flags |= IEEE802154_HW_LBT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) lp->hw->phy->supported.channels[0] = 0x00007FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) lp->hw->phy->supported.channels[2] = 0x00007FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) lp->hw->phy->current_channel = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) lp->hw->phy->symbol_duration = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) lp->hw->phy->supported.lbt = NL802154_SUPPORTED_BOOL_BOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) lp->hw->phy->supported.tx_powers = at86rf212_powers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) lp->hw->phy->supported.tx_powers_size = ARRAY_SIZE(at86rf212_powers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) lp->hw->phy->supported.cca_ed_levels = at86rf212_ed_levels_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf212_ed_levels_100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) case 11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) chip = "at86rf233";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) lp->data = &at86rf233_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) lp->hw->phy->supported.channels[0] = 0x7FFF800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) lp->hw->phy->current_channel = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) lp->hw->phy->symbol_duration = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) lp->hw->phy->supported.tx_powers = at86rf233_powers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) lp->hw->phy->supported.tx_powers_size = ARRAY_SIZE(at86rf233_powers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) lp->hw->phy->supported.cca_ed_levels = at86rf233_ed_levels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf233_ed_levels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) chip = "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) rc = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) goto not_supp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) lp->hw->phy->cca_ed_level = lp->hw->phy->supported.cca_ed_levels[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) lp->hw->phy->transmit_power = lp->hw->phy->supported.tx_powers[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) not_supp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) dev_info(&lp->spi->dev, "Detected %s chip version %d\n", chip, version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) #ifdef CONFIG_IEEE802154_AT86RF230_DEBUGFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) static struct dentry *at86rf230_debugfs_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static int at86rf230_stats_show(struct seq_file *file, void *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) struct at86rf230_local *lp = file->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) seq_printf(file, "SUCCESS:\t\t%8llu\n", lp->trac.success);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) seq_printf(file, "SUCCESS_DATA_PENDING:\t%8llu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) lp->trac.success_data_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) seq_printf(file, "SUCCESS_WAIT_FOR_ACK:\t%8llu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) lp->trac.success_wait_for_ack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) seq_printf(file, "CHANNEL_ACCESS_FAILURE:\t%8llu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) lp->trac.channel_access_failure);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) seq_printf(file, "NO_ACK:\t\t\t%8llu\n", lp->trac.no_ack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) seq_printf(file, "INVALID:\t\t%8llu\n", lp->trac.invalid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) DEFINE_SHOW_ATTRIBUTE(at86rf230_stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) static void at86rf230_debugfs_init(struct at86rf230_local *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) char debugfs_dir_name[DNAME_INLINE_LEN + 1] = "at86rf230-";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) strncat(debugfs_dir_name, dev_name(&lp->spi->dev), DNAME_INLINE_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) at86rf230_debugfs_root = debugfs_create_dir(debugfs_dir_name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) debugfs_create_file("trac_stats", 0444, at86rf230_debugfs_root, lp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) &at86rf230_stats_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) static void at86rf230_debugfs_remove(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) debugfs_remove_recursive(at86rf230_debugfs_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) static void at86rf230_debugfs_init(struct at86rf230_local *lp) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) static void at86rf230_debugfs_remove(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) static int at86rf230_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) struct ieee802154_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) struct at86rf230_local *lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) int rc, irq_type, rstn, slp_tr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) u8 xtal_trim = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) if (!spi->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) dev_err(&spi->dev, "no IRQ specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) rc = at86rf230_get_pdata(spi, &rstn, &slp_tr, &xtal_trim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) dev_err(&spi->dev, "failed to parse platform_data: %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) if (gpio_is_valid(rstn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) rc = devm_gpio_request_one(&spi->dev, rstn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) GPIOF_OUT_INIT_HIGH, "rstn");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) if (gpio_is_valid(slp_tr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) rc = devm_gpio_request_one(&spi->dev, slp_tr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) GPIOF_OUT_INIT_LOW, "slp_tr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) /* Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) if (gpio_is_valid(rstn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) gpio_set_value_cansleep(rstn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) gpio_set_value_cansleep(rstn, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) usleep_range(120, 240);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) hw = ieee802154_alloc_hw(sizeof(*lp), &at86rf230_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) lp->hw = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) lp->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) lp->slp_tr = slp_tr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) hw->parent = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) ieee802154_random_extended_addr(&hw->phy->perm_extended_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) lp->regmap = devm_regmap_init_spi(spi, &at86rf230_regmap_spi_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) if (IS_ERR(lp->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) rc = PTR_ERR(lp->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) dev_err(&spi->dev, "Failed to allocate register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) goto free_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) at86rf230_setup_spi_messages(lp, &lp->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) at86rf230_setup_spi_messages(lp, &lp->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) rc = at86rf230_detect_device(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) goto free_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) init_completion(&lp->state_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) spi_set_drvdata(spi, lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) rc = at86rf230_hw_init(lp, xtal_trim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) goto free_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) /* Read irq status register to reset irq line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) rc = at86rf230_read_subreg(lp, RG_IRQ_STATUS, 0xff, 0, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) goto free_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) irq_type = irq_get_trigger_type(spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) if (!irq_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) irq_type = IRQF_TRIGGER_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) rc = devm_request_irq(&spi->dev, spi->irq, at86rf230_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) IRQF_SHARED | irq_type, dev_name(&spi->dev), lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) goto free_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) /* disable_irq by default and wait for starting hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) disable_irq(spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) /* going into sleep by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) at86rf230_sleep(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) at86rf230_debugfs_init(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) rc = ieee802154_register_hw(lp->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) goto free_debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) free_debugfs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) at86rf230_debugfs_remove();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) free_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) ieee802154_free_hw(lp->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) static int at86rf230_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) struct at86rf230_local *lp = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) /* mask all at86rf230 irq's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) at86rf230_write_subreg(lp, SR_IRQ_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) ieee802154_unregister_hw(lp->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) ieee802154_free_hw(lp->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) at86rf230_debugfs_remove();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) dev_dbg(&spi->dev, "unregistered at86rf230\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) static const struct of_device_id at86rf230_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) { .compatible = "atmel,at86rf230", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) { .compatible = "atmel,at86rf231", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) { .compatible = "atmel,at86rf233", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) { .compatible = "atmel,at86rf212", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) MODULE_DEVICE_TABLE(of, at86rf230_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) static const struct spi_device_id at86rf230_device_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) { .name = "at86rf230", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) { .name = "at86rf231", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) { .name = "at86rf233", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) { .name = "at86rf212", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) MODULE_DEVICE_TABLE(spi, at86rf230_device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) static struct spi_driver at86rf230_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .id_table = at86rf230_device_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .of_match_table = of_match_ptr(at86rf230_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .name = "at86rf230",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .probe = at86rf230_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .remove = at86rf230_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) module_spi_driver(at86rf230_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) MODULE_DESCRIPTION("AT86RF230 Transceiver Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags