^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Analog Devices ADF7242 Low-Power IEEE 802.15.4 Transceiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2009-2017 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * https://www.analog.com/ADF7242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/ieee802154.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <net/mac802154.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <net/cfg802154.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FIRMWARE "adf7242_firmware.bin"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MAX_POLL_LOOPS 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* All Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_EXT_CTRL 0x100 /* RW External LNA/PA and internal PA control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_TX_FSK_TEST 0x101 /* RW TX FSK test mode configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_CCA1 0x105 /* RW RSSI threshold for CCA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REG_CCA2 0x106 /* RW CCA mode configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_BUFFERCFG 0x107 /* RW RX_BUFFER overwrite control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define REG_PKT_CFG 0x108 /* RW FCS evaluation configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define REG_DELAYCFG0 0x109 /* RW RC_RX command to SFD or sync word delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_DELAYCFG1 0x10A /* RW RC_TX command to TX state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define REG_DELAYCFG2 0x10B /* RW Mac delay extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define REG_SYNC_WORD0 0x10C /* RW sync word bits [7:0] of [23:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define REG_SYNC_WORD1 0x10D /* RW sync word bits [15:8] of [23:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define REG_SYNC_WORD2 0x10E /* RW sync word bits [23:16] of [23:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define REG_SYNC_CONFIG 0x10F /* RW sync word configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REG_RC_CFG 0x13E /* RW RX / TX packet configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REG_RC_VAR44 0x13F /* RW RESERVED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REG_CH_FREQ0 0x300 /* RW Channel Frequency Settings - Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_CH_FREQ1 0x301 /* RW Channel Frequency Settings - Middle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define REG_CH_FREQ2 0x302 /* RW Channel Frequency Settings - High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_TX_FD 0x304 /* RW TX Frequency Deviation Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_DM_CFG0 0x305 /* RW RX Discriminator BW Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_TX_M 0x306 /* RW TX Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REG_RX_M 0x307 /* RW RX Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define REG_RRB 0x30C /* R RSSI Readback Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define REG_LRB 0x30D /* R Link Quality Readback Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define REG_DR0 0x30E /* RW bits [15:8] of [15:0] data rate setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define REG_DR1 0x30F /* RW bits [7:0] of [15:0] data rate setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_PRAMPG 0x313 /* RW RESERVED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define REG_TXPB 0x314 /* RW TX Packet Storage Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define REG_RXPB 0x315 /* RW RX Packet Storage Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define REG_TMR_CFG0 0x316 /* RW Wake up Timer Conf Register - High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define REG_TMR_CFG1 0x317 /* RW Wake up Timer Conf Register - Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define REG_TMR_RLD0 0x318 /* RW Wake up Timer Value Register - High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define REG_TMR_RLD1 0x319 /* RW Wake up Timer Value Register - Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define REG_TMR_CTRL 0x31A /* RW Wake up Timer Timeout flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define REG_PD_AUX 0x31E /* RW Battmon enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define REG_GP_CFG 0x32C /* RW GPIO Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define REG_GP_OUT 0x32D /* RW GPIO Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define REG_GP_IN 0x32E /* R GPIO Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define REG_SYNT 0x335 /* RW bandwidth calibration timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define REG_CAL_CFG 0x33D /* RW Calibration Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define REG_PA_BIAS 0x36E /* RW PA BIAS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define REG_SYNT_CAL 0x371 /* RW Oscillator and Doubler Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define REG_IIRF_CFG 0x389 /* RW BB Filter Decimation Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define REG_CDR_CFG 0x38A /* RW CDR kVCO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define REG_DM_CFG1 0x38B /* RW Postdemodulator Filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define REG_AGCSTAT 0x38E /* R RXBB Ref Osc Calibration Engine Readback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define REG_RXCAL0 0x395 /* RW RX BB filter tuning, LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define REG_RXCAL1 0x396 /* RW RX BB filter tuning, MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define REG_RXFE_CFG 0x39B /* RW RXBB Ref Osc & RXFE Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define REG_PA_RR 0x3A7 /* RW Set PA ramp rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define REG_PA_CFG 0x3A8 /* RW PA enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define REG_EXTPA_CFG 0x3A9 /* RW External PA BIAS DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define REG_EXTPA_MSC 0x3AA /* RW PA Bias Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define REG_ADC_RBK 0x3AE /* R Readback temp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define REG_AGC_CFG1 0x3B2 /* RW GC Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define REG_AGC_MAX 0x3B4 /* RW Slew rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define REG_AGC_CFG2 0x3B6 /* RW RSSI Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define REG_AGC_CFG3 0x3B7 /* RW RSSI Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define REG_AGC_CFG4 0x3B8 /* RW RSSI Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define REG_AGC_CFG5 0x3B9 /* RW RSSI & NDEC Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define REG_AGC_CFG6 0x3BA /* RW NDEC Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define REG_OCL_CFG1 0x3C4 /* RW OCL System Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define REG_IRQ1_EN0 0x3C7 /* RW Interrupt Mask set bits for IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define REG_IRQ1_EN1 0x3C8 /* RW Interrupt Mask set bits for IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define REG_IRQ2_EN0 0x3C9 /* RW Interrupt Mask set bits for IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define REG_IRQ2_EN1 0x3CA /* RW Interrupt Mask set bits for IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define REG_IRQ1_SRC0 0x3CB /* RW Interrupt Source bits for IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define REG_IRQ1_SRC1 0x3CC /* RW Interrupt Source bits for IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define REG_OCL_BW0 0x3D2 /* RW OCL System Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define REG_OCL_BW1 0x3D3 /* RW OCL System Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define REG_OCL_BW2 0x3D4 /* RW OCL System Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define REG_OCL_BW3 0x3D5 /* RW OCL System Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define REG_OCL_BW4 0x3D6 /* RW OCL System Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define REG_OCL_BWS 0x3D7 /* RW OCL System Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define REG_OCL_CFG13 0x3E0 /* RW OCL System Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define REG_GP_DRV 0x3E3 /* RW I/O pads Configuration and bg trim */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define REG_BM_CFG 0x3E6 /* RW Batt. Monitor Threshold Voltage setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define REG_SFD_15_4 0x3F4 /* RW Option to set non standard SFD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define REG_AFC_CFG 0x3F7 /* RW AFC mode and polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define REG_AFC_KI_KP 0x3F8 /* RW AFC ki and kp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define REG_AFC_RANGE 0x3F9 /* RW AFC range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define REG_AFC_READ 0x3FA /* RW Readback frequency error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* REG_EXTPA_MSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PA_PWR(x) (((x) & 0xF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define EXTPA_BIAS_SRC BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define EXTPA_BIAS_MODE(x) (((x) & 0x7) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* REG_PA_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PA_BRIDGE_DBIAS(x) (((x) & 0x1F) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PA_DBIAS_HIGH_POWER 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PA_DBIAS_LOW_POWER 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* REG_PA_BIAS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PA_BIAS_CTRL(x) (((x) & 0x1F) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define REG_PA_BIAS_DFL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PA_BIAS_HIGH_POWER 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PA_BIAS_LOW_POWER 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define REG_PAN_ID0 0x112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define REG_PAN_ID1 0x113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define REG_SHORT_ADDR_0 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define REG_SHORT_ADDR_1 0x115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define REG_IEEE_ADDR_0 0x116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define REG_IEEE_ADDR_1 0x117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define REG_IEEE_ADDR_2 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define REG_IEEE_ADDR_3 0x119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define REG_IEEE_ADDR_4 0x11A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define REG_IEEE_ADDR_5 0x11B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define REG_IEEE_ADDR_6 0x11C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define REG_IEEE_ADDR_7 0x11D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define REG_FFILT_CFG 0x11E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define REG_AUTO_CFG 0x11F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define REG_AUTO_TX1 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define REG_AUTO_TX2 0x121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define REG_AUTO_STATUS 0x122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* REG_FFILT_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ACCEPT_BEACON_FRAMES BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ACCEPT_DATA_FRAMES BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ACCEPT_ACK_FRAMES BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ACCEPT_MACCMD_FRAMES BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ACCEPT_RESERVED_FRAMES BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ACCEPT_ALL_ADDRESS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* REG_AUTO_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define AUTO_ACK_FRAMEPEND BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IS_PANCOORD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define RX_AUTO_ACK_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CSMA_CA_RX_TURNAROUND BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* REG_AUTO_TX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MAX_FRAME_RETRIES(x) ((x) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MAX_CCA_RETRIES(x) (((x) & 0x7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* REG_AUTO_TX2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CSMA_MAX_BE(x) ((x) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CSMA_MIN_BE(x) (((x) & 0xF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CMD_SPI_NOP 0xFF /* No operation. Use for dummy writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CMD_SPI_PKT_WR 0x10 /* Write telegram to the Packet RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * starting from the TX packet base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * pointer tx_packet_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CMD_SPI_PKT_RD 0x30 /* Read telegram from the Packet RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * starting from RX packet base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * pointer rxpb.rx_packet_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CMD_SPI_MEM_WR(x) (0x18 + (x >> 8)) /* Write data to MCR or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Packet RAM sequentially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CMD_SPI_MEM_RD(x) (0x38 + (x >> 8)) /* Read data from MCR or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * Packet RAM sequentially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CMD_SPI_MEMR_WR(x) (0x08 + (x >> 8)) /* Write data to MCR or Packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * RAM as random block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CMD_SPI_MEMR_RD(x) (0x28 + (x >> 8)) /* Read data from MCR or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Packet RAM random block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CMD_SPI_PRAM_WR 0x1E /* Write data sequentially to current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * PRAM page selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CMD_SPI_PRAM_RD 0x3E /* Read data sequentially from current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * PRAM page selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CMD_RC_SLEEP 0xB1 /* Invoke transition of radio controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * into SLEEP state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CMD_RC_IDLE 0xB2 /* Invoke transition of radio controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * into IDLE state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CMD_RC_PHY_RDY 0xB3 /* Invoke transition of radio controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * into PHY_RDY state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CMD_RC_RX 0xB4 /* Invoke transition of radio controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * into RX state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CMD_RC_TX 0xB5 /* Invoke transition of radio controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * into TX state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CMD_RC_MEAS 0xB6 /* Invoke transition of radio controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * into MEAS state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CMD_RC_CCA 0xB7 /* Invoke Clear channel assessment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CMD_RC_CSMACA 0xC1 /* initiates CSMA-CA channel access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * sequence and frame transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CMD_RC_PC_RESET 0xC7 /* Program counter reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CMD_RC_RESET 0xC8 /* Resets the ADF7242 and puts it in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * the sleep state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CMD_RC_PC_RESET_NO_WAIT (CMD_RC_PC_RESET | BIT(31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define STAT_SPI_READY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define STAT_IRQ_STATUS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define STAT_RC_READY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define STAT_CCA_RESULT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define RC_STATUS_IDLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define RC_STATUS_MEAS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define RC_STATUS_PHY_RDY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define RC_STATUS_RX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define RC_STATUS_TX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define RC_STATUS_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* AUTO_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SUCCESS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SUCCESS_DATPEND 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define FAILURE_CSMACA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define FAILURE_NOACK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define AUTO_STATUS_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PRAM_PAGESIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IRQ_CCA_COMPLETE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IRQ_SFD_RX BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IRQ_SFD_TX BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IRQ_RX_PKT_RCVD BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IRQ_TX_PKT_SENT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IRQ_FRAME_VALID BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IRQ_ADDRESS_VALID BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IRQ_CSMA_CA BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define AUTO_TX_TURNAROUND BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define ADDON_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define FLAG_XMIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define FLAG_START 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define ADF7242_REPORT_CSMA_CA_STAT 0 /* framework doesn't handle yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct adf7242_local {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct completion tx_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct ieee802154_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct mutex bmux; /* protect SPI messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct spi_message stat_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct spi_transfer stat_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct dentry *debugfs_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct delayed_work work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct workqueue_struct *wqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int tx_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) bool promiscuous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) s8 rssi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u8 max_frame_retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u8 max_cca_retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u8 max_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u8 min_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u8 buf[3] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u8 buf_reg_tx[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u8 buf_read_tx[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u8 buf_read_rx[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u8 buf_stat_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u8 buf_stat_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u8 buf_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int adf7242_soft_reset(struct adf7242_local *lp, int line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int adf7242_status(struct adf7242_local *lp, u8 *stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) mutex_lock(&lp->bmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) status = spi_sync(lp->spi, &lp->stat_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) *stat = lp->buf_stat_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) mutex_unlock(&lp->bmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int adf7242_wait_status(struct adf7242_local *lp, unsigned int status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned int mask, int line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int cnt = 0, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u8 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) adf7242_status(lp, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) } while (((stat & mask) != status) && (cnt < MAX_POLL_LOOPS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (cnt >= MAX_POLL_LOOPS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (!(stat & STAT_RC_READY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) adf7242_soft_reset(lp, line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) adf7242_status(lp, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if ((stat & mask) == status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev_warn(&lp->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "%s:line %d Timeout status 0x%x (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) __func__, line, stat, cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_vdbg(&lp->spi->dev, "%s : loops=%d line %d\n", __func__, cnt, line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static int adf7242_wait_rc_ready(struct adf7242_local *lp, int line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return adf7242_wait_status(lp, STAT_RC_READY | STAT_SPI_READY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) STAT_RC_READY | STAT_SPI_READY, line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int adf7242_wait_spi_ready(struct adf7242_local *lp, int line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return adf7242_wait_status(lp, STAT_SPI_READY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) STAT_SPI_READY, line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int adf7242_write_fbuf(struct adf7242_local *lp, u8 *data, u8 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u8 *buf = lp->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct spi_transfer xfer_head = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .tx_buf = buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct spi_transfer xfer_buf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .len = len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .tx_buf = data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) spi_message_add_tail(&xfer_head, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) spi_message_add_tail(&xfer_buf, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) adf7242_wait_spi_ready(lp, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) mutex_lock(&lp->bmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) buf[0] = CMD_SPI_PKT_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) buf[1] = len + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) status = spi_sync(lp->spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) mutex_unlock(&lp->bmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int adf7242_read_fbuf(struct adf7242_local *lp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u8 *data, size_t len, bool packet_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u8 *buf = lp->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct spi_transfer xfer_head = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .tx_buf = buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .rx_buf = buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct spi_transfer xfer_buf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .len = len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .rx_buf = data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) spi_message_add_tail(&xfer_head, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) spi_message_add_tail(&xfer_buf, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) adf7242_wait_spi_ready(lp, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) mutex_lock(&lp->bmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (packet_read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) buf[0] = CMD_SPI_PKT_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) buf[1] = CMD_SPI_NOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) buf[2] = 0; /* PHR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) buf[0] = CMD_SPI_PRAM_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) buf[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) buf[2] = CMD_SPI_NOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) status = spi_sync(lp->spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) mutex_unlock(&lp->bmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int adf7242_read_reg(struct adf7242_local *lp, u16 addr, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct spi_transfer xfer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .len = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .tx_buf = lp->buf_read_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .rx_buf = lp->buf_read_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) adf7242_wait_spi_ready(lp, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) mutex_lock(&lp->bmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) lp->buf_read_tx[0] = CMD_SPI_MEM_RD(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) lp->buf_read_tx[1] = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) lp->buf_read_tx[2] = CMD_SPI_NOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) lp->buf_read_tx[3] = CMD_SPI_NOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) spi_message_add_tail(&xfer, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) status = spi_sync(lp->spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (msg.status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) status = msg.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) *data = lp->buf_read_rx[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) mutex_unlock(&lp->bmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev_vdbg(&lp->spi->dev, "%s : REG 0x%X, VAL 0x%X\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) addr, *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int adf7242_write_reg(struct adf7242_local *lp, u16 addr, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) adf7242_wait_spi_ready(lp, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) mutex_lock(&lp->bmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) lp->buf_reg_tx[0] = CMD_SPI_MEM_WR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) lp->buf_reg_tx[1] = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) lp->buf_reg_tx[2] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) status = spi_write(lp->spi, lp->buf_reg_tx, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) mutex_unlock(&lp->bmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_vdbg(&lp->spi->dev, "%s : REG 0x%X, VAL 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) __func__, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int adf7242_cmd(struct adf7242_local *lp, unsigned int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev_vdbg(&lp->spi->dev, "%s : CMD=0x%X\n", __func__, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (cmd != CMD_RC_PC_RESET_NO_WAIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) adf7242_wait_rc_ready(lp, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) mutex_lock(&lp->bmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) lp->buf_cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) status = spi_write(lp->spi, &lp->buf_cmd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) mutex_unlock(&lp->bmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static int adf7242_upload_firmware(struct adf7242_local *lp, u8 *data, u16 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct spi_transfer xfer_buf = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int status, i, page = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u8 *buf = lp->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct spi_transfer xfer_head = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .tx_buf = buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) buf[0] = CMD_SPI_PRAM_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) buf[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) spi_message_add_tail(&xfer_head, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) spi_message_add_tail(&xfer_buf, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) for (i = len; i >= 0; i -= PRAM_PAGESIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) adf7242_write_reg(lp, REG_PRAMPG, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) xfer_buf.len = (i >= PRAM_PAGESIZE) ? PRAM_PAGESIZE : i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) xfer_buf.tx_buf = &data[page * PRAM_PAGESIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) mutex_lock(&lp->bmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) status = spi_sync(lp->spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mutex_unlock(&lp->bmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) page++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int adf7242_verify_firmware(struct adf7242_local *lp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) const u8 *data, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) unsigned int page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u8 *buf = kmalloc(PRAM_PAGESIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) for (page = 0, i = len; i >= 0; i -= PRAM_PAGESIZE, page++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) size_t nb = (i >= PRAM_PAGESIZE) ? PRAM_PAGESIZE : i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) adf7242_write_reg(lp, REG_PRAMPG, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) adf7242_read_fbuf(lp, buf, nb, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) for (j = 0; j < nb; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (buf[j] != data[page * PRAM_PAGESIZE + j]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static void adf7242_clear_irqstat(struct adf7242_local *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) adf7242_write_reg(lp, REG_IRQ1_SRC1, IRQ_CCA_COMPLETE | IRQ_SFD_RX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) IRQ_SFD_TX | IRQ_RX_PKT_RCVD | IRQ_TX_PKT_SENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) IRQ_FRAME_VALID | IRQ_ADDRESS_VALID | IRQ_CSMA_CA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static int adf7242_cmd_rx(struct adf7242_local *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Wait until the ACK is sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) adf7242_wait_status(lp, RC_STATUS_PHY_RDY, RC_STATUS_MASK, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) adf7242_clear_irqstat(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) mod_delayed_work(lp->wqueue, &lp->work, msecs_to_jiffies(400));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return adf7242_cmd(lp, CMD_RC_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static void adf7242_rx_cal_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct adf7242_local *lp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) container_of(work, struct adf7242_local, work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* Reissuing RC_RX every 400ms - to adjust for offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * drift in receiver (datasheet page 61, OCL section)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (!test_bit(FLAG_XMIT, &lp->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) adf7242_cmd(lp, CMD_RC_PHY_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) adf7242_cmd_rx(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static int adf7242_set_txpower(struct ieee802154_hw *hw, int mbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct adf7242_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u8 pwr, bias_ctrl, dbias, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int db = mbm / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) dev_vdbg(&lp->spi->dev, "%s : Power %d dB\n", __func__, db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (db > 5 || db < -26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) db = DIV_ROUND_CLOSEST(db + 29, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (db > 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dbias = PA_DBIAS_HIGH_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) bias_ctrl = PA_BIAS_HIGH_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dbias = PA_DBIAS_LOW_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) bias_ctrl = PA_BIAS_LOW_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) pwr = clamp_t(u8, db, 3, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) adf7242_read_reg(lp, REG_PA_CFG, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) tmp &= ~PA_BRIDGE_DBIAS(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) tmp |= PA_BRIDGE_DBIAS(dbias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) adf7242_write_reg(lp, REG_PA_CFG, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) adf7242_read_reg(lp, REG_PA_BIAS, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) tmp &= ~PA_BIAS_CTRL(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) tmp |= PA_BIAS_CTRL(bias_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) adf7242_write_reg(lp, REG_PA_BIAS, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) adf7242_read_reg(lp, REG_EXTPA_MSC, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) tmp &= ~PA_PWR(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) tmp |= PA_PWR(pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return adf7242_write_reg(lp, REG_EXTPA_MSC, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static int adf7242_set_csma_params(struct ieee802154_hw *hw, u8 min_be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u8 max_be, u8 retries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct adf7242_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) dev_vdbg(&lp->spi->dev, "%s : min_be=%d max_be=%d retries=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) __func__, min_be, max_be, retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (min_be > max_be || max_be > 8 || retries > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ret = adf7242_write_reg(lp, REG_AUTO_TX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) MAX_FRAME_RETRIES(lp->max_frame_retries) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) MAX_CCA_RETRIES(retries));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) lp->max_cca_retries = retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) lp->max_be = max_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) lp->min_be = min_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return adf7242_write_reg(lp, REG_AUTO_TX2, CSMA_MAX_BE(max_be) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) CSMA_MIN_BE(min_be));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static int adf7242_set_frame_retries(struct ieee802154_hw *hw, s8 retries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct adf7242_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) dev_vdbg(&lp->spi->dev, "%s : Retries = %d\n", __func__, retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (retries < -1 || retries > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (retries >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ret = adf7242_write_reg(lp, REG_AUTO_TX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) MAX_FRAME_RETRIES(retries) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) MAX_CCA_RETRIES(lp->max_cca_retries));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) lp->max_frame_retries = retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static int adf7242_ed(struct ieee802154_hw *hw, u8 *level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct adf7242_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) *level = lp->rssi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) dev_vdbg(&lp->spi->dev, "%s :Exit level=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) __func__, *level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static int adf7242_start(struct ieee802154_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct adf7242_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) adf7242_cmd(lp, CMD_RC_PHY_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) adf7242_clear_irqstat(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) enable_irq(lp->spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) set_bit(FLAG_START, &lp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return adf7242_cmd_rx(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static void adf7242_stop(struct ieee802154_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct adf7242_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) disable_irq(lp->spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) cancel_delayed_work_sync(&lp->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) adf7242_cmd(lp, CMD_RC_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) clear_bit(FLAG_START, &lp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) adf7242_clear_irqstat(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static int adf7242_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct adf7242_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dev_dbg(&lp->spi->dev, "%s :Channel=%d\n", __func__, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) might_sleep();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) WARN_ON(page != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) WARN_ON(channel < 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) WARN_ON(channel > 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) freq = (2405 + 5 * (channel - 11)) * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) adf7242_cmd(lp, CMD_RC_PHY_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) adf7242_write_reg(lp, REG_CH_FREQ0, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) adf7242_write_reg(lp, REG_CH_FREQ1, freq >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) adf7242_write_reg(lp, REG_CH_FREQ2, freq >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (test_bit(FLAG_START, &lp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return adf7242_cmd_rx(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return adf7242_cmd(lp, CMD_RC_PHY_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static int adf7242_set_hw_addr_filt(struct ieee802154_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct ieee802154_hw_addr_filt *filt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) unsigned long changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct adf7242_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) dev_dbg(&lp->spi->dev, "%s :Changed=0x%lX\n", __func__, changed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) might_sleep();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u8 addr[8], i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) memcpy(addr, &filt->ieee_addr, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) adf7242_write_reg(lp, REG_IEEE_ADDR_0 + i, addr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) u16 saddr = le16_to_cpu(filt->short_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) adf7242_write_reg(lp, REG_SHORT_ADDR_0, saddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) adf7242_write_reg(lp, REG_SHORT_ADDR_1, saddr >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (changed & IEEE802154_AFILT_PANID_CHANGED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u16 pan_id = le16_to_cpu(filt->pan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) adf7242_write_reg(lp, REG_PAN_ID0, pan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) adf7242_write_reg(lp, REG_PAN_ID1, pan_id >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (changed & IEEE802154_AFILT_PANC_CHANGED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) adf7242_read_reg(lp, REG_AUTO_CFG, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (filt->pan_coord)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) reg |= IS_PANCOORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) reg &= ~IS_PANCOORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) adf7242_write_reg(lp, REG_AUTO_CFG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static int adf7242_set_promiscuous_mode(struct ieee802154_hw *hw, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct adf7242_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dev_dbg(&lp->spi->dev, "%s : mode %d\n", __func__, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) lp->promiscuous = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) adf7242_write_reg(lp, REG_AUTO_CFG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return adf7242_write_reg(lp, REG_FFILT_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ACCEPT_BEACON_FRAMES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ACCEPT_DATA_FRAMES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ACCEPT_MACCMD_FRAMES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ACCEPT_ALL_ADDRESS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ACCEPT_ACK_FRAMES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ACCEPT_RESERVED_FRAMES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) adf7242_write_reg(lp, REG_FFILT_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ACCEPT_BEACON_FRAMES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ACCEPT_DATA_FRAMES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ACCEPT_MACCMD_FRAMES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ACCEPT_RESERVED_FRAMES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return adf7242_write_reg(lp, REG_AUTO_CFG, RX_AUTO_ACK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static int adf7242_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct adf7242_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) s8 level = clamp_t(s8, mbm / 100, S8_MIN, S8_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) dev_dbg(&lp->spi->dev, "%s : level %d\n", __func__, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return adf7242_write_reg(lp, REG_CCA1, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static int adf7242_xmit(struct ieee802154_hw *hw, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct adf7242_local *lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* ensure existing instances of the IRQ handler have completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) disable_irq(lp->spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) set_bit(FLAG_XMIT, &lp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) cancel_delayed_work_sync(&lp->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) reinit_completion(&lp->tx_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) adf7242_cmd(lp, CMD_RC_PHY_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) adf7242_clear_irqstat(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ret = adf7242_write_fbuf(lp, skb->data, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ret = adf7242_cmd(lp, CMD_RC_CSMACA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) enable_irq(lp->spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ret = wait_for_completion_interruptible_timeout(&lp->tx_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) HZ / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) dev_dbg(&lp->spi->dev, "Timeout waiting for TX interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (lp->tx_stat != SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) dev_dbg(&lp->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) "Error xmit: Retry count exceeded Status=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) lp->tx_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ret = -ECOMM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) clear_bit(FLAG_XMIT, &lp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) adf7242_cmd_rx(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static int adf7242_rx(struct adf7242_local *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) u8 lqi, len_u8, *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ret = adf7242_read_reg(lp, 0, &len_u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) len = len_u8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (!ieee802154_is_valid_psdu_len(len)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dev_dbg(&lp->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) "corrupted frame received len %d\n", (int)len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) len = IEEE802154_MTU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) skb = dev_alloc_skb(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) adf7242_cmd_rx(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) data = skb_put(skb, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ret = adf7242_read_fbuf(lp, data, len, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) adf7242_cmd_rx(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) lqi = data[len - 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) lp->rssi = data[len - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ret = adf7242_cmd_rx(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) skb_trim(skb, len - 2); /* Don't put RSSI/LQI or CRC into the frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) ieee802154_rx_irqsafe(lp->hw, skb, lqi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) dev_dbg(&lp->spi->dev, "%s: ret=%d len=%d lqi=%d rssi=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) __func__, ret, (int)len, (int)lqi, lp->rssi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static const struct ieee802154_ops adf7242_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .xmit_sync = adf7242_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .ed = adf7242_ed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .set_channel = adf7242_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .set_hw_addr_filt = adf7242_set_hw_addr_filt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .start = adf7242_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .stop = adf7242_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .set_csma_params = adf7242_set_csma_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .set_frame_retries = adf7242_set_frame_retries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .set_txpower = adf7242_set_txpower,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .set_promiscuous_mode = adf7242_set_promiscuous_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .set_cca_ed_level = adf7242_set_cca_ed_level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static void adf7242_debug(struct adf7242_local *lp, u8 irq1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) u8 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) adf7242_status(lp, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) dev_dbg(&lp->spi->dev, "%s IRQ1 = %X:\n%s%s%s%s%s%s%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) __func__, irq1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) irq1 & IRQ_CCA_COMPLETE ? "IRQ_CCA_COMPLETE\n" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) irq1 & IRQ_SFD_RX ? "IRQ_SFD_RX\n" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) irq1 & IRQ_SFD_TX ? "IRQ_SFD_TX\n" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) irq1 & IRQ_RX_PKT_RCVD ? "IRQ_RX_PKT_RCVD\n" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) irq1 & IRQ_TX_PKT_SENT ? "IRQ_TX_PKT_SENT\n" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) irq1 & IRQ_CSMA_CA ? "IRQ_CSMA_CA\n" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) irq1 & IRQ_FRAME_VALID ? "IRQ_FRAME_VALID\n" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) irq1 & IRQ_ADDRESS_VALID ? "IRQ_ADDRESS_VALID\n" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) dev_dbg(&lp->spi->dev, "%s STATUS = %X:\n%s\n%s\n%s\n%s\n%s%s%s%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) __func__, stat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) stat & STAT_SPI_READY ? "SPI_READY" : "SPI_BUSY",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) stat & STAT_IRQ_STATUS ? "IRQ_PENDING" : "IRQ_CLEAR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) stat & STAT_RC_READY ? "RC_READY" : "RC_BUSY",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) stat & STAT_CCA_RESULT ? "CHAN_IDLE" : "CHAN_BUSY",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) (stat & 0xf) == RC_STATUS_IDLE ? "RC_STATUS_IDLE" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) (stat & 0xf) == RC_STATUS_MEAS ? "RC_STATUS_MEAS" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) (stat & 0xf) == RC_STATUS_PHY_RDY ? "RC_STATUS_PHY_RDY" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) (stat & 0xf) == RC_STATUS_RX ? "RC_STATUS_RX" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) (stat & 0xf) == RC_STATUS_TX ? "RC_STATUS_TX" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static irqreturn_t adf7242_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct adf7242_local *lp = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) unsigned int xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) u8 irq1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) mod_delayed_work(lp->wqueue, &lp->work, msecs_to_jiffies(400));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) adf7242_read_reg(lp, REG_IRQ1_SRC1, &irq1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (!(irq1 & (IRQ_RX_PKT_RCVD | IRQ_CSMA_CA)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) dev_err(&lp->spi->dev, "%s :ERROR IRQ1 = 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) __func__, irq1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) adf7242_debug(lp, irq1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) xmit = test_bit(FLAG_XMIT, &lp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (xmit && (irq1 & IRQ_CSMA_CA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) adf7242_wait_status(lp, RC_STATUS_PHY_RDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) RC_STATUS_MASK, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (ADF7242_REPORT_CSMA_CA_STAT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) u8 astat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) adf7242_read_reg(lp, REG_AUTO_STATUS, &astat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) astat &= AUTO_STATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) dev_dbg(&lp->spi->dev, "AUTO_STATUS = %X:\n%s%s%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) astat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) astat == SUCCESS ? "SUCCESS" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) astat ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) SUCCESS_DATPEND ? "SUCCESS_DATPEND" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) astat == FAILURE_CSMACA ? "FAILURE_CSMACA" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) astat == FAILURE_NOACK ? "FAILURE_NOACK" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* save CSMA-CA completion status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) lp->tx_stat = astat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) lp->tx_stat = SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) complete(&lp->tx_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) adf7242_clear_irqstat(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) } else if (!xmit && (irq1 & IRQ_RX_PKT_RCVD) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) (irq1 & IRQ_FRAME_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) adf7242_rx(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) } else if (!xmit && test_bit(FLAG_START, &lp->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /* Invalid packet received - drop it and restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) dev_dbg(&lp->spi->dev, "%s:%d : ERROR IRQ1 = 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) __func__, __LINE__, irq1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) adf7242_cmd(lp, CMD_RC_PHY_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) adf7242_cmd_rx(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /* This can only be xmit without IRQ, likely a RX packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) * we get an TX IRQ shortly - do nothing or let the xmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * timeout handle this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) dev_dbg(&lp->spi->dev, "%s:%d : ERROR IRQ1 = 0x%X, xmit %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) __func__, __LINE__, irq1, xmit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) adf7242_wait_status(lp, RC_STATUS_PHY_RDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) RC_STATUS_MASK, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) complete(&lp->tx_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) adf7242_clear_irqstat(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static int adf7242_soft_reset(struct adf7242_local *lp, int line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) dev_warn(&lp->spi->dev, "%s (line %d)\n", __func__, line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (test_bit(FLAG_START, &lp->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) disable_irq_nosync(lp->spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) adf7242_cmd(lp, CMD_RC_PC_RESET_NO_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) usleep_range(200, 250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) adf7242_write_reg(lp, REG_PKT_CFG, ADDON_EN | BIT(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) adf7242_cmd(lp, CMD_RC_PHY_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) adf7242_set_promiscuous_mode(lp->hw, lp->promiscuous);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) adf7242_set_csma_params(lp->hw, lp->min_be, lp->max_be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) lp->max_cca_retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) adf7242_clear_irqstat(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if (test_bit(FLAG_START, &lp->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) enable_irq(lp->spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return adf7242_cmd(lp, CMD_RC_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static int adf7242_hw_init(struct adf7242_local *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) adf7242_cmd(lp, CMD_RC_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) adf7242_cmd(lp, CMD_RC_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /* get ADF7242 addon firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * build this driver as module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * and place under /lib/firmware/adf7242_firmware.bin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * or compile firmware into the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) ret = request_firmware(&fw, FIRMWARE, &lp->spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) dev_err(&lp->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) "request_firmware() failed with %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ret = adf7242_upload_firmware(lp, (u8 *)fw->data, fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) dev_err(&lp->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) "upload firmware failed with %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ret = adf7242_verify_firmware(lp, (u8 *)fw->data, fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) dev_err(&lp->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) "verify firmware failed with %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) adf7242_cmd(lp, CMD_RC_PC_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) adf7242_write_reg(lp, REG_FFILT_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) ACCEPT_BEACON_FRAMES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ACCEPT_DATA_FRAMES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) ACCEPT_MACCMD_FRAMES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ACCEPT_RESERVED_FRAMES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) adf7242_write_reg(lp, REG_AUTO_CFG, RX_AUTO_ACK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) adf7242_write_reg(lp, REG_PKT_CFG, ADDON_EN | BIT(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) adf7242_write_reg(lp, REG_EXTPA_MSC, 0xF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) adf7242_write_reg(lp, REG_RXFE_CFG, 0x1D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) adf7242_write_reg(lp, REG_IRQ1_EN0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) adf7242_write_reg(lp, REG_IRQ1_EN1, IRQ_RX_PKT_RCVD | IRQ_CSMA_CA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) adf7242_clear_irqstat(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) adf7242_write_reg(lp, REG_IRQ1_SRC0, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) adf7242_cmd(lp, CMD_RC_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static int adf7242_stats_show(struct seq_file *file, void *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) struct adf7242_local *lp = spi_get_drvdata(file->private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) u8 stat, irq1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) adf7242_status(lp, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) adf7242_read_reg(lp, REG_IRQ1_SRC1, &irq1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) seq_printf(file, "IRQ1 = %X:\n%s%s%s%s%s%s%s%s\n", irq1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) irq1 & IRQ_CCA_COMPLETE ? "IRQ_CCA_COMPLETE\n" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) irq1 & IRQ_SFD_RX ? "IRQ_SFD_RX\n" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) irq1 & IRQ_SFD_TX ? "IRQ_SFD_TX\n" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) irq1 & IRQ_RX_PKT_RCVD ? "IRQ_RX_PKT_RCVD\n" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) irq1 & IRQ_TX_PKT_SENT ? "IRQ_TX_PKT_SENT\n" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) irq1 & IRQ_CSMA_CA ? "IRQ_CSMA_CA\n" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) irq1 & IRQ_FRAME_VALID ? "IRQ_FRAME_VALID\n" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) irq1 & IRQ_ADDRESS_VALID ? "IRQ_ADDRESS_VALID\n" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) seq_printf(file, "STATUS = %X:\n%s\n%s\n%s\n%s\n%s%s%s%s%s\n", stat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) stat & STAT_SPI_READY ? "SPI_READY" : "SPI_BUSY",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) stat & STAT_IRQ_STATUS ? "IRQ_PENDING" : "IRQ_CLEAR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) stat & STAT_RC_READY ? "RC_READY" : "RC_BUSY",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) stat & STAT_CCA_RESULT ? "CHAN_IDLE" : "CHAN_BUSY",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) (stat & 0xf) == RC_STATUS_IDLE ? "RC_STATUS_IDLE" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) (stat & 0xf) == RC_STATUS_MEAS ? "RC_STATUS_MEAS" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) (stat & 0xf) == RC_STATUS_PHY_RDY ? "RC_STATUS_PHY_RDY" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) (stat & 0xf) == RC_STATUS_RX ? "RC_STATUS_RX" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) (stat & 0xf) == RC_STATUS_TX ? "RC_STATUS_TX" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) seq_printf(file, "RSSI = %d\n", lp->rssi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static void adf7242_debugfs_init(struct adf7242_local *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) char debugfs_dir_name[DNAME_INLINE_LEN + 1] = "adf7242-";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) strncat(debugfs_dir_name, dev_name(&lp->spi->dev), DNAME_INLINE_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) lp->debugfs_root = debugfs_create_dir(debugfs_dir_name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) debugfs_create_devm_seqfile(&lp->spi->dev, "status", lp->debugfs_root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) adf7242_stats_show);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static const s32 adf7242_powers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) 500, 400, 300, 200, 100, 0, -100, -200, -300, -400, -500, -600, -700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) -800, -900, -1000, -1100, -1200, -1300, -1400, -1500, -1600, -1700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) -1800, -1900, -2000, -2100, -2200, -2300, -2400, -2500, -2600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static const s32 adf7242_ed_levels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) -9000, -8900, -8800, -8700, -8600, -8500, -8400, -8300, -8200, -8100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) -8000, -7900, -7800, -7700, -7600, -7500, -7400, -7300, -7200, -7100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) -7000, -6900, -6800, -6700, -6600, -6500, -6400, -6300, -6200, -6100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) -6000, -5900, -5800, -5700, -5600, -5500, -5400, -5300, -5200, -5100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) -5000, -4900, -4800, -4700, -4600, -4500, -4400, -4300, -4200, -4100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) -4000, -3900, -3800, -3700, -3600, -3500, -3400, -3200, -3100, -3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) static int adf7242_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct ieee802154_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) struct adf7242_local *lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) int ret, irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (!spi->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) dev_err(&spi->dev, "no IRQ specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) hw = ieee802154_alloc_hw(sizeof(*lp), &adf7242_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) lp = hw->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) lp->hw = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) lp->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) hw->priv = lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) hw->parent = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) hw->extra_tx_headroom = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /* We support only 2.4 Ghz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) hw->phy->supported.channels[0] = 0x7FFF800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) hw->flags = IEEE802154_HW_OMIT_CKSUM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) IEEE802154_HW_CSMA_PARAMS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) IEEE802154_HW_FRAME_RETRIES | IEEE802154_HW_AFILT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) IEEE802154_HW_PROMISCUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) hw->phy->flags = WPAN_PHY_FLAG_TXPOWER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) WPAN_PHY_FLAG_CCA_ED_LEVEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) WPAN_PHY_FLAG_CCA_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) hw->phy->supported.cca_ed_levels = adf7242_ed_levels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(adf7242_ed_levels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) hw->phy->cca.mode = NL802154_CCA_ENERGY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) hw->phy->supported.tx_powers = adf7242_powers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) hw->phy->supported.tx_powers_size = ARRAY_SIZE(adf7242_powers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) hw->phy->supported.min_minbe = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) hw->phy->supported.max_minbe = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) hw->phy->supported.min_maxbe = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) hw->phy->supported.max_maxbe = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) hw->phy->supported.min_frame_retries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) hw->phy->supported.max_frame_retries = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) hw->phy->supported.min_csma_backoffs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) hw->phy->supported.max_csma_backoffs = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ieee802154_random_extended_addr(&hw->phy->perm_extended_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) mutex_init(&lp->bmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) init_completion(&lp->tx_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /* Setup Status Message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) lp->stat_xfer.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) lp->stat_xfer.tx_buf = &lp->buf_stat_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) lp->stat_xfer.rx_buf = &lp->buf_stat_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) lp->buf_stat_tx = CMD_SPI_NOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) spi_message_init(&lp->stat_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) spi_message_add_tail(&lp->stat_xfer, &lp->stat_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) spi_set_drvdata(spi, lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) INIT_DELAYED_WORK(&lp->work, adf7242_rx_cal_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) lp->wqueue = alloc_ordered_workqueue(dev_name(&spi->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) WQ_MEM_RECLAIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (unlikely(!lp->wqueue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) goto err_alloc_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) ret = adf7242_hw_init(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) goto err_hw_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) irq_type = irq_get_trigger_type(spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (!irq_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) irq_type = IRQF_TRIGGER_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL, adf7242_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) irq_type | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) dev_name(&spi->dev), lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) goto err_hw_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) disable_irq(spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) ret = ieee802154_register_hw(lp->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) goto err_hw_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dev_set_drvdata(&spi->dev, lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) adf7242_debugfs_init(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) dev_info(&spi->dev, "mac802154 IRQ-%d registered\n", spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) err_hw_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) destroy_workqueue(lp->wqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) err_alloc_wq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) mutex_destroy(&lp->bmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ieee802154_free_hw(lp->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static int adf7242_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct adf7242_local *lp = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) debugfs_remove_recursive(lp->debugfs_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) cancel_delayed_work_sync(&lp->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) destroy_workqueue(lp->wqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) ieee802154_unregister_hw(lp->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) mutex_destroy(&lp->bmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) ieee802154_free_hw(lp->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static const struct of_device_id adf7242_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) { .compatible = "adi,adf7242", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) { .compatible = "adi,adf7241", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) MODULE_DEVICE_TABLE(of, adf7242_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) static const struct spi_device_id adf7242_device_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) { .name = "adf7242", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) { .name = "adf7241", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) MODULE_DEVICE_TABLE(spi, adf7242_device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static struct spi_driver adf7242_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .id_table = adf7242_device_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .of_match_table = of_match_ptr(adf7242_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .name = "adf7242",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .probe = adf7242_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .remove = adf7242_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) module_spi_driver(adf7242_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) MODULE_DESCRIPTION("ADF7242 IEEE802.15.4 Transceiver Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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