^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _RRUNNER_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _RRUNNER_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #if ((BITS_PER_LONG != 32) && (BITS_PER_LONG != 64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #error "BITS_PER_LONG not defined or not valid"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct rr_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) u32 pad0[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u32 HostCtrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u32 LocalCtrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u32 Pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u32 BrkPt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Timer increments every 0.97 micro-seconds (unsigned int) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 Timer_Hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 Timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 TimerRef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 PciState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 Event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 MbEvent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 WinBase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 WinData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 RX_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 TX_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 Overhead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 ExtIo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 DmaWriteHostHi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 DmaWriteHostLo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 pad1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 DmaReadHostHi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 DmaReadHostLo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 DmaReadLen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 DmaWriteState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 DmaWriteLcl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 DmaWriteIPchecksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 DmaWriteLen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 DmaReadState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 DmaReadLcl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 DmaReadIPchecksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 pad3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 RxBase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 RxPrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 RxCon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 pad4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 TxBase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 TxPrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 TxCon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 pad5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 RxIndPro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 RxIndCon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 RxIndRef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 pad6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 TxIndPro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 TxIndCon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 TxIndRef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 pad7[17];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 DrCmndPro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 DrCmndCon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 DrCmndRef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 pad8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 DwCmndPro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 DwCmndCon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 DwCmndRef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 AssistState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 DrDataPro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 DrDataCon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 DrDataRef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 pad9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 DwDataPro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 DwDataCon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 DwDataRef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 pad10[33];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 EvtCon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 pad11[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 TxPi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 IpRxPi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 pad11a[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 CmdRing[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* The ULA is in two registers the high order two bytes of the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * word contain the RunCode features.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * ula0 res res byte0 byte1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * ula1 byte2 byte3 byte4 byte5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 Ula0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 Ula1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 RxRingHi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 RxRingLo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 InfoPtrHi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 InfoPtrLo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 Mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 ConRetry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 ConRetryTmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 ConTmout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 CtatTmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 MaxRxRng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 IntrTmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 TxDataMvTimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 RxDataMvTimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 EvtPrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 TraceIdx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 Fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 Fail2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 DrvPrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 FilterLA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 FwRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 FwRes1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 FwRes2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 FwRes3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 WriteDmaThresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 ReadDmaThresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 pad12[325];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 Window[512];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Host control register bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define RR_INT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define RR_CLEAR_INT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define NO_SWAP 0x04000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define NO_SWAP1 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PCI_RESET_NIC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define HALT_NIC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SSTEP_NIC 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MEM_READ_MULTI 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define NIC_HALTED 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define HALT_INST 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PARITY_ERR 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define INVALID_INST_B 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define RR_REV_2 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define RR_REV_MASK 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Local control register bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define INTA_STATE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CLEAR_INTA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define FAST_EEPROM_ACCESS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ENABLE_EXTRA_SRAM 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ENABLE_EXTRA_DESC 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define ENABLE_PARITY 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define FORCE_DMA_PARITY_ERROR 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define ENABLE_EEPROM_WRITE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ENABLE_DATA_CACHE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SRAM_LO_PARITY_ERR 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SRAM_HI_PARITY_ERR 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * PCI state bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define FORCE_PCI_RESET 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PROVIDE_LENGTH 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MASK_DMA_READ_MAX 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define RBURST_DISABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define RBURST_4 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define RBURST_16 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define RBURST_32 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define RBURST_64 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define RBURST_128 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define RBURST_256 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define RBURST_1024 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MASK_DMA_WRITE_MAX 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define WBURST_DISABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define WBURST_4 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define WBURST_16 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define WBURST_32 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define WBURST_64 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define WBURST_128 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define WBURST_256 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define WBURST_1024 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MASK_MIN_DMA 0xFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define FIFO_RETRY_ENABLE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Event register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define DMA_WRITE_DONE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define DMA_READ_DONE 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define DMA_WRITE_ERR 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DMA_READ_ERR 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Receive state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * RoadRunner HIPPI Receive State Register controls and monitors the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * HIPPI receive interface in the NIC. Look at err bits when a HIPPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * receive Error Event occurs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define ENABLE_NEW_CON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define RESET_RECV 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define RECV_ALL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define RECV_1K 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define RECV_2K 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define RECV_4K 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define RECV_8K 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define RECV_16K 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define RECV_32K 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define RECV_64K 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * Transmit status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define ENA_XMIT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define PERM_CON 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * DMA write state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define RESET_DMA 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define NO_SWAP_DMA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define DMA_ACTIVE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define THRESH_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DMA_ERROR_MASK 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * Gooddies stored in the ULA registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define TRACE_ON_WHAT_BIT 0x00020000 /* Traces on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ONEM_BUF_WHAT_BIT 0x00040000 /* 1Meg vs 256K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CHAR_API_WHAT_BIT 0x00080000 /* Char API vs network only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CMD_EVT_WHAT_BIT 0x00200000 /* Command event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define LONG_TX_WHAT_BIT 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define LONG_RX_WHAT_BIT 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define WHAT_BIT_MASK 0xFFFD0000 /* Feature bit mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * Mode status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define EVENT_OVFL 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define FATAL_ERR 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define LOOP_BACK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define MODE_PH 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define MODE_FP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define PTR64BIT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define PTR32BIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define PTR_WD_SWAP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define PTR_WD_NOSWAP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define POST_WARN_EVENT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define ERR_TERM 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DIRECT_CONN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define NO_NIC_WATCHDOG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SWAP_DATA 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SWAP_CONTROL 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define NIC_HALT_ON_ERR 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define NIC_NO_RESTART 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define HALF_DUP_TX 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define HALF_DUP_RX 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * Error codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Host Error Codes - values of fail1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define ERR_UNKNOWN_MBOX 0x1001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define ERR_UNKNOWN_CMD 0x1002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define ERR_MAX_RING 0x1003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define ERR_RING_CLOSED 0x1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define ERR_RING_OPEN 0x1005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Firmware internal errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define ERR_EVENT_RING_FULL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define ERR_DW_PEND_CMND_FULL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define ERR_DR_PEND_CMND_FULL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define ERR_DW_PEND_DATA_FULL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define ERR_DR_PEND_DATA_FULL 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define ERR_ILLEGAL_JUMP 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define ERR_UNIMPLEMENTED 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define ERR_TX_INFO_FULL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define ERR_RX_INFO_FULL 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define ERR_ILLEGAL_MODE 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define ERR_MAIN_TIMEOUT 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define ERR_EVENT_BITS 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define ERR_UNPEND_FULL 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define ERR_TIMER_QUEUE_FULL 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define ERR_TIMER_QUEUE_EMPTY 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define ERR_TIMER_NO_FREE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define ERR_INTR_START 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define ERR_BAD_STARTUP 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define ERR_NO_PKT_END 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define ERR_HALTED_ON_ERR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* Hardware NIC Errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define ERR_WRITE_DMA 0x0101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define ERR_READ_DMA 0x0102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define ERR_EXT_SERIAL 0x0103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define ERR_TX_INT_PARITY 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * Event definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define EVT_RING_ENTRIES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define EVT_RING_SIZE (EVT_RING_ENTRIES * sizeof(struct event))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u16 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u8 ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u8 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u8 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u8 ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u16 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * General Events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define E_NIC_UP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define E_WATCHDOG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define E_STAT_UPD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define E_INVAL_CMD 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define E_SET_CMD_CONS 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define E_LINK_ON 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define E_LINK_OFF 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define E_INTERN_ERR 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define E_HOST_ERR 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define E_STATS_UPDATE 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define E_REJECTING 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Send Events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define E_CON_REJ 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define E_CON_TMOUT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define E_CON_NC_TMOUT 0x15 /* I , Connection No Campon Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define E_DISC_ERR 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define E_INT_PRTY 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define E_TX_IDLE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define E_TX_LINK_DROP 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define E_TX_INV_RNG 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define E_TX_INV_BUF 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define E_TX_INV_DSC 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * Destination Events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * General Receive events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define E_VAL_RNG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define E_RX_RNG_ENER 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define E_INV_RNG 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define E_RX_RNG_SPC 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define E_RX_RNG_OUT 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define E_PKT_DISCARD 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define E_INFO_EVT 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * Data corrupted events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define E_RX_PAR_ERR 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define E_RX_LLRC_ERR 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define E_IP_CKSM_ERR 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define E_DTA_CKSM_ERR 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define E_SHT_BST 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * Data lost events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define E_LST_LNK_ERR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define E_FLG_SYN_ERR 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define E_FRM_ERR 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define E_RX_IDLE 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define E_PKT_LN_ERR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define E_STATE_ERR 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define E_UNEXP_DATA 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * Fatal events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define E_RX_INV_BUF 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define E_RX_INV_DSC 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define E_RNG_BLK 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * Warning events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define E_RX_TO 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define E_BFR_SPC 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define E_INV_ULP 0x3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define E_NOT_IMPLEMENTED 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * Commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define CMD_RING_ENTRIES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u16 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u8 ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u8 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u8 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u8 ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u16 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define C_START_FW 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define C_UPD_STAT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define C_WATCHDOG 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define C_DEL_RNG 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define C_NEW_RNG 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define C_CONN 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * Mode bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define PACKET_BAD 0x01 /* Packet had link-layer error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define INTERRUPT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define TX_IP_CKSUM 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define PACKET_END 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define PACKET_START 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define SAME_IFIELD 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #if (BITS_PER_LONG == 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u64 addrlo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u32 addrhi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u32 addrlo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } rraddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static inline void set_rraddr(rraddr *ra, dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned long baddr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #if (BITS_PER_LONG == 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ra->addrlo = baddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Don't bother setting zero every time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ra->addrlo = baddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static inline void set_rxaddr(struct rr_regs __iomem *regs, volatile dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) unsigned long baddr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #if (BITS_PER_LONG == 64) && defined(__LITTLE_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) writel(baddr & 0xffffffff, ®s->RxRingHi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) writel(baddr >> 32, ®s->RxRingLo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #elif (BITS_PER_LONG == 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) writel(baddr >> 32, ®s->RxRingHi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) writel(baddr & 0xffffffff, ®s->RxRingLo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) writel(0, ®s->RxRingHi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) writel(baddr, ®s->RxRingLo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static inline void set_infoaddr(struct rr_regs __iomem *regs, volatile dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) unsigned long baddr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #if (BITS_PER_LONG == 64) && defined(__LITTLE_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) writel(baddr & 0xffffffff, ®s->InfoPtrHi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) writel(baddr >> 32, ®s->InfoPtrLo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #elif (BITS_PER_LONG == 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) writel(baddr >> 32, ®s->InfoPtrHi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) writel(baddr & 0xffffffff, ®s->InfoPtrLo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) writel(0, ®s->InfoPtrHi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) writel(baddr, ®s->InfoPtrLo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * TX ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #ifdef CONFIG_ROADRUNNER_LARGE_RINGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define TX_RING_ENTRIES 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define TX_RING_ENTRIES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define TX_TOTAL_SIZE (TX_RING_ENTRIES * sizeof(struct tx_desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct tx_desc{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) rraddr addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u32 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u8 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u8 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #ifdef CONFIG_ROADRUNNER_LARGE_RINGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define RX_RING_ENTRIES 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define RX_RING_ENTRIES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define RX_TOTAL_SIZE (RX_RING_ENTRIES * sizeof(struct rx_desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct rx_desc{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) rraddr addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u32 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u8 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u8 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * ioctl's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define SIOCRRPFW SIOCDEVPRIVATE /* put firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define SIOCRRGFW SIOCDEVPRIVATE+1 /* get firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define SIOCRRID SIOCDEVPRIVATE+2 /* identify */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct seg_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u32 seg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u32 seg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u32 seg_eestart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define EEPROM_BASE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define EEPROM_WORDS 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define EEPROM_BYTES (EEPROM_WORDS * sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct eeprom_boot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u32 key1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u32 key2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u32 sram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct seg_hdr loader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) u32 init_chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct eeprom_manf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u32 HeaderFmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u32 Firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u32 BoardRevision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u32 RoadrunnerRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) char OpticsPart[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u32 OpticsRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u32 pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) char SramPart[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) u32 SramRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u32 pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) char EepromPart[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u32 EepromRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 EepromSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) char PalPart[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u32 PalRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u32 pad3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) char PalCodeFile[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u32 PalCodeRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) char BoardULA[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) char SerialNo[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) char MfgDate[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) char MfgTime[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) char ModifyDate[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u32 ModCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u32 pad4[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct eeprom_phase_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) char phase1File[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) u32 phase1Rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) char phase1Date[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) char phase2File[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u32 phase2Rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) char phase2Date[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u32 reserved7[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct eeprom_rncd_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u32 FwStart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u32 FwRev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) char FwDate[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u32 AddrRunCodeSegs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u32 FileNames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) char File[13][8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Phase 1 region (starts are word offset 0x80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct phase1_hdr{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u32 jump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u32 noop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct seg_hdr phase2Seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct eeprom {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct eeprom_boot boot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u32 pad1[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct eeprom_manf manf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct eeprom_phase_info phase_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct eeprom_rncd_info rncd_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u32 pad2[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u32 hdr_checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct phase1_hdr phase1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct rr_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u32 NicTimeStamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u32 RngCreated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u32 RngDeleted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u32 IntrGen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u32 NEvtOvfl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u32 InvCmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) u32 DmaReadErrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) u32 DmaWriteErrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) u32 StatUpdtT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) u32 StatUpdtC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u32 WatchDog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u32 Trace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* Serial HIPPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u32 LnkRdyEst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u32 GLinkErr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u32 AltFlgErr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u32 OvhdBit8Sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u32 RmtSerPrtyErr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u32 RmtParPrtyErr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) u32 RmtLoopBk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) u32 pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* HIPPI tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u32 ConEst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) u32 ConRejS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) u32 ConRetry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) u32 ConTmOut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) u32 SndConDiscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) u32 SndParErr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) u32 PktSnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u32 pad2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) u32 ShFBstSnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u64 BytSent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) u32 TxTimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u32 pad3[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* HIPPI rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u32 ConAcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) u32 ConRejdiPrty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) u32 ConRejd64b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u32 ConRejdBuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) u32 RxConDiscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) u32 RxConNoData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) u32 PktRx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) u32 pad4[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) u32 ShFBstRx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) u64 BytRx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) u32 RxParErr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u32 RxLLRCerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) u32 RxBstSZerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) u32 RxStateErr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) u32 RxRdyErr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u32 RxInvULP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) u32 RxSpcBuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) u32 RxSpcDesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) u32 RxRngSpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) u32 RxRngFull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u32 RxPktLenErr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u32 RxCksmErr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 RxPktDrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) u32 RngLowSpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u32 RngDataClose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) u32 RxTimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u32 RxIdle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * This struct is shared with the NIC firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct ring_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) rraddr rngptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) u16 entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) u8 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) u8 entry_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) u16 pi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u16 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u8 entry_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u8 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u16 entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) u16 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u16 pi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct rr_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct rr_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) u32 stati[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) } s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct ring_ctrl evt_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct ring_ctrl cmd_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct ring_ctrl tx_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) u8 pad[464];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u8 trace[3072];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * The linux structure for the RoadRunner.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * RX/TX descriptors are put first to make sure they are properly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * aligned and do not cross cache-line boundaries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct rr_private
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct rx_desc *rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct tx_desc *tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct event *evt_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dma_addr_t tx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dma_addr_t rx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dma_addr_t evt_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* Alignment ok ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct sk_buff *rx_skbuff[RX_RING_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct sk_buff *tx_skbuff[TX_RING_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct rr_regs __iomem *regs; /* Register base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct ring_ctrl *rx_ctrl; /* Receive ring control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct rr_info *info; /* Shared info page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) dma_addr_t rx_ctrl_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) dma_addr_t info_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) u32 cur_rx, cur_cmd, cur_evt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u32 dirty_rx, dirty_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) u32 tx_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u32 fw_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) volatile short fw_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * Prototypes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static int rr_init(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static int rr_init1(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static irqreturn_t rr_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static int rr_open(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static netdev_tx_t rr_start_xmit(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static int rr_close(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static int rr_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static unsigned int rr_read_eeprom(struct rr_private *rrpriv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) unsigned char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) unsigned long length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static u32 rr_read_eeprom_word(struct rr_private *rrpriv, size_t offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static int rr_load_firmware(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static inline void rr_raz_tx(struct rr_private *, struct net_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static inline void rr_raz_rx(struct rr_private *, struct net_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #endif /* _RRUNNER_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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