^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * yam.c -- YAM radio modem driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1998 Frederic Rible F1OAT (frible@teaser.fr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Adapted from baycom.c driver written by Thomas Sailer (sailer@ife.ee.ethz.ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Please note that the GPL allows you to use the driver, NOT the radio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * In order to use the radio, you need a license from the communications
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * authority of your country.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * History:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * 0.0 F1OAT 06.06.98 Begin of work with baycom.c source code V 0.3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * 0.1 F1OAT 07.06.98 Add timer polling routine for channel arbitration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * 0.2 F6FBB 08.06.98 Added delay after FPGA programming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * 0.3 F6FBB 29.07.98 Delayed PTT implementation for dupmode=2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * 0.4 F6FBB 30.07.98 Added TxTail, Slottime and Persistence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * 0.5 F6FBB 01.08.98 Shared IRQs, /proc/net and network statistics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * 0.6 F6FBB 25.08.98 Added 1200Bds format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * 0.7 F6FBB 12.09.98 Added to the kernel configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * 0.8 F6FBB 14.10.98 Fixed slottime/persistence timing bug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * OK1ZIA 2.09.01 Fixed "kfree_skb on hard IRQ"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * using dev_kfree_skb_any(). (important in 2.4 kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/net.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/in.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/if.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/if_arp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <net/ax25.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <net/net_namespace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/yam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const char yam_drvname[] = "yam";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const char yam_drvinfo[] __initconst = KERN_INFO \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "YAM driver version 0.8 by F1OAT/F6FBB\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FIRMWARE_9600 "yam/9600.bin"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define FIRMWARE_1200 "yam/1200.bin"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define YAM_9600 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define YAM_1200 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define NR_PORTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define YAM_MAGIC 0xF10A7654
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Transmitter states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TX_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TX_HEAD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TX_DATA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TX_CRC1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TX_CRC2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TX_TAIL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define YAM_MAX_FRAME 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DEFAULT_BITRATE 9600 /* bps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DEFAULT_HOLDD 10 /* sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DEFAULT_TXD 300 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DEFAULT_TXTAIL 10 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DEFAULT_SLOT 100 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DEFAULT_PERS 64 /* 0->255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct yam_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int bitrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int baudrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int dupmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int nb_rxint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int nb_mdint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Parameters section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int txd; /* tx delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int holdd; /* duplex ptt delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int txtail; /* txtail delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int slot; /* slottime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int pers; /* persistence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Tx section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int tx_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int tx_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int slotcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned char tx_buf[YAM_MAX_FRAME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int tx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int tx_crcl, tx_crch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct sk_buff_head send_queue; /* Packets awaiting transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Rx section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int dcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned char rx_buf[YAM_MAX_FRAME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int rx_crcl, rx_crch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct yam_mcs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned char bits[YAM_FPGA_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int bitrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct yam_mcs *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static struct net_device *yam_devs[NR_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct yam_mcs *yam_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static DEFINE_TIMER(yam_timer, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RBR(iobase) (iobase+0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define THR(iobase) (iobase+0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IER(iobase) (iobase+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IIR(iobase) (iobase+2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define FCR(iobase) (iobase+2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define LCR(iobase) (iobase+3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MCR(iobase) (iobase+4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define LSR(iobase) (iobase+5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MSR(iobase) (iobase+6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SCR(iobase) (iobase+7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DLL(iobase) (iobase+0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DLM(iobase) (iobase+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define YAM_EXTENT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Interrupt Identification Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IIR_NOPEND 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IIR_MSR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IIR_TX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IIR_RX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IIR_LSR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IIR_TIMEOUT 12 /* Fifo mode only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IIR_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Interrupt Enable Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IER_RX 1 /* enable rx interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IER_TX 2 /* enable tx interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IER_LSR 4 /* enable line status interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IER_MSR 8 /* enable modem status interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Modem Control Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MCR_DTR 0x01 /* DTR output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MCR_RTS 0x02 /* RTS output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MCR_OUT1 0x04 /* OUT1 output (not accessible in RS232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MCR_OUT2 0x08 /* Master Interrupt enable (must be set on PCs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MCR_LOOP 0x10 /* Loopback enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Modem Status Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MSR_DCTS 0x01 /* Delta CTS input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MSR_DDSR 0x02 /* Delta DSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MSR_DRIN 0x04 /* Delta RI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MSR_DDCD 0x08 /* Delta DCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MSR_CTS 0x10 /* CTS input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MSR_DSR 0x20 /* DSR input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MSR_RING 0x40 /* RI input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MSR_DCD 0x80 /* DCD input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* line status register bit mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define LSR_RXC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define LSR_OE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define LSR_PE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define LSR_FE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define LSR_BREAK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define LSR_THRE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define LSR_TSRE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Line Control Register Bit Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define LCR_DLAB 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define LCR_BREAK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define LCR_PZERO 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define LCR_PEVEN 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define LCR_PODD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define LCR_STOP1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define LCR_STOP2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define LCR_BIT5 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define LCR_BIT6 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define LCR_BIT7 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define LCR_BIT8 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* YAM Modem <-> UART Port mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TX_RDY MSR_DCTS /* transmitter ready to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define RX_DCD MSR_DCD /* carrier detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define RX_FLAG MSR_RING /* hdlc flag received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define FPGA_DONE MSR_DSR /* FPGA is configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define PTT_ON (MCR_RTS|MCR_OUT2) /* activate PTT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define PTT_OFF (MCR_DTR|MCR_OUT2) /* release PTT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define ENABLE_RXINT IER_RX /* enable uart rx interrupt during rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define ENABLE_TXINT IER_MSR /* enable uart ms interrupt during tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define ENABLE_RTXINT (IER_RX|IER_MSR) /* full duplex operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * CRC Tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const unsigned char chktabl[256] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x00, 0x89, 0x12, 0x9b, 0x24, 0xad, 0x36, 0xbf, 0x48, 0xc1, 0x5a, 0xd3, 0x6c, 0xe5, 0x7e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 0xf7, 0x81, 0x08, 0x93, 0x1a, 0xa5, 0x2c, 0xb7, 0x3e, 0xc9, 0x40, 0xdb, 0x52, 0xed, 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 0xff, 0x76, 0x02, 0x8b, 0x10, 0x99, 0x26, 0xaf, 0x34, 0xbd, 0x4a, 0xc3, 0x58, 0xd1, 0x6e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 0xe7, 0x7c, 0xf5, 0x83, 0x0a, 0x91, 0x18, 0xa7, 0x2e, 0xb5, 0x3c, 0xcb, 0x42, 0xd9, 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 0xef, 0x66, 0xfd, 0x74, 0x04, 0x8d, 0x16, 0x9f, 0x20, 0xa9, 0x32, 0xbb, 0x4c, 0xc5, 0x5e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 0xd7, 0x68, 0xe1, 0x7a, 0xf3, 0x85, 0x0c, 0x97, 0x1e, 0xa1, 0x28, 0xb3, 0x3a, 0xcd, 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 0xdf, 0x56, 0xe9, 0x60, 0xfb, 0x72, 0x06, 0x8f, 0x14, 0x9d, 0x22, 0xab, 0x30, 0xb9, 0x4e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 0xc7, 0x5c, 0xd5, 0x6a, 0xe3, 0x78, 0xf1, 0x87, 0x0e, 0x95, 0x1c, 0xa3, 0x2a, 0xb1, 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 0xcf, 0x46, 0xdd, 0x54, 0xeb, 0x62, 0xf9, 0x70, 0x08, 0x81, 0x1a, 0x93, 0x2c, 0xa5, 0x3e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 0xb7, 0x40, 0xc9, 0x52, 0xdb, 0x64, 0xed, 0x76, 0xff, 0x89, 0x00, 0x9b, 0x12, 0xad, 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 0xbf, 0x36, 0xc1, 0x48, 0xd3, 0x5a, 0xe5, 0x6c, 0xf7, 0x7e, 0x0a, 0x83, 0x18, 0x91, 0x2e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 0xa7, 0x3c, 0xb5, 0x42, 0xcb, 0x50, 0xd9, 0x66, 0xef, 0x74, 0xfd, 0x8b, 0x02, 0x99, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 0xaf, 0x26, 0xbd, 0x34, 0xc3, 0x4a, 0xd1, 0x58, 0xe7, 0x6e, 0xf5, 0x7c, 0x0c, 0x85, 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 0x97, 0x28, 0xa1, 0x3a, 0xb3, 0x44, 0xcd, 0x56, 0xdf, 0x60, 0xe9, 0x72, 0xfb, 0x8d, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 0x9f, 0x16, 0xa9, 0x20, 0xbb, 0x32, 0xc5, 0x4c, 0xd7, 0x5e, 0xe1, 0x68, 0xf3, 0x7a, 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 0x87, 0x1c, 0x95, 0x2a, 0xa3, 0x38, 0xb1, 0x46, 0xcf, 0x54, 0xdd, 0x62, 0xeb, 0x70, 0xf9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 0x8f, 0x06, 0x9d, 0x14, 0xab, 0x22, 0xb9, 0x30, 0xc7, 0x4e, 0xd5, 0x5c, 0xe3, 0x6a, 0xf1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 0x78};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const unsigned char chktabh[256] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x00, 0x11, 0x23, 0x32, 0x46, 0x57, 0x65, 0x74, 0x8c, 0x9d, 0xaf, 0xbe, 0xca, 0xdb, 0xe9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 0xf8, 0x10, 0x01, 0x33, 0x22, 0x56, 0x47, 0x75, 0x64, 0x9c, 0x8d, 0xbf, 0xae, 0xda, 0xcb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 0xf9, 0xe8, 0x21, 0x30, 0x02, 0x13, 0x67, 0x76, 0x44, 0x55, 0xad, 0xbc, 0x8e, 0x9f, 0xeb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 0xfa, 0xc8, 0xd9, 0x31, 0x20, 0x12, 0x03, 0x77, 0x66, 0x54, 0x45, 0xbd, 0xac, 0x9e, 0x8f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 0xfb, 0xea, 0xd8, 0xc9, 0x42, 0x53, 0x61, 0x70, 0x04, 0x15, 0x27, 0x36, 0xce, 0xdf, 0xed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 0xfc, 0x88, 0x99, 0xab, 0xba, 0x52, 0x43, 0x71, 0x60, 0x14, 0x05, 0x37, 0x26, 0xde, 0xcf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 0xfd, 0xec, 0x98, 0x89, 0xbb, 0xaa, 0x63, 0x72, 0x40, 0x51, 0x25, 0x34, 0x06, 0x17, 0xef,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 0xfe, 0xcc, 0xdd, 0xa9, 0xb8, 0x8a, 0x9b, 0x73, 0x62, 0x50, 0x41, 0x35, 0x24, 0x16, 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 0xff, 0xee, 0xdc, 0xcd, 0xb9, 0xa8, 0x9a, 0x8b, 0x84, 0x95, 0xa7, 0xb6, 0xc2, 0xd3, 0xe1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 0xf0, 0x08, 0x19, 0x2b, 0x3a, 0x4e, 0x5f, 0x6d, 0x7c, 0x94, 0x85, 0xb7, 0xa6, 0xd2, 0xc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 0xf1, 0xe0, 0x18, 0x09, 0x3b, 0x2a, 0x5e, 0x4f, 0x7d, 0x6c, 0xa5, 0xb4, 0x86, 0x97, 0xe3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 0xf2, 0xc0, 0xd1, 0x29, 0x38, 0x0a, 0x1b, 0x6f, 0x7e, 0x4c, 0x5d, 0xb5, 0xa4, 0x96, 0x87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 0xf3, 0xe2, 0xd0, 0xc1, 0x39, 0x28, 0x1a, 0x0b, 0x7f, 0x6e, 0x5c, 0x4d, 0xc6, 0xd7, 0xe5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 0xf4, 0x80, 0x91, 0xa3, 0xb2, 0x4a, 0x5b, 0x69, 0x78, 0x0c, 0x1d, 0x2f, 0x3e, 0xd6, 0xc7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 0xf5, 0xe4, 0x90, 0x81, 0xb3, 0xa2, 0x5a, 0x4b, 0x79, 0x68, 0x1c, 0x0d, 0x3f, 0x2e, 0xe7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 0xf6, 0xc4, 0xd5, 0xa1, 0xb0, 0x82, 0x93, 0x6b, 0x7a, 0x48, 0x59, 0x2d, 0x3c, 0x0e, 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 0xf7, 0xe6, 0xd4, 0xc5, 0xb1, 0xa0, 0x92, 0x83, 0x7b, 0x6a, 0x58, 0x49, 0x3d, 0x2c, 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 0x0f};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * FPGA functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static void delay(int ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned long timeout = jiffies + ((ms * HZ) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) while (time_before(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * reset FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static void fpga_reset(int iobase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) outb(0, IER(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) outb(LCR_DLAB | LCR_BIT5, LCR(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) outb(1, DLL(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) outb(0, DLM(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) outb(LCR_BIT5, LCR(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) inb(LSR(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) inb(MSR(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* turn off FPGA supply voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) outb(MCR_OUT1 | MCR_OUT2, MCR(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) delay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* turn on FPGA supply voltage again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) outb(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2, MCR(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) delay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * send one byte to FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int fpga_write(int iobase, unsigned char wrd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned char bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned long timeout = jiffies + HZ / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) for (k = 0; k < 8; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) bit = (wrd & 0x80) ? (MCR_RTS | MCR_DTR) : MCR_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) outb(bit | MCR_OUT1 | MCR_OUT2, MCR(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) wrd <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) outb(0xfc, THR(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) while ((inb(LSR(iobase)) & LSR_TSRE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * predef should be 0 for loading user defined mcs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * predef should be YAM_1200 for loading predef 1200 mcs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * predef should be YAM_9600 for loading predef 9600 mcs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static unsigned char *add_mcs(unsigned char *bits, int bitrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned int predef)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) const char *fw_name[2] = {FIRMWARE_9600, FIRMWARE_1200};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct yam_mcs *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) switch (predef) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case YAM_1200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case YAM_9600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) predef--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pdev = platform_device_register_simple("yam", 0, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (IS_ERR(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) printk(KERN_ERR "yam: Failed to register firmware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) err = request_firmware(&fw, fw_name[predef], &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) platform_device_unregister(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) printk(KERN_ERR "Failed to load firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) fw_name[predef]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (fw->size != YAM_FPGA_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) printk(KERN_ERR "Bogus length %zu in firmware \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) fw->size, fw_name[predef]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) bits = (unsigned char *)fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) printk(KERN_ERR "yam: Invalid predef number %u\n", predef);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* If it already exists, replace the bit data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) p = yam_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) while (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (p->bitrate == bitrate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) memcpy(p->bits, bits, YAM_FPGA_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) p = p->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Allocate a new mcs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if ((p = kmalloc(sizeof(struct yam_mcs), GFP_KERNEL)) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) memcpy(p->bits, bits, YAM_FPGA_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) p->bitrate = bitrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) p->next = yam_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) yam_data = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return p->bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static unsigned char *get_mcs(int bitrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct yam_mcs *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) p = yam_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) while (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (p->bitrate == bitrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return p->bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) p = p->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Load predefined mcs data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) switch (bitrate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case 1200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* setting predef as YAM_1200 for loading predef 1200 mcs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return add_mcs(NULL, bitrate, YAM_1200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* setting predef as YAM_9600 for loading predef 9600 mcs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return add_mcs(NULL, bitrate, YAM_9600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * download bitstream to FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * data is contained in bits[] array in yam1200.h resp. yam9600.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static int fpga_download(int iobase, int bitrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) unsigned char *pbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) pbits = get_mcs(bitrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (pbits == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) fpga_reset(iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) for (i = 0; i < YAM_FPGA_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (fpga_write(iobase, pbits[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) printk(KERN_ERR "yam: error in write cycle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return -1; /* write... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) fpga_write(iobase, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) rc = inb(MSR(iobase)); /* check DONE signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Needed for some hardwares */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) delay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return (rc & MSR_DSR) ? 0 : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * Serial port init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static void yam_set_uart(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct yam_port *yp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int divisor = 115200 / yp->baudrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) outb(0, IER(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) outb(LCR_DLAB | LCR_BIT8, LCR(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) outb(divisor, DLL(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) outb(0, DLM(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) outb(LCR_BIT8, LCR(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) outb(PTT_OFF, MCR(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) outb(0x00, FCR(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Flush pending irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) inb(RBR(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) inb(MSR(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Enable rx irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) outb(ENABLE_RTXINT, IER(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) enum uart {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) c_uart_unknown, c_uart_8250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) c_uart_16450, c_uart_16550, c_uart_16550A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static const char *uart_str[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {"unknown", "8250", "16450", "16550", "16550A"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static enum uart yam_check_uart(unsigned int iobase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) unsigned char b1, b2, b3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) enum uart u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) enum uart uart_tab[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {c_uart_16450, c_uart_unknown, c_uart_16550, c_uart_16550A};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) b1 = inb(MCR(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) outb(b1 | 0x10, MCR(iobase)); /* loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) b2 = inb(MSR(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) outb(0x1a, MCR(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) b3 = inb(MSR(iobase)) & 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) outb(b1, MCR(iobase)); /* restore old values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) outb(b2, MSR(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (b3 != 0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return c_uart_unknown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) inb(RBR(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) inb(RBR(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) outb(0x01, FCR(iobase)); /* enable FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u = uart_tab[(inb(IIR(iobase)) >> 6) & 3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (u == c_uart_16450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) outb(0x5a, SCR(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) b1 = inb(SCR(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) outb(0xa5, SCR(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) b2 = inb(SCR(iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if ((b1 != 0x5a) || (b2 != 0xa5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u = c_uart_8250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * Rx Section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static inline void yam_rx_flag(struct net_device *dev, struct yam_port *yp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (yp->dcd && yp->rx_len >= 3 && yp->rx_len < YAM_MAX_FRAME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int pkt_len = yp->rx_len - 2 + 1; /* -CRC + kiss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if ((yp->rx_crch & yp->rx_crcl) != 0xFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Bad crc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!(skb = dev_alloc_skb(pkt_len))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) printk(KERN_WARNING "%s: memory squeeze, dropping packet\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ++dev->stats.rx_dropped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) unsigned char *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) cp = skb_put(skb, pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) *cp++ = 0; /* KISS kludge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) memcpy(cp, yp->rx_buf, pkt_len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) skb->protocol = ax25_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ++dev->stats.rx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) yp->rx_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) yp->rx_crcl = 0x21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) yp->rx_crch = 0xf3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static inline void yam_rx_byte(struct net_device *dev, struct yam_port *yp, unsigned char rxb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (yp->rx_len < YAM_MAX_FRAME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) unsigned char c = yp->rx_crcl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) yp->rx_crcl = (chktabl[c] ^ yp->rx_crch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) yp->rx_crch = (chktabh[c] ^ rxb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) yp->rx_buf[yp->rx_len++] = rxb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /********************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * TX Section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ********************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static void ptt_on(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) outb(PTT_ON, MCR(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static void ptt_off(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) outb(PTT_OFF, MCR(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static netdev_tx_t yam_send_packet(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct yam_port *yp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (skb->protocol == htons(ETH_P_IP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return ax25_ip_xmit(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) skb_queue_tail(&yp->send_queue, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) netif_trans_update(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static void yam_start_tx(struct net_device *dev, struct yam_port *yp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if ((yp->tx_state == TX_TAIL) || (yp->txd == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) yp->tx_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) yp->tx_count = (yp->bitrate * yp->txd) / 8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) yp->tx_state = TX_HEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ptt_on(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static void yam_arbitrate(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct yam_port *yp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (yp->magic != YAM_MAGIC || yp->tx_state != TX_OFF ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) skb_queue_empty(&yp->send_queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* tx_state is TX_OFF and there is data to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (yp->dupmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* Full duplex mode, don't wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) yam_start_tx(dev, yp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (yp->dcd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* DCD on, wait slotime ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) yp->slotcnt = yp->slot / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* Is slottime passed ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if ((--yp->slotcnt) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) yp->slotcnt = yp->slot / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* is random > persist ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if ((prandom_u32() % 256) > yp->pers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) yam_start_tx(dev, yp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static void yam_dotimer(struct timer_list *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) for (i = 0; i < NR_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct net_device *dev = yam_devs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (dev && netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) yam_arbitrate(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) yam_timer.expires = jiffies + HZ / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) add_timer(&yam_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static void yam_tx_byte(struct net_device *dev, struct yam_port *yp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) unsigned char b, temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) switch (yp->tx_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) case TX_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) case TX_HEAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (--yp->tx_count <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (!(skb = skb_dequeue(&yp->send_queue))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ptt_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) yp->tx_state = TX_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) yp->tx_state = TX_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (skb->data[0] != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* do_kiss_params(s, skb->data, skb->len); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) yp->tx_len = skb->len - 1; /* strip KISS byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (yp->tx_len >= YAM_MAX_FRAME || yp->tx_len < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) skb_copy_from_linear_data_offset(skb, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) yp->tx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) yp->tx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) yp->tx_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) yp->tx_crcl = 0x21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) yp->tx_crch = 0xf3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) yp->tx_state = TX_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) case TX_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) b = yp->tx_buf[yp->tx_count++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) outb(b, THR(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) temp = yp->tx_crcl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) yp->tx_crcl = chktabl[temp] ^ yp->tx_crch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) yp->tx_crch = chktabh[temp] ^ b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (yp->tx_count >= yp->tx_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) yp->tx_state = TX_CRC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) case TX_CRC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) yp->tx_crch = chktabl[yp->tx_crcl] ^ yp->tx_crch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) yp->tx_crcl = chktabh[yp->tx_crcl] ^ chktabl[yp->tx_crch] ^ 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) outb(yp->tx_crcl, THR(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) yp->tx_state = TX_CRC2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) case TX_CRC2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) outb(chktabh[yp->tx_crch] ^ 0xFF, THR(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (skb_queue_empty(&yp->send_queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) yp->tx_count = (yp->bitrate * yp->txtail) / 8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (yp->dupmode == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) yp->tx_count += (yp->bitrate * yp->holdd) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (yp->tx_count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) yp->tx_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) yp->tx_state = TX_TAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) yp->tx_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) yp->tx_state = TX_HEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ++dev->stats.tx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) case TX_TAIL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (--yp->tx_count <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) yp->tx_state = TX_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ptt_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /***********************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * ISR routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ************************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static irqreturn_t yam_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct yam_port *yp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) unsigned char iir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) int counter = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) for (i = 0; i < NR_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dev = yam_devs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) yp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) while ((iir = IIR_MASK & inb(IIR(dev->base_addr))) != IIR_NOPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) unsigned char msr = inb(MSR(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) unsigned char lsr = inb(LSR(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) unsigned char rxb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (lsr & LSR_OE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ++dev->stats.rx_fifo_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) yp->dcd = (msr & RX_DCD) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (--counter <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) printk(KERN_ERR "%s: too many irq iir=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dev->name, iir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (msr & TX_RDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ++yp->nb_mdint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) yam_tx_byte(dev, yp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (lsr & LSR_RXC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ++yp->nb_rxint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) rxb = inb(RBR(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (msr & RX_FLAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) yam_rx_flag(dev, yp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) yam_rx_byte(dev, yp, rxb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static void *yam_seq_start(struct seq_file *seq, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return (*pos < NR_PORTS) ? yam_devs[*pos] : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static void *yam_seq_next(struct seq_file *seq, void *v, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ++*pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return (*pos < NR_PORTS) ? yam_devs[*pos] : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static void yam_seq_stop(struct seq_file *seq, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static int yam_seq_show(struct seq_file *seq, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct net_device *dev = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) const struct yam_port *yp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) seq_printf(seq, "Device %s\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) seq_printf(seq, " Up %d\n", netif_running(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) seq_printf(seq, " Speed %u\n", yp->bitrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) seq_printf(seq, " IoBase 0x%x\n", yp->iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) seq_printf(seq, " BaudRate %u\n", yp->baudrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) seq_printf(seq, " IRQ %u\n", yp->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) seq_printf(seq, " TxState %u\n", yp->tx_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) seq_printf(seq, " Duplex %u\n", yp->dupmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) seq_printf(seq, " HoldDly %u\n", yp->holdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) seq_printf(seq, " TxDelay %u\n", yp->txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) seq_printf(seq, " TxTail %u\n", yp->txtail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) seq_printf(seq, " SlotTime %u\n", yp->slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) seq_printf(seq, " Persist %u\n", yp->pers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) seq_printf(seq, " TxFrames %lu\n", dev->stats.tx_packets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) seq_printf(seq, " RxFrames %lu\n", dev->stats.rx_packets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) seq_printf(seq, " TxInt %u\n", yp->nb_mdint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) seq_printf(seq, " RxInt %u\n", yp->nb_rxint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) seq_printf(seq, " RxOver %lu\n", dev->stats.rx_fifo_errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) seq_printf(seq, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static const struct seq_operations yam_seqops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .start = yam_seq_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .next = yam_seq_next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .stop = yam_seq_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .show = yam_seq_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static int yam_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct yam_port *yp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) enum uart u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) int ret=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) printk(KERN_INFO "Trying %s at iobase 0x%lx irq %u\n", dev->name, dev->base_addr, dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (!yp->bitrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (!dev->base_addr || dev->base_addr > 0x1000 - YAM_EXTENT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) dev->irq < 2 || dev->irq > 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (!request_region(dev->base_addr, YAM_EXTENT, dev->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) printk(KERN_ERR "%s: cannot 0x%lx busy\n", dev->name, dev->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if ((u = yam_check_uart(dev->base_addr)) == c_uart_unknown) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) printk(KERN_ERR "%s: cannot find uart type\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) goto out_release_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (fpga_download(dev->base_addr, yp->bitrate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) printk(KERN_ERR "%s: cannot init FPGA\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) goto out_release_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) outb(0, IER(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (request_irq(dev->irq, yam_interrupt, IRQF_SHARED, dev->name, dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) printk(KERN_ERR "%s: irq %d busy\n", dev->name, dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) goto out_release_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) yam_set_uart(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) yp->slotcnt = yp->slot / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* Reset overruns for all ports - FPGA programming makes overruns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) for (i = 0; i < NR_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct net_device *yam_dev = yam_devs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) inb(LSR(yam_dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) yam_dev->stats.rx_fifo_errors = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) printk(KERN_INFO "%s at iobase 0x%lx irq %u uart %s\n", dev->name, dev->base_addr, dev->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) uart_str[u]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) out_release_base:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) release_region(dev->base_addr, YAM_EXTENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static int yam_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct yam_port *yp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * disable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) outb(0, IER(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) outb(1, MCR(dev->base_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* Remove IRQ handler if last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) free_irq(dev->irq,dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) release_region(dev->base_addr, YAM_EXTENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) while ((skb = skb_dequeue(&yp->send_queue)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) printk(KERN_INFO "%s: close yam at iobase 0x%lx irq %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) yam_drvname, dev->base_addr, dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static int yam_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct yam_port *yp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct yamdrv_ioctl_cfg yi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct yamdrv_ioctl_mcs *ym;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) int ioctl_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (copy_from_user(&ioctl_cmd, ifr->ifr_data, sizeof(int)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (yp->magic != YAM_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (!capable(CAP_NET_ADMIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (cmd != SIOCDEVPRIVATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) switch (ioctl_cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) case SIOCYAMRESERVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return -EINVAL; /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) case SIOCYAMSMCS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return -EINVAL; /* Cannot change this parameter when up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ym = memdup_user(ifr->ifr_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) sizeof(struct yamdrv_ioctl_mcs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (IS_ERR(ym))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return PTR_ERR(ym);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (ym->cmd != SIOCYAMSMCS || ym->bitrate > YAM_MAXBITRATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) kfree(ym);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* setting predef as 0 for loading userdefined mcs data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) add_mcs(ym->bits, ym->bitrate, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) kfree(ym);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) case SIOCYAMSCFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (!capable(CAP_SYS_RAWIO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (copy_from_user(&yi, ifr->ifr_data, sizeof(struct yamdrv_ioctl_cfg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (yi.cmd != SIOCYAMSCFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if ((yi.cfg.mask & YAM_IOBASE) && netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return -EINVAL; /* Cannot change this parameter when up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if ((yi.cfg.mask & YAM_IRQ) && netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return -EINVAL; /* Cannot change this parameter when up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if ((yi.cfg.mask & YAM_BITRATE) && netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return -EINVAL; /* Cannot change this parameter when up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if ((yi.cfg.mask & YAM_BAUDRATE) && netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return -EINVAL; /* Cannot change this parameter when up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (yi.cfg.mask & YAM_IOBASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) yp->iobase = yi.cfg.iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) dev->base_addr = yi.cfg.iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (yi.cfg.mask & YAM_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (yi.cfg.irq > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) yp->irq = yi.cfg.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) dev->irq = yi.cfg.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (yi.cfg.mask & YAM_BITRATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (yi.cfg.bitrate > YAM_MAXBITRATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) yp->bitrate = yi.cfg.bitrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (yi.cfg.mask & YAM_BAUDRATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (yi.cfg.baudrate > YAM_MAXBAUDRATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) yp->baudrate = yi.cfg.baudrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (yi.cfg.mask & YAM_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (yi.cfg.mode > YAM_MAXMODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) yp->dupmode = yi.cfg.mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (yi.cfg.mask & YAM_HOLDDLY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (yi.cfg.holddly > YAM_MAXHOLDDLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) yp->holdd = yi.cfg.holddly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (yi.cfg.mask & YAM_TXDELAY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (yi.cfg.txdelay > YAM_MAXTXDELAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) yp->txd = yi.cfg.txdelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (yi.cfg.mask & YAM_TXTAIL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (yi.cfg.txtail > YAM_MAXTXTAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) yp->txtail = yi.cfg.txtail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (yi.cfg.mask & YAM_PERSIST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (yi.cfg.persist > YAM_MAXPERSIST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) yp->pers = yi.cfg.persist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (yi.cfg.mask & YAM_SLOTTIME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (yi.cfg.slottime > YAM_MAXSLOTTIME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) yp->slot = yi.cfg.slottime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) yp->slotcnt = yp->slot / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) case SIOCYAMGCFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) memset(&yi, 0, sizeof(yi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) yi.cfg.mask = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) yi.cfg.iobase = yp->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) yi.cfg.irq = yp->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) yi.cfg.bitrate = yp->bitrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) yi.cfg.baudrate = yp->baudrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) yi.cfg.mode = yp->dupmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) yi.cfg.txdelay = yp->txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) yi.cfg.holddly = yp->holdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) yi.cfg.txtail = yp->txtail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) yi.cfg.persist = yp->pers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) yi.cfg.slottime = yp->slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (copy_to_user(ifr->ifr_data, &yi, sizeof(struct yamdrv_ioctl_cfg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static int yam_set_mac_address(struct net_device *dev, void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) struct sockaddr *sa = (struct sockaddr *) addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* addr is an AX.25 shifted ASCII mac address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static const struct net_device_ops yam_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .ndo_open = yam_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .ndo_stop = yam_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .ndo_start_xmit = yam_send_packet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .ndo_do_ioctl = yam_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .ndo_set_mac_address = yam_set_mac_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static void yam_setup(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct yam_port *yp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) yp->magic = YAM_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) yp->bitrate = DEFAULT_BITRATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) yp->baudrate = DEFAULT_BITRATE * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) yp->iobase = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) yp->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) yp->dupmode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) yp->holdd = DEFAULT_HOLDD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) yp->txd = DEFAULT_TXD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) yp->txtail = DEFAULT_TXTAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) yp->slot = DEFAULT_SLOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) yp->pers = DEFAULT_PERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) yp->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) dev->base_addr = yp->iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) dev->irq = yp->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) skb_queue_head_init(&yp->send_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) dev->netdev_ops = &yam_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) dev->header_ops = &ax25_header_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) dev->type = ARPHRD_AX25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) dev->hard_header_len = AX25_MAX_HEADER_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) dev->mtu = AX25_MTU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) dev->addr_len = AX25_ADDR_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) memcpy(dev->broadcast, &ax25_bcast, AX25_ADDR_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) memcpy(dev->dev_addr, &ax25_defaddr, AX25_ADDR_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static int __init yam_init_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) char name[IFNAMSIZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) printk(yam_drvinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) for (i = 0; i < NR_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) sprintf(name, "yam%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) dev = alloc_netdev(sizeof(struct yam_port), name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) NET_NAME_UNKNOWN, yam_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) pr_err("yam: cannot allocate net device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) err = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) printk(KERN_WARNING "yam: cannot register net device %s\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) yam_devs[i] = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) timer_setup(&yam_timer, yam_dotimer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) yam_timer.expires = jiffies + HZ / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) add_timer(&yam_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) proc_create_seq("yam", 0444, init_net.proc_net, &yam_seqops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) while (--i >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) unregister_netdev(yam_devs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) free_netdev(yam_devs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static void __exit yam_cleanup_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct yam_mcs *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) del_timer_sync(&yam_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) for (i = 0; i < NR_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) struct net_device *dev = yam_devs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) while (yam_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) p = yam_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) yam_data = yam_data->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) kfree(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) remove_proc_entry("yam", init_net.proc_net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) MODULE_AUTHOR("Frederic Rible F1OAT frible@teaser.fr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) MODULE_DESCRIPTION("Yam amateur radio modem driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) MODULE_FIRMWARE(FIRMWARE_1200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) MODULE_FIRMWARE(FIRMWARE_9600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) module_init(yam_init_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) module_exit(yam_cleanup_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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