^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * hdlcdrv.c -- HDLC packet radio network driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1996-2000 Thomas Sailer (sailer@ife.ee.ethz.ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Please note that the GPL allows you to use the driver, NOT the radio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * In order to use the radio, you need a license from the communications
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * authority of your country.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * The driver was derived from Donald Beckers skeleton.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Written 1993-94 by Donald Becker.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * History:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * 0.1 21.09.1996 Started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * 18.10.1996 Changed to new user space access routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * (copy_{to,from}_user)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * 0.2 21.11.1996 various small changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * 0.3 03.03.1997 fixed (hopefully) IP not working with ax.25 as a module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * 0.4 16.04.1997 init code/data tagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * 0.5 30.07.1997 made HDLC buffers bigger (solves a problem with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * soundmodem driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * 0.6 05.04.1998 add spinlocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * 0.7 03.08.1999 removed some old compatibility cruft
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 0.8 12.02.2000 adapted to softnet driver interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/capability.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/net.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/in.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/if.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/if_arp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/hdlcdrv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <net/ax25.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/crc-ccitt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define KISS_VERBOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PARAM_TXDELAY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PARAM_PERSIST 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PARAM_SLOTTIME 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PARAM_TXTAIL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PARAM_FULLDUP 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PARAM_HARDWARE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PARAM_RETURN 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * the CRC routines are stolen from WAMPES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * by Dieter Deyke
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*---------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline void append_crc_ccitt(unsigned char *buffer, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int crc = crc_ccitt(0xffff, buffer, len) ^ 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) buffer += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *buffer++ = crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *buffer++ = crc >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*---------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static inline int check_crc_ccitt(const unsigned char *buf, int cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return (crc_ccitt(0xffff, buf, cnt) & 0xffff) == 0xf0b8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*---------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int calc_crc_ccitt(const unsigned char *buf, int cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int crc = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) for (; cnt > 0; cnt--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) crc = (crc >> 8) ^ crc_ccitt_table[(crc ^ *buf++) & 0xff];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) crc ^= 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return crc & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define tenms_to_2flags(s,tenms) ((tenms * s->par.bitrate) / 100 / 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * The HDLC routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int hdlc_rx_add_bytes(struct hdlcdrv_state *s, unsigned int bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int added = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) while (s->hdlcrx.rx_state && num >= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (s->hdlcrx.len >= sizeof(s->hdlcrx.buffer)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) s->hdlcrx.rx_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *s->hdlcrx.bp++ = bits >> (32-num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) s->hdlcrx.len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) num -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) added += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return added;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void hdlc_rx_flag(struct net_device *dev, struct hdlcdrv_state *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int pkt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned char *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (s->hdlcrx.len < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (!check_crc_ccitt(s->hdlcrx.buffer, s->hdlcrx.len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pkt_len = s->hdlcrx.len - 2 + 1; /* KISS kludge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (!(skb = dev_alloc_skb(pkt_len))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) printk("%s: memory squeeze, dropping packet\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) cp = skb_put(skb, pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *cp++ = 0; /* KISS kludge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) memcpy(cp, s->hdlcrx.buffer, pkt_len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) skb->protocol = ax25_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void hdlcdrv_receiver(struct net_device *dev, struct hdlcdrv_state *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int mask1, mask2, mask3, mask4, mask5, mask6, word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (!s || s->magic != HDLCDRV_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (test_and_set_bit(0, &s->hdlcrx.in_hdlc_rx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) while (!hdlcdrv_hbuf_empty(&s->hdlcrx.hbuf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) word = hdlcdrv_hbuf_get(&s->hdlcrx.hbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #ifdef HDLCDRV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) hdlcdrv_add_bitbuffer_word(&s->bitbuf_hdlc, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif /* HDLCDRV_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) s->hdlcrx.bitstream >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) s->hdlcrx.bitstream |= word << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) s->hdlcrx.bitbuf >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) s->hdlcrx.bitbuf |= word << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) s->hdlcrx.numbits += 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) for(i = 15, mask1 = 0x1fc00, mask2 = 0x1fe00, mask3 = 0x0fc00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) mask4 = 0x1f800, mask5 = 0xf800, mask6 = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) i >= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) i--, mask1 <<= 1, mask2 <<= 1, mask3 <<= 1, mask4 <<= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mask5 <<= 1, mask6 = (mask6 << 1) | 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if ((s->hdlcrx.bitstream & mask1) == mask1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) s->hdlcrx.rx_state = 0; /* abort received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) else if ((s->hdlcrx.bitstream & mask2) == mask3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* flag received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (s->hdlcrx.rx_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) hdlc_rx_add_bytes(s, s->hdlcrx.bitbuf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) << (8+i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) s->hdlcrx.numbits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) -8-i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) hdlc_rx_flag(dev, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) s->hdlcrx.len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) s->hdlcrx.bp = s->hdlcrx.buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) s->hdlcrx.rx_state = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) s->hdlcrx.numbits = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) } else if ((s->hdlcrx.bitstream & mask4) == mask5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* stuffed bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) s->hdlcrx.numbits--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) s->hdlcrx.bitbuf = (s->hdlcrx.bitbuf & (~mask6)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ((s->hdlcrx.bitbuf & mask6) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) s->hdlcrx.numbits -= hdlc_rx_add_bytes(s, s->hdlcrx.bitbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) s->hdlcrx.numbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) clear_bit(0, &s->hdlcrx.in_hdlc_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static inline void do_kiss_params(struct hdlcdrv_state *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned char *data, unsigned long len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #ifdef KISS_VERBOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define PKP(a,b) printk(KERN_INFO "hdlcdrv.c: channel params: " a "\n", b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #else /* KISS_VERBOSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define PKP(a,b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #endif /* KISS_VERBOSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (len < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) switch(data[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case PARAM_TXDELAY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) s->ch_params.tx_delay = data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PKP("TX delay = %ums", 10 * s->ch_params.tx_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) case PARAM_PERSIST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) s->ch_params.ppersist = data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PKP("p persistence = %u", s->ch_params.ppersist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case PARAM_SLOTTIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) s->ch_params.slottime = data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PKP("slot time = %ums", s->ch_params.slottime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case PARAM_TXTAIL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) s->ch_params.tx_tail = data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PKP("TX tail = %ums", s->ch_params.tx_tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case PARAM_FULLDUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) s->ch_params.fulldup = !!data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PKP("%s duplex", s->ch_params.fulldup ? "full" : "half");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #undef PKP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) void hdlcdrv_transmitter(struct net_device *dev, struct hdlcdrv_state *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned int mask1, mask2, mask3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int pkt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (!s || s->magic != HDLCDRV_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (test_and_set_bit(0, &s->hdlctx.in_hdlc_tx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (s->hdlctx.numbits >= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (hdlcdrv_hbuf_full(&s->hdlctx.hbuf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) clear_bit(0, &s->hdlctx.in_hdlc_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) hdlcdrv_hbuf_put(&s->hdlctx.hbuf, s->hdlctx.bitbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) s->hdlctx.bitbuf >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) s->hdlctx.numbits -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) switch (s->hdlctx.tx_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) clear_bit(0, &s->hdlctx.in_hdlc_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (s->hdlctx.numflags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) s->hdlctx.numflags--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) s->hdlctx.bitbuf |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 0x7e7e << s->hdlctx.numbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) s->hdlctx.numbits += 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (s->hdlctx.tx_state == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) clear_bit(0, &s->hdlctx.in_hdlc_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (!(skb = s->skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int flgs = tenms_to_2flags(s, s->ch_params.tx_tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (flgs < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) flgs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) s->hdlctx.tx_state = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) s->hdlctx.numflags = flgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) s->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pkt_len = skb->len-1; /* strip KISS byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (pkt_len >= HDLCDRV_MAXFLEN || pkt_len < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) s->hdlctx.tx_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) s->hdlctx.numflags = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dev_kfree_skb_irq(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) skb_copy_from_linear_data_offset(skb, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) s->hdlctx.buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev_kfree_skb_irq(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) s->hdlctx.bp = s->hdlctx.buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) append_crc_ccitt(s->hdlctx.buffer, pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) s->hdlctx.len = pkt_len+2; /* the appended CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) s->hdlctx.tx_state = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) s->hdlctx.bitstream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (!s->hdlctx.len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) s->hdlctx.tx_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) s->hdlctx.numflags = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) s->hdlctx.len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) s->hdlctx.bitbuf |= *s->hdlctx.bp <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) s->hdlctx.numbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) s->hdlctx.bitstream >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) s->hdlctx.bitstream |= (*s->hdlctx.bp++) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) mask1 = 0x1f000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mask2 = 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) mask3 = 0xffffffff >> (31-s->hdlctx.numbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) s->hdlctx.numbits += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) for(i = 0; i < 8; i++, mask1 <<= 1, mask2 <<= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) mask3 = (mask3 << 1) | 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if ((s->hdlctx.bitstream & mask1) != mask1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) s->hdlctx.bitstream &= ~mask2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) s->hdlctx.bitbuf =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) (s->hdlctx.bitbuf & mask3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ((s->hdlctx.bitbuf &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) (~mask3)) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) s->hdlctx.numbits++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) mask3 = (mask3 << 1) | 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static void start_tx(struct net_device *dev, struct hdlcdrv_state *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) s->hdlctx.tx_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) s->hdlctx.numflags = tenms_to_2flags(s, s->ch_params.tx_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) s->hdlctx.bitbuf = s->hdlctx.bitstream = s->hdlctx.numbits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) hdlcdrv_transmitter(dev, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) s->hdlctx.ptt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) s->ptt_keyed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) void hdlcdrv_arbitrate(struct net_device *dev, struct hdlcdrv_state *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (!s || s->magic != HDLCDRV_MAGIC || s->hdlctx.ptt || !s->skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (s->ch_params.fulldup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) start_tx(dev, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (s->hdlcrx.dcd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) s->hdlctx.slotcnt = s->ch_params.slottime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if ((--s->hdlctx.slotcnt) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) s->hdlctx.slotcnt = s->ch_params.slottime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if ((prandom_u32() % 256) > s->ch_params.ppersist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) start_tx(dev, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * ===================== network driver interface =========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static netdev_tx_t hdlcdrv_send_packet(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct hdlcdrv_state *sm = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (skb->protocol == htons(ETH_P_IP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return ax25_ip_xmit(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (skb->data[0] != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) do_kiss_params(sm, skb->data, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (sm->skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) sm->skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static int hdlcdrv_set_mac_address(struct net_device *dev, void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct sockaddr *sa = (struct sockaddr *)addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* addr is an AX.25 shifted ASCII mac address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * Open/initialize the board. This is called (in the current kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * sometime after booting when the 'ifconfig' program is run.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * This routine should set everything up anew at each open, even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * registers that "should" only need to be set once at boot, so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * there is non-reboot way to recover if something goes wrong.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int hdlcdrv_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct hdlcdrv_state *s = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!s->ops || !s->ops->open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * initialise some variables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) s->opened = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) s->hdlcrx.hbuf.rd = s->hdlcrx.hbuf.wr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) s->hdlcrx.in_hdlc_rx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) s->hdlcrx.rx_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) s->hdlctx.hbuf.rd = s->hdlctx.hbuf.wr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) s->hdlctx.in_hdlc_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) s->hdlctx.tx_state = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) s->hdlctx.numflags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) s->hdlctx.bitstream = s->hdlctx.bitbuf = s->hdlctx.numbits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) s->hdlctx.ptt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) s->hdlctx.slotcnt = s->ch_params.slottime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) s->hdlctx.calibrate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) i = s->ops->open(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * The inverse routine to hdlcdrv_open().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int hdlcdrv_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct hdlcdrv_state *s = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (s->ops && s->ops->close)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) i = s->ops->close(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev_kfree_skb(s->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) s->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) s->opened = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int hdlcdrv_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct hdlcdrv_state *s = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct hdlcdrv_ioctl bi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (cmd != SIOCDEVPRIVATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (s->ops && s->ops->ioctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return s->ops->ioctl(dev, ifr, &bi, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (copy_from_user(&bi, ifr->ifr_data, sizeof(bi)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) switch (bi.cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (s->ops && s->ops->ioctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return s->ops->ioctl(dev, ifr, &bi, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) case HDLCDRVCTL_GETCHANNELPAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) bi.data.cp.tx_delay = s->ch_params.tx_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) bi.data.cp.tx_tail = s->ch_params.tx_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) bi.data.cp.slottime = s->ch_params.slottime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) bi.data.cp.ppersist = s->ch_params.ppersist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) bi.data.cp.fulldup = s->ch_params.fulldup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) case HDLCDRVCTL_SETCHANNELPAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!capable(CAP_NET_ADMIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) s->ch_params.tx_delay = bi.data.cp.tx_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) s->ch_params.tx_tail = bi.data.cp.tx_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) s->ch_params.slottime = bi.data.cp.slottime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) s->ch_params.ppersist = bi.data.cp.ppersist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) s->ch_params.fulldup = bi.data.cp.fulldup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) s->hdlctx.slotcnt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) case HDLCDRVCTL_GETMODEMPAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) bi.data.mp.iobase = dev->base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) bi.data.mp.irq = dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) bi.data.mp.dma = dev->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) bi.data.mp.dma2 = s->ptt_out.dma2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) bi.data.mp.seriobase = s->ptt_out.seriobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) bi.data.mp.pariobase = s->ptt_out.pariobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) bi.data.mp.midiiobase = s->ptt_out.midiiobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) case HDLCDRVCTL_SETMODEMPAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if ((!capable(CAP_SYS_RAWIO)) || netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dev->base_addr = bi.data.mp.iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dev->irq = bi.data.mp.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dev->dma = bi.data.mp.dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) s->ptt_out.dma2 = bi.data.mp.dma2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) s->ptt_out.seriobase = bi.data.mp.seriobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) s->ptt_out.pariobase = bi.data.mp.pariobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) s->ptt_out.midiiobase = bi.data.mp.midiiobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) case HDLCDRVCTL_GETSTAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) bi.data.cs.ptt = hdlcdrv_ptt(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) bi.data.cs.dcd = s->hdlcrx.dcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) bi.data.cs.ptt_keyed = s->ptt_keyed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) bi.data.cs.tx_packets = dev->stats.tx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) bi.data.cs.tx_errors = dev->stats.tx_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) bi.data.cs.rx_packets = dev->stats.rx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) bi.data.cs.rx_errors = dev->stats.rx_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) case HDLCDRVCTL_OLDGETSTAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) bi.data.ocs.ptt = hdlcdrv_ptt(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) bi.data.ocs.dcd = s->hdlcrx.dcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) bi.data.ocs.ptt_keyed = s->ptt_keyed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case HDLCDRVCTL_CALIBRATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if(!capable(CAP_SYS_RAWIO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (s->par.bitrate <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (bi.data.calibrate > INT_MAX / s->par.bitrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) s->hdlctx.calibrate = bi.data.calibrate * s->par.bitrate / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) case HDLCDRVCTL_GETSAMPLES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #ifndef HDLCDRV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #else /* HDLCDRV_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (s->bitbuf_channel.rd == s->bitbuf_channel.wr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) bi.data.bits =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) s->bitbuf_channel.buffer[s->bitbuf_channel.rd];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) s->bitbuf_channel.rd = (s->bitbuf_channel.rd+1) %
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) sizeof(s->bitbuf_channel.buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #endif /* HDLCDRV_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case HDLCDRVCTL_GETBITS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #ifndef HDLCDRV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #else /* HDLCDRV_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (s->bitbuf_hdlc.rd == s->bitbuf_hdlc.wr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) bi.data.bits =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) s->bitbuf_hdlc.buffer[s->bitbuf_hdlc.rd];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) s->bitbuf_hdlc.rd = (s->bitbuf_hdlc.rd+1) %
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) sizeof(s->bitbuf_hdlc.buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #endif /* HDLCDRV_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case HDLCDRVCTL_DRIVERNAME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (s->ops && s->ops->drvname) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) strncpy(bi.data.drivername, s->ops->drvname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) sizeof(bi.data.drivername));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) bi.data.drivername[0] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (copy_to_user(ifr->ifr_data, &bi, sizeof(bi)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const struct net_device_ops hdlcdrv_netdev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .ndo_open = hdlcdrv_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .ndo_stop = hdlcdrv_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .ndo_start_xmit = hdlcdrv_send_packet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .ndo_do_ioctl = hdlcdrv_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .ndo_set_mac_address = hdlcdrv_set_mac_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * Initialize fields in hdlcdrv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static void hdlcdrv_setup(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static const struct hdlcdrv_channel_params dflt_ch_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 20, 2, 10, 40, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct hdlcdrv_state *s = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * initialize the hdlcdrv_state struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) s->ch_params = dflt_ch_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) s->ptt_keyed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) spin_lock_init(&s->hdlcrx.hbuf.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) s->hdlcrx.hbuf.rd = s->hdlcrx.hbuf.wr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) s->hdlcrx.in_hdlc_rx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) s->hdlcrx.rx_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) spin_lock_init(&s->hdlctx.hbuf.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) s->hdlctx.hbuf.rd = s->hdlctx.hbuf.wr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) s->hdlctx.in_hdlc_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) s->hdlctx.tx_state = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) s->hdlctx.numflags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) s->hdlctx.bitstream = s->hdlctx.bitbuf = s->hdlctx.numbits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) s->hdlctx.ptt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) s->hdlctx.slotcnt = s->ch_params.slottime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) s->hdlctx.calibrate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #ifdef HDLCDRV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) s->bitbuf_channel.rd = s->bitbuf_channel.wr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) s->bitbuf_channel.shreg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) s->bitbuf_hdlc.rd = s->bitbuf_hdlc.wr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) s->bitbuf_hdlc.shreg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #endif /* HDLCDRV_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* Fill in the fields of the device structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) s->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dev->netdev_ops = &hdlcdrv_netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dev->header_ops = &ax25_header_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dev->type = ARPHRD_AX25; /* AF_AX25 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) dev->hard_header_len = AX25_MAX_HEADER_LEN + AX25_BPQ_HEADER_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dev->mtu = AX25_DEF_PACLEN; /* eth_mtu is the default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) dev->addr_len = AX25_ADDR_LEN; /* sizeof an ax.25 address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) memcpy(dev->broadcast, &ax25_bcast, AX25_ADDR_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) memcpy(dev->dev_addr, &ax25_defaddr, AX25_ADDR_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dev->tx_queue_len = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct net_device *hdlcdrv_register(const struct hdlcdrv_ops *ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) unsigned int privsize, const char *ifname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) unsigned int baseaddr, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) unsigned int dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct hdlcdrv_state *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (privsize < sizeof(struct hdlcdrv_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) privsize = sizeof(struct hdlcdrv_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) dev = alloc_netdev(privsize, ifname, NET_NAME_UNKNOWN, hdlcdrv_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * initialize part of the hdlcdrv_state struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) s = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) s->magic = HDLCDRV_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) s->ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) dev->base_addr = baseaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dev->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dev->dma = dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) err = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) printk(KERN_WARNING "hdlcdrv: cannot register net "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) "device %s\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) dev = ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) void hdlcdrv_unregister(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct hdlcdrv_state *s = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) BUG_ON(s->magic != HDLCDRV_MAGIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (s->opened && s->ops->close)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) s->ops->close(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) EXPORT_SYMBOL(hdlcdrv_receiver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) EXPORT_SYMBOL(hdlcdrv_transmitter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) EXPORT_SYMBOL(hdlcdrv_arbitrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) EXPORT_SYMBOL(hdlcdrv_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) EXPORT_SYMBOL(hdlcdrv_unregister);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static int __init hdlcdrv_init_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) printk(KERN_INFO "hdlcdrv: (C) 1996-2000 Thomas Sailer HB9JNX/AE4WA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) printk(KERN_INFO "hdlcdrv: version 0.8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static void __exit hdlcdrv_cleanup_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) printk(KERN_INFO "hdlcdrv: cleanup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) MODULE_DESCRIPTION("Packet Radio network interface HDLC encoder/decoder");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) module_init(hdlcdrv_init_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) module_exit(hdlcdrv_cleanup_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* --------------------------------------------------------------------- */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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