^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * FUJITSU Extended Socket Network Device driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2015 FUJITSU LIMITED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef FJES_REGS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define FJES_REGS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define XSCT_DEVICE_REGISTER_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Information registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define XSCT_OWNER_EPID 0x0000 /* Owner EPID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define XSCT_MAX_EP 0x0004 /* Maximum EP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Device Control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define XSCT_DCTL 0x0010 /* Device Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Command Control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define XSCT_CR 0x0020 /* Command request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define XSCT_CS 0x0024 /* Command status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define XSCT_SHSTSAL 0x0028 /* Share status address Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define XSCT_SHSTSAH 0x002C /* Share status address High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define XSCT_REQBL 0x0034 /* Request Buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define XSCT_REQBAL 0x0038 /* Request Buffer Address Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define XSCT_REQBAH 0x003C /* Request Buffer Address High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define XSCT_RESPBL 0x0044 /* Response Buffer Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define XSCT_RESPBAL 0x0048 /* Response Buffer Address Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define XSCT_RESPBAH 0x004C /* Response Buffer Address High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Interrupt Control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define XSCT_IS 0x0080 /* Interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define XSCT_IMS 0x0084 /* Interrupt mask set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define XSCT_IMC 0x0088 /* Interrupt mask clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define XSCT_IG 0x008C /* Interrupt generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define XSCT_ICTL 0x0090 /* Interrupt control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* register structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Information registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) union REG_OWNER_EPID {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __le32 epid:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __le32:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) } bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) __le32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) union REG_MAX_EP {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) __le32 maxep:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) __le32:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) } bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __le32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Device Control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) union REG_DCTL {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __le32 reset:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __le32 rsv0:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __le32 rsv1:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) } bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __le32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Command Control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) union REG_CR {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __le32 req_code:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) __le32 err_info:14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __le32 error:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __le32 req_start:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) } bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __le32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) union REG_CS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __le32 req_code:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __le32 rsv0:14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __le32 busy:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __le32 complete:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) } bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __le32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Interrupt Control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) union REG_ICTL {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) __le32 automak:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __le32 rsv0:31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) } bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __le32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) enum REG_ICTL_MASK {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) REG_ICTL_MASK_INFO_UPDATE = 1 << 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) REG_ICTL_MASK_DEV_STOP_REQ = 1 << 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) REG_ICTL_MASK_TXRX_STOP_REQ = 1 << 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) REG_ICTL_MASK_TXRX_STOP_DONE = 1 << 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) REG_ICTL_MASK_RX_DATA = 1 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) REG_ICTL_MASK_ALL = GENMASK(20, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) enum REG_IS_MASK {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) REG_IS_MASK_IS_ASSERT = 1 << 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) REG_IS_MASK_EPID = GENMASK(15, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct fjes_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 fjes_hw_rd32(struct fjes_hw *hw, u32 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define wr32(reg, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 *base = hw->base; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) writel((val), &base[(reg)]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define rd32(reg) (fjes_hw_rd32(hw, reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #endif /* FJES_REGS_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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