^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* FDDI network adapter driver for DEC FDDIcontroller 700/700-C devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2018 Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * modify it under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * as published by the Free Software Foundation; either version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * 2 of the License, or (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * References:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Dave Sawyer & Phil Weeks & Frank Itkowsky,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * "DEC FDDIcontroller 700 Port Specification",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Revision 1.1, Digital Equipment Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/if_fddi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* IOmem register offsets. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FZA_REG_BASE 0x100000 /* register base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FZA_REG_RESET 0x100200 /* reset, r/w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FZA_REG_INT_EVENT 0x100400 /* interrupt event, r/w1c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FZA_REG_STATUS 0x100402 /* status, r/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FZA_REG_INT_MASK 0x100404 /* interrupt mask, r/w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FZA_REG_CONTROL_A 0x100500 /* control A, r/w1s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FZA_REG_CONTROL_B 0x100502 /* control B, r/w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Reset register constants. Bits 1:0 are r/w, others are fixed at 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FZA_RESET_DLU 0x0002 /* OR with INIT to blast flash memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FZA_RESET_INIT 0x0001 /* switch into the reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FZA_RESET_CLR 0x0000 /* run self-test and return to work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Interrupt event register constants. All bits are r/w1c. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FZA_EVENT_DLU_DONE 0x0800 /* flash memory write complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FZA_EVENT_FLUSH_TX 0x0400 /* transmit ring flush request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FZA_EVENT_PM_PARITY_ERR 0x0200 /* onboard packet memory parity err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FZA_EVENT_HB_PARITY_ERR 0x0100 /* host bus parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FZA_EVENT_NXM_ERR 0x0080 /* non-existent memory access error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * also raised for unaligned and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * unsupported partial-word accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FZA_EVENT_LINK_ST_CHG 0x0040 /* link status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define FZA_EVENT_STATE_CHG 0x0020 /* adapter state change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FZA_EVENT_UNS_POLL 0x0010 /* unsolicited event service request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define FZA_EVENT_CMD_DONE 0x0008 /* command done ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FZA_EVENT_SMT_TX_POLL 0x0004 /* SMT frame transmit request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define FZA_EVENT_RX_POLL 0x0002 /* receive request (packet avail.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define FZA_EVENT_TX_DONE 0x0001 /* RMC transmit done ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Status register constants. All bits are r/o. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define FZA_STATUS_DLU_SHIFT 0xc /* down line upgrade status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FZA_STATUS_DLU_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define FZA_STATUS_LINK_SHIFT 0xb /* link status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define FZA_STATUS_LINK_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FZA_STATUS_STATE_SHIFT 0x8 /* adapter state bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FZA_STATUS_STATE_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FZA_STATUS_HALT_SHIFT 0x0 /* halt reason bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FZA_STATUS_HALT_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define FZA_STATUS_TEST_SHIFT 0x0 /* test failure bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define FZA_STATUS_TEST_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define FZA_STATUS_GET_DLU(x) (((x) >> FZA_STATUS_DLU_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) FZA_STATUS_DLU_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FZA_STATUS_GET_LINK(x) (((x) >> FZA_STATUS_LINK_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FZA_STATUS_LINK_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define FZA_STATUS_GET_STATE(x) (((x) >> FZA_STATUS_STATE_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FZA_STATUS_STATE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define FZA_STATUS_GET_HALT(x) (((x) >> FZA_STATUS_HALT_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) FZA_STATUS_HALT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define FZA_STATUS_GET_TEST(x) (((x) >> FZA_STATUS_TEST_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FZA_STATUS_TEST_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define FZA_DLU_FAILURE 0x0 /* DLU catastrophic error; brain dead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define FZA_DLU_ERROR 0x1 /* DLU error; old firmware intact */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define FZA_DLU_SUCCESS 0x2 /* DLU OK; new firmware loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define FZA_LINK_OFF 0x0 /* link unavailable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define FZA_LINK_ON 0x1 /* link available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define FZA_STATE_RESET 0x0 /* resetting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define FZA_STATE_UNINITIALIZED 0x1 /* after a reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define FZA_STATE_INITIALIZED 0x2 /* initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define FZA_STATE_RUNNING 0x3 /* running (link active) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define FZA_STATE_MAINTENANCE 0x4 /* running (link looped back) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define FZA_STATE_HALTED 0x5 /* halted (error condition) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define FZA_HALT_UNKNOWN 0x00 /* unknown reason */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define FZA_HALT_HOST 0x01 /* host-directed HALT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define FZA_HALT_HB_PARITY 0x02 /* host bus parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define FZA_HALT_NXM 0x03 /* adapter non-existent memory ref. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define FZA_HALT_SW 0x04 /* adapter software fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define FZA_HALT_HW 0x05 /* adapter hardware fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define FZA_HALT_PC_TRACE 0x06 /* PC Trace path test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define FZA_HALT_DLSW 0x07 /* data link software fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define FZA_HALT_DLHW 0x08 /* data link hardware fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define FZA_TEST_FATAL 0x00 /* self-test catastrophic failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define FZA_TEST_68K 0x01 /* 68000 CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define FZA_TEST_SRAM_BWADDR 0x02 /* SRAM byte/word address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define FZA_TEST_SRAM_DBUS 0x03 /* SRAM data bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define FZA_TEST_SRAM_STUCK1 0x04 /* SRAM stuck-at range 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define FZA_TEST_SRAM_STUCK2 0x05 /* SRAM stuck-at range 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define FZA_TEST_SRAM_COUPL1 0x06 /* SRAM coupling range 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define FZA_TEST_SRAM_COUPL2 0x07 /* SRAM coupling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define FZA_TEST_FLASH_CRC 0x08 /* Flash CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define FZA_TEST_ROM 0x09 /* option ROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define FZA_TEST_PHY_CSR 0x0a /* PHY CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define FZA_TEST_MAC_BIST 0x0b /* MAC BiST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define FZA_TEST_MAC_CSR 0x0c /* MAC CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define FZA_TEST_MAC_ADDR_UNIQ 0x0d /* MAC unique address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define FZA_TEST_ELM_BIST 0x0e /* ELM BiST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define FZA_TEST_ELM_CSR 0x0f /* ELM CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define FZA_TEST_ELM_ADDR_UNIQ 0x10 /* ELM unique address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define FZA_TEST_CAM 0x11 /* CAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define FZA_TEST_NIROM 0x12 /* NI ROM checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define FZA_TEST_SC_LOOP 0x13 /* SC loopback packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define FZA_TEST_LM_LOOP 0x14 /* LM loopback packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define FZA_TEST_EB_LOOP 0x15 /* EB loopback packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define FZA_TEST_SC_LOOP_BYPS 0x16 /* SC bypass loopback packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define FZA_TEST_LM_LOOP_LOCAL 0x17 /* LM local loopback packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define FZA_TEST_EB_LOOP_LOCAL 0x18 /* EB local loopback packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define FZA_TEST_CDC_LOOP 0x19 /* CDC loopback packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define FZA_TEST_FIBER_LOOP 0x1A /* FIBER loopback packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define FZA_TEST_CAM_MATCH_LOOP 0x1B /* CAM match packet loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define FZA_TEST_68K_IRQ_STUCK 0x1C /* 68000 interrupt line stuck-at */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define FZA_TEST_IRQ_PRESENT 0x1D /* interrupt present register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define FZA_TEST_RMC_BIST 0x1E /* RMC BiST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define FZA_TEST_RMC_CSR 0x1F /* RMC CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define FZA_TEST_RMC_ADDR_UNIQ 0x20 /* RMC unique address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define FZA_TEST_PM_DPATH 0x21 /* packet memory data path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define FZA_TEST_PM_ADDR 0x22 /* packet memory address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define FZA_TEST_RES_23 0x23 /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define FZA_TEST_PM_DESC 0x24 /* packet memory descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define FZA_TEST_PM_OWN 0x25 /* packet memory own bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define FZA_TEST_PM_PARITY 0x26 /* packet memory parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define FZA_TEST_PM_BSWAP 0x27 /* packet memory byte swap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define FZA_TEST_PM_WSWAP 0x28 /* packet memory word swap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define FZA_TEST_PM_REF 0x29 /* packet memory refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define FZA_TEST_PM_CSR 0x2A /* PM CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define FZA_TEST_PORT_STATUS 0x2B /* port status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define FZA_TEST_HOST_IRQMASK 0x2C /* host interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define FZA_TEST_TIMER_IRQ1 0x2D /* RTOS timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define FZA_TEST_FORCE_IRQ1 0x2E /* force RTOS IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define FZA_TEST_TIMER_IRQ5 0x2F /* IRQ5 backoff timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define FZA_TEST_FORCE_IRQ5 0x30 /* force IRQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define FZA_TEST_RES_31 0x31 /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define FZA_TEST_IC_PRIO 0x32 /* interrupt controller priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define FZA_TEST_PM_FULL 0x33 /* full packet memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define FZA_TEST_PMI_DMA 0x34 /* PMI DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Interrupt mask register constants. All bits are r/w. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define FZA_MASK_RESERVED 0xf000 /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define FZA_MASK_DLU_DONE 0x0800 /* flash memory write complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define FZA_MASK_FLUSH_TX 0x0400 /* transmit ring flush request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define FZA_MASK_PM_PARITY_ERR 0x0200 /* onboard packet memory parity error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define FZA_MASK_HB_PARITY_ERR 0x0100 /* host bus parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define FZA_MASK_NXM_ERR 0x0080 /* adapter non-existent memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * reference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define FZA_MASK_LINK_ST_CHG 0x0040 /* link status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define FZA_MASK_STATE_CHG 0x0020 /* adapter state change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define FZA_MASK_UNS_POLL 0x0010 /* unsolicited event service request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define FZA_MASK_CMD_DONE 0x0008 /* command ring entry processed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define FZA_MASK_SMT_TX_POLL 0x0004 /* SMT frame transmit request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define FZA_MASK_RCV_POLL 0x0002 /* receive request (packet available)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define FZA_MASK_TX_DONE 0x0001 /* RMC transmit done acknowledge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Which interrupts to receive: 0/1 is mask/unmask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define FZA_MASK_NONE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define FZA_MASK_NORMAL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ((~(FZA_MASK_RESERVED | FZA_MASK_DLU_DONE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) FZA_MASK_PM_PARITY_ERR | FZA_MASK_HB_PARITY_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) FZA_MASK_NXM_ERR)) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Control A register constants. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define FZA_CONTROL_A_HB_PARITY_ERR 0x8000 /* host bus parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define FZA_CONTROL_A_NXM_ERR 0x4000 /* adapter non-existent memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * reference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define FZA_CONTROL_A_SMT_RX_OVFL 0x0040 /* SMT receive overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define FZA_CONTROL_A_FLUSH_DONE 0x0020 /* flush tx request complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define FZA_CONTROL_A_SHUT 0x0010 /* turn the interface off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define FZA_CONTROL_A_HALT 0x0008 /* halt the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define FZA_CONTROL_A_CMD_POLL 0x0004 /* command ring poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define FZA_CONTROL_A_SMT_RX_POLL 0x0002 /* SMT receive ring poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define FZA_CONTROL_A_TX_POLL 0x0001 /* transmit poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Control B register constants. All bits are r/w.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * Possible values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * 0x0000 after booting into REX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * 0x0003 after issuing `boot #/mop'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define FZA_CONTROL_B_CONSOLE 0x0002 /* OR with DRIVER for console
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * (TC firmware) mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define FZA_CONTROL_B_DRIVER 0x0001 /* driver mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define FZA_CONTROL_B_IDLE 0x0000 /* no driver installed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define FZA_RESET_PAD \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) (FZA_REG_RESET - FZA_REG_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define FZA_INT_EVENT_PAD \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) (FZA_REG_INT_EVENT - FZA_REG_RESET - sizeof(u16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define FZA_CONTROL_A_PAD \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) (FZA_REG_CONTROL_A - FZA_REG_INT_MASK - sizeof(u16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Layout of registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct fza_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u8 pad0[FZA_RESET_PAD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u16 reset; /* reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u8 pad1[FZA_INT_EVENT_PAD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u16 int_event; /* interrupt event register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u16 status; /* status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u16 int_mask; /* interrupt mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u8 pad2[FZA_CONTROL_A_PAD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u16 control_a; /* control A register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u16 control_b; /* control B register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Command descriptor ring entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct fza_ring_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 cmd_own; /* bit 31: ownership, bits [30:0]: command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 stat; /* command status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 buffer; /* address of the buffer in the FZA space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 pad0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define FZA_RING_CMD 0x200400 /* command ring address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define FZA_RING_CMD_SIZE 0x40 /* command descriptor ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Command constants. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define FZA_RING_CMD_MASK 0x7fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define FZA_RING_CMD_NOP 0x00000000 /* nop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define FZA_RING_CMD_INIT 0x00000001 /* initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define FZA_RING_CMD_MODCAM 0x00000002 /* modify CAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define FZA_RING_CMD_PARAM 0x00000003 /* set system parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define FZA_RING_CMD_MODPROM 0x00000004 /* modify promiscuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define FZA_RING_CMD_SETCHAR 0x00000005 /* set link characteristics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define FZA_RING_CMD_RDCNTR 0x00000006 /* read counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define FZA_RING_CMD_STATUS 0x00000007 /* get link status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define FZA_RING_CMD_RDCAM 0x00000008 /* read CAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Command status constants. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define FZA_RING_STAT_SUCCESS 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Unsolicited event descriptor ring entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct fza_ring_uns {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 own; /* bit 31: ownership, bits [30:0]: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 id; /* event ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 buffer; /* address of the buffer in the FZA space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 pad0; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define FZA_RING_UNS 0x200800 /* unsolicited ring address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define FZA_RING_UNS_SIZE 0x40 /* unsolicited descriptor ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Unsolicited event constants. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define FZA_RING_UNS_UND 0x00000000 /* undefined event ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define FZA_RING_UNS_INIT_IN 0x00000001 /* ring init initiated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define FZA_RING_UNS_INIT_RX 0x00000002 /* ring init received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define FZA_RING_UNS_BEAC_IN 0x00000003 /* ring beaconing initiated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define FZA_RING_UNS_DUP_ADDR 0x00000004 /* duplicate address detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define FZA_RING_UNS_DUP_TOK 0x00000005 /* duplicate token detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define FZA_RING_UNS_PURG_ERR 0x00000006 /* ring purger error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define FZA_RING_UNS_STRIP_ERR 0x00000007 /* bridge strip error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define FZA_RING_UNS_OP_OSC 0x00000008 /* ring op oscillation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define FZA_RING_UNS_BEAC_RX 0x00000009 /* directed beacon received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define FZA_RING_UNS_PCT_IN 0x0000000a /* PC trace initiated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define FZA_RING_UNS_PCT_RX 0x0000000b /* PC trace received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define FZA_RING_UNS_TX_UNDER 0x0000000c /* transmit underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define FZA_RING_UNS_TX_FAIL 0x0000000d /* transmit failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define FZA_RING_UNS_RX_OVER 0x0000000e /* receive overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* RMC (Ring Memory Control) transmit descriptor ring entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct fza_ring_rmc_tx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 rmc; /* RMC information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 avl; /* available for host (unused by RMC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 own; /* bit 31: ownership, bits [30:0]: reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 pad0; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define FZA_TX_BUFFER_ADDR(x) (0x200000 | (((x) & 0xffff) << 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define FZA_TX_BUFFER_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct fza_buffer_tx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 data[FZA_TX_BUFFER_SIZE / sizeof(u32)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Transmit ring RMC constants. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define FZA_RING_TX_SOP 0x80000000 /* start of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define FZA_RING_TX_EOP 0x40000000 /* end of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define FZA_RING_TX_DTP 0x20000000 /* discard this packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define FZA_RING_TX_VBC 0x10000000 /* valid buffer byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define FZA_RING_TX_DCC_MASK 0x0f000000 /* DMA completion code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define FZA_RING_TX_DCC_SUCCESS 0x01000000 /* transmit succeeded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define FZA_RING_TX_DCC_DTP_SOP 0x02000000 /* DTP set at SOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define FZA_RING_TX_DCC_DTP 0x04000000 /* DTP set within packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define FZA_RING_TX_DCC_ABORT 0x05000000 /* MAC-requested abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define FZA_RING_TX_DCC_PARITY 0x06000000 /* xmit data parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define FZA_RING_TX_DCC_UNDRRUN 0x07000000 /* transmit underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define FZA_RING_TX_XPO_MASK 0x003fe000 /* transmit packet offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Host receive descriptor ring entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct fza_ring_hst_rx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 buf0_own; /* bit 31: ownership, bits [30:23]: unused,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * bits [22:0]: right-shifted address of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * buffer in system memory (low buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 buffer1; /* bits [31:23]: unused,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * bits [22:0]: right-shifted address of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * buffer in system memory (high buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 rmc; /* RMC information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 pad0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define FZA_RX_BUFFER_SIZE (4096 + 512) /* buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Receive ring RMC constants. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define FZA_RING_RX_SOP 0x80000000 /* start of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define FZA_RING_RX_EOP 0x40000000 /* end of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define FZA_RING_RX_FSC_MASK 0x38000000 /* # of frame status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define FZA_RING_RX_FSB_MASK 0x07c00000 /* frame status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define FZA_RING_RX_FSB_ERR 0x04000000 /* error detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define FZA_RING_RX_FSB_ADDR 0x02000000 /* address recognized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define FZA_RING_RX_FSB_COP 0x01000000 /* frame copied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define FZA_RING_RX_FSB_F0 0x00800000 /* first additional flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define FZA_RING_RX_FSB_F1 0x00400000 /* second additional flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define FZA_RING_RX_BAD 0x00200000 /* bad packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define FZA_RING_RX_CRC 0x00100000 /* CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define FZA_RING_RX_RRR_MASK 0x000e0000 /* MAC receive status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define FZA_RING_RX_RRR_OK 0x00000000 /* receive OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define FZA_RING_RX_RRR_SADDR 0x00020000 /* source address matched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define FZA_RING_RX_RRR_DADDR 0x00040000 /* dest address not matched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define FZA_RING_RX_RRR_ABORT 0x00060000 /* RMC abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define FZA_RING_RX_RRR_LENGTH 0x00080000 /* invalid length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define FZA_RING_RX_RRR_FRAG 0x000a0000 /* fragment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define FZA_RING_RX_RRR_FORMAT 0x000c0000 /* format error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define FZA_RING_RX_RRR_RESET 0x000e0000 /* MAC reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define FZA_RING_RX_DA_MASK 0x00018000 /* daddr match status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define FZA_RING_RX_DA_NONE 0x00000000 /* no match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define FZA_RING_RX_DA_PROM 0x00008000 /* promiscuous match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define FZA_RING_RX_DA_CAM 0x00010000 /* CAM entry match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define FZA_RING_RX_DA_LOCAL 0x00018000 /* link addr or LLC bcast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define FZA_RING_RX_SA_MASK 0x00006000 /* saddr match status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define FZA_RING_RX_SA_NONE 0x00000000 /* no match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define FZA_RING_RX_SA_ALIAS 0x00002000 /* alias address match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define FZA_RING_RX_SA_CAM 0x00004000 /* CAM entry match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define FZA_RING_RX_SA_LOCAL 0x00006000 /* link address match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* SMT (Station Management) transmit/receive descriptor ring entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct fza_ring_smt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 own; /* bit 31: ownership, bits [30:0]: unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u32 rmc; /* RMC information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 buffer; /* address of the buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 pad0; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Ownership constants.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * Only an owner is permitted to process a given ring entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * RMC transmit ring meanings are reversed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define FZA_RING_OWN_MASK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define FZA_RING_OWN_FZA 0x00000000 /* permit FZA, forbid host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define FZA_RING_OWN_HOST 0x80000000 /* permit host, forbid FZA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define FZA_RING_TX_OWN_RMC 0x80000000 /* permit RMC, forbid host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define FZA_RING_TX_OWN_HOST 0x00000000 /* permit host, forbid RMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* RMC constants. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define FZA_RING_PBC_MASK 0x00001fff /* frame length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Layout of counter buffers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct fza_counter {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u32 msw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u32 lsw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct fza_counters {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct fza_counter sys_buf; /* system buffer unavailable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct fza_counter tx_under; /* transmit underruns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct fza_counter tx_fail; /* transmit failures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct fza_counter rx_over; /* receive data overruns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct fza_counter frame_cnt; /* frame count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct fza_counter error_cnt; /* error count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct fza_counter lost_cnt; /* lost count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct fza_counter rinit_in; /* ring initialization initiated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct fza_counter rinit_rx; /* ring initialization received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct fza_counter beac_in; /* ring beacon initiated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct fza_counter dup_addr; /* duplicate address test failures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct fza_counter dup_tok; /* duplicate token detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct fza_counter purg_err; /* ring purge errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct fza_counter strip_err; /* bridge strip errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct fza_counter pct_in; /* traces initiated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct fza_counter pct_rx; /* traces received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct fza_counter lem_rej; /* LEM rejects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct fza_counter tne_rej; /* TNE expiry rejects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct fza_counter lem_event; /* LEM events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct fza_counter lct_rej; /* LCT rejects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct fza_counter conn_cmpl; /* connections completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct fza_counter el_buf; /* elasticity buffer errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Layout of command buffers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* INIT command buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * Values of default link parameters given are as obtained from a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * DEFZA-AA rev. C03 board. The board counts time in units of 80ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct fza_cmd_init {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u32 tx_mode; /* transmit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u32 hst_rx_size; /* host receive ring entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct fza_counters counters; /* counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u8 rmc_rev[4]; /* RMC revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u8 rom_rev[4]; /* ROM revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u8 fw_rev[4]; /* firmware revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u32 mop_type; /* MOP device type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u32 hst_rx; /* base of host rx descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u32 rmc_tx; /* base of RMC tx descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u32 rmc_tx_size; /* size of RMC tx descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 smt_tx; /* base of SMT tx descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 smt_tx_size; /* size of SMT tx descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 smt_rx; /* base of SMT rx descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u32 smt_rx_size; /* size of SMT rx descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u32 hw_addr[2]; /* link address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u32 def_t_req; /* default Requested TTRT (T_REQ) --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * C03: 100000 [80ns]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 def_tvx; /* default Valid Transmission Time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * (TVX) -- C03: 32768 [80ns]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u32 def_t_max; /* default Maximum TTRT (T_MAX) --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * C03: 2162688 [80ns]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u32 lem_threshold; /* default LEM threshold -- C03: 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u32 def_station_id[2]; /* default station ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u32 pmd_type_alt; /* alternative PMD type code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u32 smt_ver; /* SMT version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u32 rtoken_timeout; /* default restricted token timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * -- C03: 12500000 [80ns]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u32 ring_purger; /* default ring purger enable --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * C03: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u32 smt_ver_max; /* max SMT version ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u32 smt_ver_min; /* min SMT version ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u32 pmd_type; /* PMD type code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* INIT command PMD type codes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define FZA_PMD_TYPE_MMF 0 /* Multimode fiber */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define FZA_PMD_TYPE_TW 101 /* ThinWire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define FZA_PMD_TYPE_STP 102 /* STP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* MODCAM/RDCAM command buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define FZA_CMD_CAM_SIZE 64 /* CAM address entry count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct fza_cmd_cam {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u32 hw_addr[FZA_CMD_CAM_SIZE][2]; /* CAM address entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* PARAM command buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * Permitted ranges given are as defined by the spec and obtained from a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * DEFZA-AA rev. C03 board, respectively. The rtoken_timeout field is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * erroneously interpreted in units of ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct fza_cmd_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 loop_mode; /* loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u32 t_max; /* Maximum TTRT (T_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * def: ??? [80ns]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * C03: [t_req+1,4294967295] [80ns]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u32 t_req; /* Requested TTRT (T_REQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * def: [50000,2097151] [80ns]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * C03: [50001,t_max-1] [80ns]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u32 tvx; /* Valid Transmission Time (TVX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * def: [29375,65280] [80ns]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * C03: [29376,65279] [80ns]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u32 lem_threshold; /* LEM threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u32 station_id[2]; /* station ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u32 rtoken_timeout; /* restricted token timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * def: [0,125000000] [80ns]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * C03: [0,9999] [ms]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u32 ring_purger; /* ring purger enable: 0|1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* Loopback modes for the PARAM command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define FZA_LOOP_NORMAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define FZA_LOOP_INTERN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define FZA_LOOP_EXTERN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* MODPROM command buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct fza_cmd_modprom {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u32 llc_prom; /* LLC promiscuous enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u32 smt_prom; /* SMT promiscuous enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u32 llc_multi; /* LLC multicast promiscuous enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 llc_bcast; /* LLC broadcast promiscuous enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* SETCHAR command buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * Permitted ranges are as for the PARAM command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct fza_cmd_setchar {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 t_max; /* Maximum TTRT (T_MAX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u32 t_req; /* Requested TTRT (T_REQ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u32 tvx; /* Valid Transmission Time (TVX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u32 lem_threshold; /* LEM threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u32 rtoken_timeout; /* restricted token timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u32 ring_purger; /* ring purger enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* RDCNTR command buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct fza_cmd_rdcntr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct fza_counters counters; /* counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* STATUS command buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct fza_cmd_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u32 led_state; /* LED state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u32 rmt_state; /* ring management state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 link_state; /* link state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u32 dup_addr; /* duplicate address flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u32 ring_purger; /* ring purger state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u32 t_neg; /* negotiated TTRT [80ns] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u32 una[2]; /* upstream neighbour address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 una_timeout; /* UNA timed out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 strip_mode; /* frame strip mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 yield_mode; /* claim token yield mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u32 phy_state; /* PHY state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u32 neigh_phy; /* neighbour PHY type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u32 reject; /* reject reason */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u32 phy_lee; /* PHY link error estimate [-log10] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u32 una_old[2]; /* old upstream neighbour address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u32 rmt_mac; /* remote MAC indicated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u32 ring_err; /* ring error reason */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u32 beac_rx[2]; /* sender of last directed beacon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 un_dup_addr; /* upstream neighbr dup address flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u32 dna[2]; /* downstream neighbour address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u32 dna_old[2]; /* old downstream neighbour address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* Common command buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) union fza_cmd_buf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct fza_cmd_init init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct fza_cmd_cam cam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct fza_cmd_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct fza_cmd_modprom modprom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct fza_cmd_setchar setchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct fza_cmd_rdcntr rdcntr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct fza_cmd_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* MAC (Media Access Controller) chip packet request header constants. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Packet request header byte #0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define FZA_PRH0_FMT_TYPE_MASK 0xc0 /* type of packet, always zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define FZA_PRH0_TOK_TYPE_MASK 0x30 /* type of token required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * to send this frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define FZA_PRH0_TKN_TYPE_ANY 0x30 /* use either token type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define FZA_PRH0_TKN_TYPE_UNR 0x20 /* use an unrestricted token */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define FZA_PRH0_TKN_TYPE_RST 0x10 /* use a restricted token */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define FZA_PRH0_TKN_TYPE_IMM 0x00 /* send immediately, no token required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define FZA_PRH0_FRAME_MASK 0x08 /* type of frame to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define FZA_PRH0_FRAME_SYNC 0x08 /* send a synchronous frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define FZA_PRH0_FRAME_ASYNC 0x00 /* send an asynchronous frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define FZA_PRH0_MODE_MASK 0x04 /* send mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define FZA_PRH0_MODE_IMMED 0x04 /* an immediate mode, send regardless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * of the ring operational state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define FZA_PRH0_MODE_NORMAL 0x00 /* a normal mode, send only if ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * operational
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define FZA_PRH0_SF_MASK 0x02 /* send frame first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define FZA_PRH0_SF_FIRST 0x02 /* send this frame first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * with this token capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define FZA_PRH0_SF_NORMAL 0x00 /* treat this frame normally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define FZA_PRH0_BCN_MASK 0x01 /* beacon frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define FZA_PRH0_BCN_BEACON 0x01 /* send the frame only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * if in the beacon state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define FZA_PRH0_BCN_DATA 0x01 /* send the frame only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * if in the data state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* Packet request header byte #1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* bit 7 always zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define FZA_PRH1_SL_MASK 0x40 /* send frame last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define FZA_PRH1_SL_LAST 0x40 /* send this frame last, releasing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * the token afterwards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define FZA_PRH1_SL_NORMAL 0x00 /* treat this frame normally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define FZA_PRH1_CRC_MASK 0x20 /* CRC append */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define FZA_PRH1_CRC_NORMAL 0x20 /* calculate the CRC and append it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * as the FCS field to the frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define FZA_PRH1_CRC_SKIP 0x00 /* leave the frame as is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define FZA_PRH1_TKN_SEND_MASK 0x18 /* type of token to send after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * frame if this is the last frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define FZA_PRH1_TKN_SEND_ORIG 0x18 /* send a token of the same type as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * originally captured one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define FZA_PRH1_TKN_SEND_RST 0x10 /* send a restricted token */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define FZA_PRH1_TKN_SEND_UNR 0x08 /* send an unrestricted token */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define FZA_PRH1_TKN_SEND_NONE 0x00 /* send no token */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define FZA_PRH1_EXTRA_FS_MASK 0x07 /* send extra frame status indicators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define FZA_PRH1_EXTRA_FS_ST 0x07 /* TR RR ST II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define FZA_PRH1_EXTRA_FS_SS 0x06 /* TR RR SS II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define FZA_PRH1_EXTRA_FS_SR 0x05 /* TR RR SR II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define FZA_PRH1_EXTRA_FS_NONE1 0x04 /* TR RR II II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define FZA_PRH1_EXTRA_FS_RT 0x03 /* TR RR RT II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define FZA_PRH1_EXTRA_FS_RS 0x02 /* TR RR RS II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define FZA_PRH1_EXTRA_FS_RR 0x01 /* TR RR RR II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define FZA_PRH1_EXTRA_FS_NONE 0x00 /* TR RR II II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* Packet request header byte #2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define FZA_PRH2_NORMAL 0x00 /* always zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* PRH used for LLC frames. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define FZA_PRH0_LLC (FZA_PRH0_TKN_TYPE_UNR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define FZA_PRH1_LLC (FZA_PRH1_CRC_NORMAL | FZA_PRH1_TKN_SEND_UNR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define FZA_PRH2_LLC (FZA_PRH2_NORMAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* PRH used for SMT frames. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define FZA_PRH0_SMT (FZA_PRH0_TKN_TYPE_UNR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define FZA_PRH1_SMT (FZA_PRH1_CRC_NORMAL | FZA_PRH1_TKN_SEND_UNR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define FZA_PRH2_SMT (FZA_PRH2_NORMAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #if ((FZA_RING_RX_SIZE) < 2) || ((FZA_RING_RX_SIZE) > 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) # error FZA_RING_RX_SIZE has to be from 2 up to 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #if ((FZA_RING_TX_MODE) != 0) && ((FZA_RING_TX_MODE) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) # error FZA_RING_TX_MODE has to be either 0 or 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define FZA_RING_TX_SIZE (512 << (FZA_RING_TX_MODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct fza_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct device *bdev; /* pointer to the bus device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) const char *name; /* printable device name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) void __iomem *mmio; /* MMIO ioremap cookie */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct fza_regs __iomem *regs; /* pointer to FZA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct sk_buff *rx_skbuff[FZA_RING_RX_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* all skbs assigned to the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * receive descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) dma_addr_t rx_dma[FZA_RING_RX_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* their corresponding DMA addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct fza_ring_cmd __iomem *ring_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* pointer to the command descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int ring_cmd_index; /* index to the command descriptor ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * for the next command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct fza_ring_uns __iomem *ring_uns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* pointer to the unsolicited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * descriptor ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) int ring_uns_index; /* index to the unsolicited descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * ring for the next event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct fza_ring_rmc_tx __iomem *ring_rmc_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* pointer to the RMC transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * descriptor ring (obtained from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * INIT command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) int ring_rmc_tx_size; /* number of entries in the RMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * transmit descriptor ring (obtained
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * from the INIT command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) int ring_rmc_tx_index; /* index to the RMC transmit descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * ring for the next transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int ring_rmc_txd_index; /* index to the RMC transmit descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * ring for the next transmit done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * acknowledge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct fza_ring_hst_rx __iomem *ring_hst_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* pointer to the host receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * descriptor ring (obtained from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * INIT command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int ring_hst_rx_size; /* number of entries in the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * receive descriptor ring (set by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * INIT command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) int ring_hst_rx_index; /* index to the host receive descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * ring for the next transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct fza_ring_smt __iomem *ring_smt_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* pointer to the SMT transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * descriptor ring (obtained from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * INIT command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int ring_smt_tx_size; /* number of entries in the SMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * transmit descriptor ring (obtained
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * from the INIT command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) int ring_smt_tx_index; /* index to the SMT transmit descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * ring for the next transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct fza_ring_smt __iomem *ring_smt_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* pointer to the SMT transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * descriptor ring (obtained from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * INIT command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) int ring_smt_rx_size; /* number of entries in the SMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * receive descriptor ring (obtained
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * from the INIT command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) int ring_smt_rx_index; /* index to the SMT receive descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * ring for the next transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct fza_buffer_tx __iomem *buffer_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* pointer to the RMC transmit buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) uint state; /* adapter expected state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) spinlock_t lock; /* for device & private data access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) uint int_mask; /* interrupt source selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) int cmd_done_flag; /* command completion trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) wait_queue_head_t cmd_done_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) int state_chg_flag; /* state change trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) wait_queue_head_t state_chg_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct timer_list reset_timer; /* RESET time-out trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) int timer_state; /* RESET trigger state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) int queue_active; /* whether to enable queueing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct net_device_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) uint irq_count_flush_tx; /* transmit flush irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) uint irq_count_uns_poll; /* unsolicited event irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) uint irq_count_smt_tx_poll; /* SMT transmit irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) uint irq_count_rx_poll; /* host receive irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) uint irq_count_tx_done; /* transmit done irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) uint irq_count_cmd_done; /* command done irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) uint irq_count_state_chg; /* state change irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) uint irq_count_link_st_chg; /* link status change irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) uint t_max; /* T_MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) uint t_req; /* T_REQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) uint tvx; /* TVX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) uint lem_threshold; /* LEM threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) uint station_id[2]; /* station ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) uint rtoken_timeout; /* restricted token timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) uint ring_purger; /* ring purger enable flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct fza_fddihdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) u8 pa[2]; /* preamble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u8 sd; /* starting delimiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct fddihdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) } __packed;
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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