^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Ethernet driver for the WIZnet W5300 chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008-2009 WIZnet Co.,Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011 Taehun Kim <kth3321 <at> gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2012 Mike Sinkovsky <msink@permonline.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_data/wiznet.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DRV_NAME "w5300"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRV_VERSION "2012-04-04"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MODULE_DESCRIPTION("WIZnet W5300 Ethernet driver v"DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_AUTHOR("Mike Sinkovsky <msink@permonline.ru>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MODULE_ALIAS("platform:"DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define W5300_MR 0x0000 /* Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MR_DBW (1 << 15) /* Data bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MR_MPF (1 << 14) /* Mac layer pause frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MR_WDF(n) (((n)&7)<<11) /* Write data fetch time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MR_RDH (1 << 10) /* Read data hold time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MR_FS (1 << 8) /* FIFO swap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MR_RST (1 << 7) /* S/W reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MR_PB (1 << 4) /* Ping block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MR_DBS (1 << 2) /* Data bus swap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MR_IND (1 << 0) /* Indirect mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define W5300_IR 0x0002 /* Interrupt Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define W5300_IMR 0x0004 /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IR_S0 0x0001 /* S0 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define W5300_SHARL 0x0008 /* Source MAC address (0123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define W5300_SHARH 0x000c /* Source MAC address (45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define W5300_TMSRL 0x0020 /* Transmit Memory Size (0123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define W5300_TMSRH 0x0024 /* Transmit Memory Size (4567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define W5300_RMSRL 0x0028 /* Receive Memory Size (0123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define W5300_RMSRH 0x002c /* Receive Memory Size (4567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define W5300_MTYPE 0x0030 /* Memory Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define W5300_IDR 0x00fe /* Chip ID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IDR_W5300 0x5300 /* =0x5300 for WIZnet W5300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define W5300_S0_MR 0x0200 /* S0 Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define S0_MR_CLOSED 0x0000 /* Close mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define S0_MR_MACRAW 0x0004 /* MAC RAW mode (promiscuous) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define S0_MR_MACRAW_MF 0x0044 /* MAC RAW mode (filtered) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define W5300_S0_CR 0x0202 /* S0 Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define S0_CR_OPEN 0x0001 /* OPEN command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define S0_CR_CLOSE 0x0010 /* CLOSE command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define S0_CR_SEND 0x0020 /* SEND command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define S0_CR_RECV 0x0040 /* RECV command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define W5300_S0_IMR 0x0204 /* S0 Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define W5300_S0_IR 0x0206 /* S0 Interrupt Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define S0_IR_RECV 0x0004 /* Receive interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define S0_IR_SENDOK 0x0010 /* Send OK interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define W5300_S0_SSR 0x0208 /* S0 Socket Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define W5300_S0_TX_WRSR 0x0220 /* S0 TX Write Size Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define W5300_S0_TX_FSR 0x0224 /* S0 TX Free Size Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define W5300_S0_RX_RSR 0x0228 /* S0 Received data Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define W5300_S0_TX_FIFO 0x022e /* S0 Transmit FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define W5300_S0_RX_FIFO 0x0230 /* S0 Receive FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define W5300_REGS_LEN 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Device driver private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct w5300_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) bool indirect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u16 (*read) (struct w5300_priv *priv, u16 addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void (*write)(struct w5300_priv *priv, u16 addr, u16 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int link_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int link_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct net_device *ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) bool promisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Lowlevel I/O functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ***********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * In direct address mode host system can directly access W5300 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * after mapping to Memory-Mapped I/O space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * 0x400 bytes are required for memory space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline u16 w5300_read_direct(struct w5300_priv *priv, u16 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return ioread16(priv->base + (addr << CONFIG_WIZNET_BUS_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline void w5300_write_direct(struct w5300_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u16 addr, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) iowrite16(data, priv->base + (addr << CONFIG_WIZNET_BUS_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * In indirect address mode host system indirectly accesses registers by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * using Indirect Mode Address Register (IDM_AR) and Indirect Mode Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Register (IDM_DR), which are directly mapped to Memory-Mapped I/O space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * Mode Register (MR) is directly accessible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * Only 0x06 bytes are required for memory space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define W5300_IDM_AR 0x0002 /* Indirect Mode Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define W5300_IDM_DR 0x0004 /* Indirect Mode Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static u16 w5300_read_indirect(struct w5300_priv *priv, u16 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) spin_lock_irqsave(&priv->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) w5300_write_direct(priv, W5300_IDM_AR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) data = w5300_read_direct(priv, W5300_IDM_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) spin_unlock_irqrestore(&priv->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void w5300_write_indirect(struct w5300_priv *priv, u16 addr, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) spin_lock_irqsave(&priv->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) w5300_write_direct(priv, W5300_IDM_AR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) w5300_write_direct(priv, W5300_IDM_DR, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) spin_unlock_irqrestore(&priv->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #if defined(CONFIG_WIZNET_BUS_DIRECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define w5300_read w5300_read_direct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define w5300_write w5300_write_direct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #elif defined(CONFIG_WIZNET_BUS_INDIRECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define w5300_read w5300_read_indirect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define w5300_write w5300_write_indirect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #else /* CONFIG_WIZNET_BUS_ANY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define w5300_read priv->read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define w5300_write priv->write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static u32 w5300_read32(struct w5300_priv *priv, u16 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) data = w5300_read(priv, addr) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) data |= w5300_read(priv, addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void w5300_write32(struct w5300_priv *priv, u16 addr, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) w5300_write(priv, addr, data >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) w5300_write(priv, addr + 2, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int w5300_command(struct w5300_priv *priv, u16 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned long timeout = jiffies + msecs_to_jiffies(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) w5300_write(priv, W5300_S0_CR, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) while (w5300_read(priv, W5300_S0_CR) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static void w5300_read_frame(struct w5300_priv *priv, u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u16 fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) for (i = 0; i < len; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) fifo = w5300_read(priv, W5300_S0_RX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *buf++ = fifo >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) *buf++ = fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) fifo = w5300_read(priv, W5300_S0_RX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) fifo = w5300_read(priv, W5300_S0_RX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static void w5300_write_frame(struct w5300_priv *priv, u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u16 fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) for (i = 0; i < len; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) fifo = *buf++ << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) fifo |= *buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) w5300_write(priv, W5300_S0_TX_FIFO, fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) w5300_write32(priv, W5300_S0_TX_WRSR, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void w5300_write_macaddr(struct w5300_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct net_device *ndev = priv->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) w5300_write32(priv, W5300_SHARL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ndev->dev_addr[0] << 24 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ndev->dev_addr[1] << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ndev->dev_addr[2] << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ndev->dev_addr[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) w5300_write(priv, W5300_SHARH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ndev->dev_addr[4] << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ndev->dev_addr[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void w5300_hw_reset(struct w5300_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) w5300_write_direct(priv, W5300_MR, MR_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) mdelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) w5300_write_direct(priv, W5300_MR, priv->indirect ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MR_WDF(7) | MR_PB | MR_IND :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MR_WDF(7) | MR_PB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) w5300_write(priv, W5300_IMR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) w5300_write_macaddr(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Configure 128K of internal memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * as 64K RX fifo and 64K TX fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) w5300_write32(priv, W5300_RMSRL, 64 << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) w5300_write32(priv, W5300_RMSRH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) w5300_write32(priv, W5300_TMSRL, 64 << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) w5300_write32(priv, W5300_TMSRH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) w5300_write(priv, W5300_MTYPE, 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void w5300_hw_start(struct w5300_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) w5300_write(priv, W5300_S0_MR, priv->promisc ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) S0_MR_MACRAW : S0_MR_MACRAW_MF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) w5300_command(priv, S0_CR_OPEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) w5300_write(priv, W5300_S0_IMR, S0_IR_RECV | S0_IR_SENDOK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) w5300_write(priv, W5300_IMR, IR_S0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static void w5300_hw_close(struct w5300_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) w5300_write(priv, W5300_IMR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) w5300_command(priv, S0_CR_CLOSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /***********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Device driver functions / callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ***********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static void w5300_get_drvinfo(struct net_device *ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) strlcpy(info->version, DRV_VERSION, sizeof(info->version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) strlcpy(info->bus_info, dev_name(ndev->dev.parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static u32 w5300_get_link(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct w5300_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (gpio_is_valid(priv->link_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return !!gpio_get_value(priv->link_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static u32 w5300_get_msglevel(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct w5300_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return priv->msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static void w5300_set_msglevel(struct net_device *ndev, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct w5300_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) priv->msg_enable = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int w5300_get_regs_len(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return W5300_REGS_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static void w5300_get_regs(struct net_device *ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct ethtool_regs *regs, void *_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct w5300_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u8 *buf = _buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) regs->version = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) for (addr = 0; addr < W5300_REGS_LEN; addr += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) switch (addr & 0x23f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case W5300_S0_TX_FIFO: /* cannot read TX_FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case W5300_S0_RX_FIFO: /* cannot read RX_FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) data = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) data = w5300_read(priv, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) *buf++ = data >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) *buf++ = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void w5300_tx_timeout(struct net_device *ndev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct w5300_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) netif_stop_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) w5300_hw_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) w5300_hw_start(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ndev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) netif_trans_update(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) netif_wake_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static netdev_tx_t w5300_start_tx(struct sk_buff *skb, struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct w5300_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) netif_stop_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) w5300_write_frame(priv, skb->data, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ndev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ndev->stats.tx_bytes += skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) netif_dbg(priv, tx_queued, ndev, "tx queued\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) w5300_command(priv, S0_CR_SEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int w5300_napi_poll(struct napi_struct *napi, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct w5300_priv *priv = container_of(napi, struct w5300_priv, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct net_device *ndev = priv->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int rx_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u16 rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) for (rx_count = 0; rx_count < budget; rx_count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u32 rx_fifo_len = w5300_read32(priv, W5300_S0_RX_RSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (rx_fifo_len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) rx_len = w5300_read(priv, W5300_S0_RX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) skb = netdev_alloc_skb_ip_align(ndev, roundup(rx_len, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (unlikely(!skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) for (i = 0; i < rx_fifo_len; i += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) w5300_read(priv, W5300_S0_RX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ndev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) skb_put(skb, rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) w5300_read_frame(priv, skb->data, rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) skb->protocol = eth_type_trans(skb, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) netif_receive_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ndev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ndev->stats.rx_bytes += rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (rx_count < budget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) napi_complete_done(napi, rx_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) w5300_write(priv, W5300_IMR, IR_S0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return rx_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static irqreturn_t w5300_interrupt(int irq, void *ndev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct net_device *ndev = ndev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct w5300_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int ir = w5300_read(priv, W5300_S0_IR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (!ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) w5300_write(priv, W5300_S0_IR, ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (ir & S0_IR_SENDOK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) netif_dbg(priv, tx_done, ndev, "tx done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) netif_wake_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (ir & S0_IR_RECV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (napi_schedule_prep(&priv->napi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) w5300_write(priv, W5300_IMR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) __napi_schedule(&priv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static irqreturn_t w5300_detect_link(int irq, void *ndev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct net_device *ndev = ndev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct w5300_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (netif_running(ndev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (gpio_get_value(priv->link_gpio) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) netif_info(priv, link, ndev, "link is up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) netif_carrier_on(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) netif_info(priv, link, ndev, "link is down\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) netif_carrier_off(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static void w5300_set_rx_mode(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct w5300_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) bool set_promisc = (ndev->flags & IFF_PROMISC) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (priv->promisc != set_promisc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) priv->promisc = set_promisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) w5300_hw_start(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int w5300_set_macaddr(struct net_device *ndev, void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct w5300_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct sockaddr *sock_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (!is_valid_ether_addr(sock_addr->sa_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return -EADDRNOTAVAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) memcpy(ndev->dev_addr, sock_addr->sa_data, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) w5300_write_macaddr(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int w5300_open(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct w5300_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) netif_info(priv, ifup, ndev, "enabling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) w5300_hw_start(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) napi_enable(&priv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) netif_start_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (!gpio_is_valid(priv->link_gpio) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) gpio_get_value(priv->link_gpio) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) netif_carrier_on(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int w5300_stop(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct w5300_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) netif_info(priv, ifdown, ndev, "shutting down\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) w5300_hw_close(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) netif_carrier_off(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) netif_stop_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) napi_disable(&priv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static const struct ethtool_ops w5300_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .get_drvinfo = w5300_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .get_msglevel = w5300_get_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .set_msglevel = w5300_set_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .get_link = w5300_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .get_regs_len = w5300_get_regs_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .get_regs = w5300_get_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static const struct net_device_ops w5300_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .ndo_open = w5300_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .ndo_stop = w5300_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .ndo_start_xmit = w5300_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .ndo_tx_timeout = w5300_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .ndo_set_rx_mode = w5300_set_rx_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .ndo_set_mac_address = w5300_set_macaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static int w5300_hw_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct wiznet_platform_data *data = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct net_device *ndev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct w5300_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) const char *name = netdev_name(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) int mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (data && is_valid_ether_addr(data->mac_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) memcpy(ndev->dev_addr, data->mac_addr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) eth_hw_addr_random(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) priv->base = devm_ioremap_resource(&pdev->dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) mem_size = resource_size(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) spin_lock_init(&priv->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) priv->indirect = mem_size < W5300_BUS_DIRECT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (priv->indirect) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) priv->read = w5300_read_indirect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) priv->write = w5300_write_indirect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) priv->read = w5300_read_direct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) priv->write = w5300_write_direct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) w5300_hw_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (w5300_read(priv, W5300_IDR) != IDR_W5300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ret = request_irq(irq, w5300_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) IRQ_TYPE_LEVEL_LOW, name, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) priv->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) priv->link_gpio = data ? data->link_gpio : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (gpio_is_valid(priv->link_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) char *link_name = devm_kzalloc(&pdev->dev, 16, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (!link_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) snprintf(link_name, 16, "%s-link", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) priv->link_irq = gpio_to_irq(priv->link_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (request_any_context_irq(priv->link_irq, w5300_detect_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) link_name, priv->ndev) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) priv->link_gpio = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) netdev_info(ndev, "at 0x%llx irq %d\n", (u64)mem->start, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int w5300_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct w5300_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct net_device *ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ndev = alloc_etherdev(sizeof(*priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (!ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) SET_NETDEV_DEV(ndev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) platform_set_drvdata(pdev, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) priv->ndev = ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ndev->netdev_ops = &w5300_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ndev->ethtool_ops = &w5300_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ndev->watchdog_timeo = HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) netif_napi_add(ndev, &priv->napi, w5300_napi_poll, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* This chip doesn't support VLAN packets with normal MTU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * so disable VLAN for this device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ndev->features |= NETIF_F_VLAN_CHALLENGED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) err = register_netdev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) err = w5300_hw_probe(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) goto err_hw_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) err_hw_probe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) unregister_netdev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) err_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) free_netdev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int w5300_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct net_device *ndev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct w5300_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) w5300_hw_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) free_irq(priv->irq, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (gpio_is_valid(priv->link_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) free_irq(priv->link_irq, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) unregister_netdev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) free_netdev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static int w5300_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct net_device *ndev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct w5300_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (netif_running(ndev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) netif_carrier_off(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) netif_device_detach(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) w5300_hw_close(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int w5300_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct net_device *ndev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct w5300_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (!netif_running(ndev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) w5300_hw_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) w5300_hw_start(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) netif_device_attach(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (!gpio_is_valid(priv->link_gpio) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) gpio_get_value(priv->link_gpio) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) netif_carrier_on(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static SIMPLE_DEV_PM_OPS(w5300_pm_ops, w5300_suspend, w5300_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static struct platform_driver w5300_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .pm = &w5300_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .probe = w5300_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .remove = w5300_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) module_platform_driver(w5300_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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