^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * File: via-velocity.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Purpose: Header file to define driver's private structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Author: Chuang Liang-Shing, AJ Jiang
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Date: Jan 24, 2003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifndef VELOCITY_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define VELOCITY_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define VELOCITY_TX_CSUM_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define VELOCITY_NAME "via-velocity"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define VELOCITY_FULL_DRV_NAM "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define VELOCITY_VERSION "1.15"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VELOCITY_IO_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define VELOCITY_NAPI_WEIGHT 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PKT_BUF_SZ 1540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MAX_UNITS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OPTION_DEFAULT { [0 ... MAX_UNITS-1] = -1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REV_ID_VT6110 (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BYTE_REG_BITS_ON(x,p) do { writeb(readb((p))|(x),(p));} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define WORD_REG_BITS_ON(x,p) do { writew(readw((p))|(x),(p));} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DWORD_REG_BITS_ON(x,p) do { writel(readl((p))|(x),(p));} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BYTE_REG_BITS_IS_ON(x,p) (readb((p)) & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define WORD_REG_BITS_IS_ON(x,p) (readw((p)) & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DWORD_REG_BITS_IS_ON(x,p) (readl((p)) & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BYTE_REG_BITS_OFF(x,p) do { writeb(readb((p)) & (~(x)),(p));} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define WORD_REG_BITS_OFF(x,p) do { writew(readw((p)) & (~(x)),(p));} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DWORD_REG_BITS_OFF(x,p) do { writel(readl((p)) & (~(x)),(p));} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BYTE_REG_BITS_SET(x,m,p) do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define WORD_REG_BITS_SET(x,m,p) do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DWORD_REG_BITS_SET(x,m,p) do { writel( (readl((p)) & (~(m)))|(x),(p));} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VAR_USED(p) do {(p)=(p);} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Purpose: Structures for MAX RX/TX descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define B_OWNED_BY_CHIP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define B_OWNED_BY_HOST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Bits in the RSR0 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RSR_DETAG cpu_to_le16(0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RSR_SNTAG cpu_to_le16(0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RSR_RXER cpu_to_le16(0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RSR_RL cpu_to_le16(0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RSR_CE cpu_to_le16(0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RSR_FAE cpu_to_le16(0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RSR_CRC cpu_to_le16(0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RSR_VIDM cpu_to_le16(0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Bits in the RSR1 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RSR_RXOK cpu_to_le16(0x8000) // rx OK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RSR_PFT cpu_to_le16(0x4000) // Perfect filtering address match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RSR_MAR cpu_to_le16(0x2000) // MAC accept multicast address packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RSR_BAR cpu_to_le16(0x1000) // MAC accept broadcast address packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RSR_PHY cpu_to_le16(0x0800) // MAC accept physical address packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RSR_VTAG cpu_to_le16(0x0400) // 802.1p/1q tagging packet indicator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RSR_STP cpu_to_le16(0x0200) // start of packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RSR_EDP cpu_to_le16(0x0100) // end of packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Bits in the CSM register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CSM_IPOK 0x40 //IP Checksum validation ok
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CSM_TUPOK 0x20 //TCP/UDP Checksum validation ok
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CSM_FRAG 0x10 //Fragment IP datagram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CSM_IPKT 0x04 //Received an IP packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CSM_TCPKT 0x02 //Received a TCP packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CSM_UDPKT 0x01 //Received a UDP packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Bits in the TSR0 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TSR0_ABT cpu_to_le16(0x0080) // Tx abort because of excessive collision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TSR0_OWT cpu_to_le16(0x0040) // Jumbo frame Tx abort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TSR0_OWC cpu_to_le16(0x0020) // Out of window collision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TSR0_COLS cpu_to_le16(0x0010) // experience collision in this transmit event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TSR0_NCR3 cpu_to_le16(0x0008) // collision retry counter[3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TSR0_NCR2 cpu_to_le16(0x0004) // collision retry counter[2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TSR0_NCR1 cpu_to_le16(0x0002) // collision retry counter[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TSR0_NCR0 cpu_to_le16(0x0001) // collision retry counter[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TSR0_TERR cpu_to_le16(0x8000) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TSR0_FDX cpu_to_le16(0x4000) // current transaction is serviced by full duplex mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TSR0_GMII cpu_to_le16(0x2000) // current transaction is serviced by GMII mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TSR0_LNKFL cpu_to_le16(0x1000) // packet serviced during link down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TSR0_SHDN cpu_to_le16(0x0400) // shutdown case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TSR0_CRS cpu_to_le16(0x0200) // carrier sense lost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TSR0_CDH cpu_to_le16(0x0100) // AQE test fail (CD heartbeat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) // Bits in the TCR0 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TCR0_TIC 0x80 // assert interrupt immediately while descriptor has been send complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TCR0_PIC 0x40 // priority interrupt request, INA# is issued over adaptive interrupt scheme
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TCR0_VETAG 0x20 // enable VLAN tag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TCR0_IPCK 0x10 // request IP checksum calculation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TCR0_UDPCK 0x08 // request UDP checksum calculation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TCR0_TCPCK 0x04 // request TCP checksum calculation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TCR0_JMBO 0x02 // indicate a jumbo packet in GMAC side
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TCR0_CRC 0x01 // disable CRC generation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TCPLS_NORMAL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TCPLS_START 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TCPLS_END 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TCPLS_MED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) // max transmit or receive buffer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CB_RX_BUF_SIZE 2048UL // max buffer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) // NOTE: must be multiple of 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CB_MAX_RD_NUM 512 // MAX # of RD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CB_MAX_TD_NUM 256 // MAX # of TD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CB_INIT_RD_NUM_3119 128 // init # of RD, for setup VT3119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CB_INIT_TD_NUM_3119 64 // init # of TD, for setup VT3119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CB_INIT_RD_NUM 128 // init # of RD, for setup default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CB_INIT_TD_NUM 64 // init # of TD, for setup default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) // for 3119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CB_TD_RING_NUM 4 // # of TD rings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CB_MAX_SEG_PER_PKT 7 // max data seg per packet (Tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * If collisions excess 15 times , tx will abort, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * if tx fifo underflow, tx will fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * we should try to resend it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CB_MAX_TX_ABORT_RETRY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Receive descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct rdesc0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) __le16 RSR; /* Receive status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) __le16 len; /* bits 0--13; bit 15 - owner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct rdesc1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) __le16 PQTAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u8 CSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u8 IPKT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) RX_INTEN = cpu_to_le16(0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct rx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct rdesc0 rdesc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct rdesc1 rdesc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) __le32 pa_low; /* Low 32 bit PCI address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) __le16 pa_high; /* Next 16 bit PCI address (48 total) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __le16 size; /* bits 0--14 - frame size, bit 15 - enable int. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Transmit descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct tdesc0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) __le16 TSR; /* Transmit status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) __le16 len; /* bits 0--13 - size of frame, bit 15 - owner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct tdesc1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __le16 vlan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 TCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u8 cmd; /* bits 0--1 - TCPLS, bits 4--7 - CMDZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) TD_QUEUE = cpu_to_le16(0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct td_buf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) __le32 pa_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) __le16 pa_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) __le16 size; /* bits 0--13 - size, bit 15 - queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct tx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct tdesc0 tdesc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct tdesc1 tdesc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct td_buf td_buf[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct velocity_rd_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dma_addr_t skb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * Used to track transmit side buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct velocity_td_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int nskb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dma_addr_t skb_dma[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) enum velocity_owner {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) OWNED_BY_HOST = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) OWNED_BY_NIC = cpu_to_le16(0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * MAC registers and macros.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MCAM_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define VCAM_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TX_QUEUE_NO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MAX_HW_MIB_COUNTER 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define VELOCITY_MIN_MTU (64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define VELOCITY_MAX_MTU (9000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Registers in the MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MAC_REG_PAR 0x00 // physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MAC_REG_RCR 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MAC_REG_TCR 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MAC_REG_CR0_SET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MAC_REG_CR1_SET 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define MAC_REG_CR2_SET 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define MAC_REG_CR3_SET 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define MAC_REG_CR0_CLR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MAC_REG_CR1_CLR 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define MAC_REG_CR2_CLR 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define MAC_REG_CR3_CLR 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define MAC_REG_MAR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MAC_REG_CAM 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define MAC_REG_DEC_BASE_HI 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define MAC_REG_DBF_BASE_HI 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define MAC_REG_ISR_CTL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define MAC_REG_ISR_HOTMR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define MAC_REG_ISR_TSUPTHR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define MAC_REG_ISR_RSUPTHR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define MAC_REG_ISR_CTL1 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define MAC_REG_TXE_SR 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define MAC_REG_RXE_SR 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define MAC_REG_ISR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define MAC_REG_ISR0 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define MAC_REG_ISR1 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define MAC_REG_ISR2 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define MAC_REG_ISR3 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define MAC_REG_IMR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define MAC_REG_IMR0 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define MAC_REG_IMR1 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define MAC_REG_IMR2 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define MAC_REG_IMR3 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define MAC_REG_TDCSR_SET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define MAC_REG_RDCSR_SET 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define MAC_REG_TDCSR_CLR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define MAC_REG_RDCSR_CLR 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define MAC_REG_RDBASE_LO 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define MAC_REG_RDINDX 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define MAC_REG_TDBASE_LO 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define MAC_REG_RDCSIZE 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define MAC_REG_TDCSIZE 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define MAC_REG_TDINDX 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define MAC_REG_TDIDX0 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define MAC_REG_TDIDX1 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define MAC_REG_TDIDX2 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define MAC_REG_TDIDX3 0x5A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define MAC_REG_PAUSE_TIMER 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define MAC_REG_RBRDU 0x5E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define MAC_REG_FIFO_TEST0 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define MAC_REG_FIFO_TEST1 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define MAC_REG_CAMADDR 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define MAC_REG_CAMCR 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define MAC_REG_GFTEST 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define MAC_REG_FTSTCMD 0x6B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define MAC_REG_MIICFG 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define MAC_REG_MIISR 0x6D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define MAC_REG_PHYSR0 0x6E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define MAC_REG_PHYSR1 0x6F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define MAC_REG_MIICR 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define MAC_REG_MIIADR 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define MAC_REG_MIIDATA 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define MAC_REG_SOFT_TIMER0 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define MAC_REG_SOFT_TIMER1 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define MAC_REG_CFGA 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define MAC_REG_CFGB 0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define MAC_REG_CFGC 0x7A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define MAC_REG_CFGD 0x7B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define MAC_REG_DCFG0 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define MAC_REG_DCFG1 0x7D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define MAC_REG_MCFG0 0x7E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define MAC_REG_MCFG1 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define MAC_REG_TBIST 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define MAC_REG_RBIST 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define MAC_REG_PMCC 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define MAC_REG_STICKHW 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define MAC_REG_MIBCR 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define MAC_REG_EERSV 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define MAC_REG_REVID 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define MAC_REG_MIBREAD 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define MAC_REG_BPMA 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define MAC_REG_EEWR_DATA 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define MAC_REG_BPMD_WR 0x8F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define MAC_REG_BPCMD 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define MAC_REG_BPMD_RD 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define MAC_REG_EECHKSUM 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define MAC_REG_EECSR 0x93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define MAC_REG_EERD_DATA 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define MAC_REG_EADDR 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define MAC_REG_EMBCMD 0x97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define MAC_REG_JMPSR0 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define MAC_REG_JMPSR1 0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define MAC_REG_JMPSR2 0x9A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define MAC_REG_JMPSR3 0x9B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define MAC_REG_CHIPGSR 0x9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define MAC_REG_TESTCFG 0x9D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define MAC_REG_DEBUG 0x9E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define MAC_REG_CHIPGCR 0x9F /* Chip Operation and Diagnostic Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define MAC_REG_WOLCR0_SET 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define MAC_REG_WOLCR1_SET 0xA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define MAC_REG_PWCFG_SET 0xA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define MAC_REG_WOLCFG_SET 0xA3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define MAC_REG_WOLCR0_CLR 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define MAC_REG_WOLCR1_CLR 0xA5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define MAC_REG_PWCFG_CLR 0xA6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define MAC_REG_WOLCFG_CLR 0xA7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define MAC_REG_WOLSR0_SET 0xA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define MAC_REG_WOLSR1_SET 0xA9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define MAC_REG_WOLSR0_CLR 0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define MAC_REG_WOLSR1_CLR 0xAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define MAC_REG_PATRN_CRC0 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define MAC_REG_PATRN_CRC1 0xB2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define MAC_REG_PATRN_CRC2 0xB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define MAC_REG_PATRN_CRC3 0xB6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define MAC_REG_PATRN_CRC4 0xB8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define MAC_REG_PATRN_CRC5 0xBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define MAC_REG_PATRN_CRC6 0xBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define MAC_REG_PATRN_CRC7 0xBE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define MAC_REG_BYTEMSK0_0 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define MAC_REG_BYTEMSK0_1 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define MAC_REG_BYTEMSK0_2 0xC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define MAC_REG_BYTEMSK0_3 0xCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define MAC_REG_BYTEMSK1_0 0xD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define MAC_REG_BYTEMSK1_1 0xD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define MAC_REG_BYTEMSK1_2 0xD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define MAC_REG_BYTEMSK1_3 0xDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define MAC_REG_BYTEMSK2_0 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define MAC_REG_BYTEMSK2_1 0xE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define MAC_REG_BYTEMSK2_2 0xE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define MAC_REG_BYTEMSK2_3 0xEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define MAC_REG_BYTEMSK3_0 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define MAC_REG_BYTEMSK3_1 0xF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define MAC_REG_BYTEMSK3_2 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define MAC_REG_BYTEMSK3_3 0xFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * Bits in the RCR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define RCR_AS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define RCR_AP 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define RCR_AL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define RCR_PROM 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define RCR_AB 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define RCR_AM 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define RCR_AR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define RCR_SEP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * Bits in the TCR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define TCR_TB2BDIS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define TCR_COLTMC1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define TCR_COLTMC0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define TCR_LB1 0x02 /* loopback[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define TCR_LB0 0x01 /* loopback[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * Bits in the CR0 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define CR0_TXON 0x00000008UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define CR0_RXON 0x00000004UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define CR0_STOP 0x00000002UL /* stop MAC, default = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define CR0_STRT 0x00000001UL /* start MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define CR0_SFRST 0x00008000UL /* software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define CR0_TM1EN 0x00004000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define CR0_TM0EN 0x00002000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define CR0_DPOLL 0x00000800UL /* disable rx/tx auto polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define CR0_DISAU 0x00000100UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define CR0_XONEN 0x00800000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define CR0_FDXTFCEN 0x00400000UL /* full-duplex TX flow control enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define CR0_FDXRFCEN 0x00200000UL /* full-duplex RX flow control enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define CR0_HDXFCEN 0x00100000UL /* half-duplex flow control enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define CR0_XHITH1 0x00080000UL /* TX XON high threshold 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define CR0_XHITH0 0x00040000UL /* TX XON high threshold 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define CR0_XLTH1 0x00020000UL /* TX pause frame low threshold 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define CR0_XLTH0 0x00010000UL /* TX pause frame low threshold 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define CR0_GSPRST 0x80000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define CR0_FORSRST 0x40000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define CR0_FPHYRST 0x20000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define CR0_DIAG 0x10000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define CR0_INTPCTL 0x04000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define CR0_GINTMSK1 0x02000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define CR0_GINTMSK0 0x01000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * Bits in the CR1 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define CR1_SFRST 0x80 /* software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define CR1_TM1EN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define CR1_TM0EN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define CR1_DPOLL 0x08 /* disable rx/tx auto polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define CR1_DISAU 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * Bits in the CR2 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define CR2_XONEN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define CR2_FDXTFCEN 0x40 /* full-duplex TX flow control enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define CR2_FDXRFCEN 0x20 /* full-duplex RX flow control enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define CR2_HDXFCEN 0x10 /* half-duplex flow control enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define CR2_XHITH1 0x08 /* TX XON high threshold 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define CR2_XHITH0 0x04 /* TX XON high threshold 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define CR2_XLTH1 0x02 /* TX pause frame low threshold 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define CR2_XLTH0 0x01 /* TX pause frame low threshold 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * Bits in the CR3 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define CR3_GSPRST 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define CR3_FORSRST 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define CR3_FPHYRST 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define CR3_DIAG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define CR3_INTPCTL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define CR3_GINTMSK1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define CR3_GINTMSK0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define ISRCTL_UDPINT 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define ISRCTL_TSUPDIS 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define ISRCTL_RSUPDIS 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define ISRCTL_PMSK1 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define ISRCTL_PMSK0 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define ISRCTL_INTPD 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define ISRCTL_HCRLD 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define ISRCTL_SCRLD 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * Bits in the ISR_CTL1 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define ISRCTL1_UDPINT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define ISRCTL1_TSUPDIS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define ISRCTL1_RSUPDIS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define ISRCTL1_PMSK1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define ISRCTL1_PMSK0 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define ISRCTL1_INTPD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define ISRCTL1_HCRLD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define ISRCTL1_SCRLD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * Bits in the TXE_SR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define TXESR_TFDBS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define TXESR_TDWBS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define TXESR_TDRBS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define TXESR_TDSTR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * Bits in the RXE_SR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define RXESR_RFDBS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define RXESR_RDWBS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define RXESR_RDRBS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define RXESR_RDSTR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * Bits in the ISR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define ISR_ISR3 0x80000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define ISR_ISR2 0x40000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define ISR_ISR1 0x20000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define ISR_ISR0 0x10000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define ISR_TXSTLI 0x02000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define ISR_RXSTLI 0x01000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define ISR_HFLD 0x00800000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define ISR_UDPI 0x00400000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define ISR_MIBFI 0x00200000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define ISR_SHDNI 0x00100000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define ISR_PHYI 0x00080000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define ISR_PWEI 0x00040000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define ISR_TMR1I 0x00020000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define ISR_TMR0I 0x00010000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define ISR_SRCI 0x00008000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define ISR_LSTPEI 0x00004000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define ISR_LSTEI 0x00002000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define ISR_OVFI 0x00001000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define ISR_FLONI 0x00000800UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define ISR_RACEI 0x00000400UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define ISR_TXWB1I 0x00000200UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define ISR_TXWB0I 0x00000100UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define ISR_PTX3I 0x00000080UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define ISR_PTX2I 0x00000040UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define ISR_PTX1I 0x00000020UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define ISR_PTX0I 0x00000010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define ISR_PTXI 0x00000008UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define ISR_PRXI 0x00000004UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define ISR_PPTXI 0x00000002UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define ISR_PPRXI 0x00000001UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * Bits in the IMR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define IMR_TXSTLM 0x02000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define IMR_UDPIM 0x00400000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define IMR_MIBFIM 0x00200000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define IMR_SHDNIM 0x00100000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define IMR_PHYIM 0x00080000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define IMR_PWEIM 0x00040000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define IMR_TMR1IM 0x00020000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define IMR_TMR0IM 0x00010000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define IMR_SRCIM 0x00008000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define IMR_LSTPEIM 0x00004000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define IMR_LSTEIM 0x00002000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define IMR_OVFIM 0x00001000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define IMR_FLONIM 0x00000800UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define IMR_RACEIM 0x00000400UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define IMR_TXWB1IM 0x00000200UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define IMR_TXWB0IM 0x00000100UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define IMR_PTX3IM 0x00000080UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define IMR_PTX2IM 0x00000040UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define IMR_PTX1IM 0x00000020UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define IMR_PTX0IM 0x00000010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define IMR_PTXIM 0x00000008UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define IMR_PRXIM 0x00000004UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define IMR_PPTXIM 0x00000002UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define IMR_PPRXIM 0x00000001UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* 0x0013FB0FUL = initial value of IMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define INT_MASK_DEF (IMR_PPTXIM|IMR_PPRXIM|IMR_PTXIM|IMR_PRXIM|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) IMR_PWEIM|IMR_TXWB0IM|IMR_TXWB1IM|IMR_FLONIM|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) IMR_OVFIM|IMR_LSTEIM|IMR_LSTPEIM|IMR_SRCIM|IMR_MIBFIM|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) IMR_SHDNIM|IMR_TMR1IM|IMR_TMR0IM|IMR_TXSTLM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * Bits in the TDCSR0/1, RDCSR0 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define TRDCSR_DEAD 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define TRDCSR_WAK 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define TRDCSR_ACT 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define TRDCSR_RUN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * Bits in the CAMADDR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define CAMADDR_CAMEN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define CAMADDR_VCAMSL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * Bits in the CAMCR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define CAMCR_PS1 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define CAMCR_PS0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define CAMCR_AITRPKT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define CAMCR_AITR16 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define CAMCR_CAMRD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define CAMCR_CAMWR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define CAMCR_PS_CAM_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define CAMCR_PS_CAM_DATA 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define CAMCR_PS_MAR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * Bits in the MIICFG register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define MIICFG_MPO1 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define MIICFG_MPO0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define MIICFG_MFDC 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * Bits in the MIISR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define MIISR_MIDLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * Bits in the PHYSR0 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define PHYSR0_PHYRST 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define PHYSR0_LINKGD 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define PHYSR0_FDPX 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define PHYSR0_SPDG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define PHYSR0_SPD10 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define PHYSR0_RXFLC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define PHYSR0_TXFLC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * Bits in the PHYSR1 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define PHYSR1_PHYTBI 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * Bits in the MIICR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define MIICR_MAUTO 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define MIICR_RCMD 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define MIICR_WCMD 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define MIICR_MDPM 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define MIICR_MOUT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define MIICR_MDO 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define MIICR_MDI 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define MIICR_MDC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * Bits in the MIIADR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define MIIADR_SWMPL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * Bits in the CFGA register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define CFGA_PMHCTG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define CFGA_GPIO1PD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define CFGA_ABSHDN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define CFGA_PACPI 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * Bits in the CFGB register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define CFGB_GTCKOPT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define CFGB_MIIOPT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define CFGB_CRSEOPT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define CFGB_OFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define CFGB_CRANDOM 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define CFGB_CAP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define CFGB_MBA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define CFGB_BAKOPT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * Bits in the CFGC register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define CFGC_EELOAD 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define CFGC_BROPT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define CFGC_DLYEN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define CFGC_DTSEL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define CFGC_BTSEL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define CFGC_BPS2 0x04 /* bootrom select[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define CFGC_BPS1 0x02 /* bootrom select[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define CFGC_BPS0 0x01 /* bootrom select[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * Bits in the CFGD register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define CFGD_IODIS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define CFGD_MSLVDACEN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define CFGD_CFGDACEN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define CFGD_PCI64EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define CFGD_HTMRL4 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * Bits in the DCFG1 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define DCFG_XMWI 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define DCFG_XMRM 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define DCFG_XMRL 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define DCFG_PERDIS 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define DCFG_MRWAIT 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define DCFG_MWWAIT 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define DCFG_LATMEN 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * Bits in the MCFG0 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define MCFG_RXARB 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define MCFG_RFT1 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define MCFG_RFT0 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define MCFG_LOWTHOPT 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define MCFG_PQEN 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define MCFG_RTGOPT 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define MCFG_VIDFR 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * Bits in the MCFG1 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define MCFG_TXARB 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define MCFG_TXQBK1 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define MCFG_TXQBK0 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define MCFG_TXQNOBK 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define MCFG_SNAPOPT 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * Bits in the PMCC register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define PMCC_DSI 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define PMCC_D2_DIS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define PMCC_D1_DIS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define PMCC_D3C_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define PMCC_D3H_EN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define PMCC_D2_EN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define PMCC_D1_EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define PMCC_D0_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * Bits in STICKHW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define STICKHW_SWPTAG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define STICKHW_WOLSR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define STICKHW_WOLEN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define STICKHW_DS1 0x02 /* R/W by software/cfg cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define STICKHW_DS0 0x01 /* suspend well DS write port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * Bits in the MIBCR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define MIBCR_MIBISTOK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define MIBCR_MIBISTGO 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define MIBCR_MIBINC 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define MIBCR_MIBHI 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define MIBCR_MIBFRZ 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define MIBCR_MIBFLSH 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define MIBCR_MPTRINI 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define MIBCR_MIBCLR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * Bits in the EERSV register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define EERSV_BOOT_RPL ((u8) 0x01) /* Boot method selection for VT6110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define EERSV_BOOT_MASK ((u8) 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define EERSV_BOOT_INT19 ((u8) 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define EERSV_BOOT_INT18 ((u8) 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define EERSV_BOOT_LOCAL ((u8) 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define EERSV_BOOT_BEV ((u8) 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * Bits in BPCMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define BPCMD_BPDNE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define BPCMD_EBPWR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define BPCMD_EBPRD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * Bits in the EECSR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define EECSR_EMBP 0x40 /* eeprom embedded programming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define EECSR_RELOAD 0x20 /* eeprom content reload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define EECSR_DPM 0x10 /* eeprom direct programming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define EECSR_ECS 0x08 /* eeprom CS pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define EECSR_ECK 0x04 /* eeprom CK pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define EECSR_EDI 0x02 /* eeprom DI pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define EECSR_EDO 0x01 /* eeprom DO pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * Bits in the EMBCMD register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define EMBCMD_EDONE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define EMBCMD_EWDIS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define EMBCMD_EWEN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define EMBCMD_EWR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define EMBCMD_ERD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * Bits in TESTCFG register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define TESTCFG_HBDIS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * Bits in CHIPGCR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define CHIPGCR_FCGMII 0x80 /* force GMII (else MII only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define CHIPGCR_FCFDX 0x40 /* force full duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define CHIPGCR_FCRESV 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define CHIPGCR_FCMODE 0x10 /* enable MAC forced mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define CHIPGCR_LPSOPT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define CHIPGCR_TM1US 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define CHIPGCR_TM0US 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define CHIPGCR_PHYINTEN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * Bits in WOLCR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define WOLCR_MSWOLEN7 0x0080 /* enable pattern match filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define WOLCR_MSWOLEN6 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define WOLCR_MSWOLEN5 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define WOLCR_MSWOLEN4 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define WOLCR_MSWOLEN3 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define WOLCR_MSWOLEN2 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define WOLCR_MSWOLEN1 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define WOLCR_MSWOLEN0 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define WOLCR_ARP_EN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * Bits in WOLCR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define WOLCR_LINKOFF_EN 0x0800 /* link off detected enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define WOLCR_LINKON_EN 0x0400 /* link on detected enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define WOLCR_MAGIC_EN 0x0200 /* magic packet filter enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define WOLCR_UNICAST_EN 0x0100 /* unicast filter enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * Bits in PWCFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define PWCFG_PHYPWOPT 0x80 /* internal MII I/F timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define PWCFG_PCISTICK 0x40 /* PCI sticky R/W enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define PWCFG_WOLTYPE 0x20 /* pulse(1) or button (0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define PWCFG_LEGCY_WOL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define PWCFG_PMCSR_PME_SR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define PWCFG_PMCSR_PME_EN 0x04 /* control by PCISTICK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define PWCFG_LEGACY_WOLSR 0x02 /* Legacy WOL_SR shadow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define PWCFG_LEGACY_WOLEN 0x01 /* Legacy WOL_EN shadow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * Bits in WOLCFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define WOLCFG_PMEOVR 0x80 /* for legacy use, force PMEEN always */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define WOLCFG_SAM 0x20 /* accept multicast case reset, default=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define WOLCFG_SAB 0x10 /* accept broadcast case reset, default=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define WOLCFG_SMIIACC 0x08 /* ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define WOLCFG_SGENWH 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define WOLCFG_PHYINTEN 0x01 /* 0:PHYINT trigger enable, 1:use internal MII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) to report status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * Bits in WOLSR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define WOLSR_LINKOFF_INT 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define WOLSR_LINKON_INT 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define WOLSR_MAGIC_INT 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define WOLSR_UNICAST_INT 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * Ethernet address filter type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define PKT_TYPE_NONE 0x0000 /* Turn off receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define PKT_TYPE_DIRECTED 0x0001 /* obselete, directed address is always accepted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define PKT_TYPE_MULTICAST 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define PKT_TYPE_ALL_MULTICAST 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define PKT_TYPE_BROADCAST 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define PKT_TYPE_PROMISCUOUS 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define PKT_TYPE_LONG 0x2000 /* NOTE.... the definition of LONG is >2048 bytes in our chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define PKT_TYPE_RUNT 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define PKT_TYPE_ERROR 0x8000 /* Accept error packets, e.g. CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * Loopback mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define MAC_LB_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define MAC_LB_INTERNAL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define MAC_LB_EXTERNAL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * Enabled mask value of irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #if defined(_SIM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define IMR_MASK_VALUE 0x0033FF0FUL /* initial value of IMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) set IMR0 to 0x0F according to spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define IMR_MASK_VALUE 0x0013FB0FUL /* initial value of IMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ignore MIBFI,RACEI to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) reduce intr. frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) NOTE.... do not enable NoBuf int mask at driver driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) when (1) NoBuf -> RxThreshold = SF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) (2) OK -> RxThreshold = original value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * Revision id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define REV_ID_VT3119_A0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define REV_ID_VT3119_A1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define REV_ID_VT3216_A0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * Max time out delay time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define W_MAX_TIMEOUT 0x0FFFU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * MAC registers as a structure. Cannot be directly accessed this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * way but generates offsets for readl/writel() calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct mac_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) volatile u8 PAR[6]; /* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) volatile u8 RCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) volatile u8 TCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) volatile __le32 CR0Set; /* 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) volatile __le32 CR0Clr; /* 0x0C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) volatile u8 MARCAM[8]; /* 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) volatile __le32 DecBaseHi; /* 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) volatile __le16 DbfBaseHi; /* 0x1C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) volatile __le16 reserved_1E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) volatile __le16 ISRCTL; /* 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) volatile u8 TXESR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) volatile u8 RXESR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) volatile __le32 ISR; /* 0x24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) volatile __le32 IMR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) volatile __le32 TDStatusPort; /* 0x2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) volatile __le16 TDCSRSet; /* 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) volatile u8 RDCSRSet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) volatile u8 reserved_33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) volatile __le16 TDCSRClr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) volatile u8 RDCSRClr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) volatile u8 reserved_37;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) volatile __le32 RDBaseLo; /* 0x38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) volatile __le16 RDIdx; /* 0x3C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) volatile u8 TQETMR; /* 0x3E, VT3216 and above only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) volatile u8 RQETMR; /* 0x3F, VT3216 and above only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) volatile __le32 TDBaseLo[4]; /* 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) volatile __le16 RDCSize; /* 0x50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) volatile __le16 TDCSize; /* 0x52 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) volatile __le16 TDIdx[4]; /* 0x54 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) volatile __le16 tx_pause_timer; /* 0x5C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) volatile __le16 RBRDU; /* 0x5E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) volatile __le32 FIFOTest0; /* 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) volatile __le32 FIFOTest1; /* 0x64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) volatile u8 CAMADDR; /* 0x68 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) volatile u8 CAMCR; /* 0x69 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) volatile u8 GFTEST; /* 0x6A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) volatile u8 FTSTCMD; /* 0x6B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) volatile u8 MIICFG; /* 0x6C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) volatile u8 MIISR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) volatile u8 PHYSR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) volatile u8 PHYSR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) volatile u8 MIICR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) volatile u8 MIIADR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) volatile __le16 MIIDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) volatile __le16 SoftTimer0; /* 0x74 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) volatile __le16 SoftTimer1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) volatile u8 CFGA; /* 0x78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) volatile u8 CFGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) volatile u8 CFGC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) volatile u8 CFGD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) volatile __le16 DCFG; /* 0x7C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) volatile __le16 MCFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) volatile u8 TBIST; /* 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) volatile u8 RBIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) volatile u8 PMCPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) volatile u8 STICKHW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) volatile u8 MIBCR; /* 0x84 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) volatile u8 reserved_85;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) volatile u8 rev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) volatile u8 PORSTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) volatile __le32 MIBData; /* 0x88 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) volatile __le16 EEWrData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) volatile u8 reserved_8E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) volatile u8 BPMDWr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) volatile u8 BPCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) volatile u8 BPMDRd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) volatile u8 EECHKSUM; /* 0x92 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) volatile u8 EECSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) volatile __le16 EERdData; /* 0x94 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) volatile u8 EADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) volatile u8 EMBCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) volatile u8 JMPSR0; /* 0x98 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) volatile u8 JMPSR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) volatile u8 JMPSR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) volatile u8 JMPSR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) volatile u8 CHIPGSR; /* 0x9C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) volatile u8 TESTCFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) volatile u8 DEBUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) volatile u8 CHIPGCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) volatile __le16 WOLCRSet; /* 0xA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) volatile u8 PWCFGSet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) volatile u8 WOLCFGSet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) volatile __le16 WOLCRClr; /* 0xA4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) volatile u8 PWCFGCLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) volatile u8 WOLCFGClr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) volatile __le16 WOLSRSet; /* 0xA8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) volatile __le16 reserved_AA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) volatile __le16 WOLSRClr; /* 0xAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) volatile __le16 reserved_AE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) volatile __le16 PatternCRC[8]; /* 0xB0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) volatile __le32 ByteMask[4][4]; /* 0xC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) enum hw_mib {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) HW_MIB_ifRxAllPkts = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) HW_MIB_ifRxOkPkts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) HW_MIB_ifTxOkPkts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) HW_MIB_ifRxErrorPkts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) HW_MIB_ifRxRuntOkPkt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) HW_MIB_ifRxRuntErrPkt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) HW_MIB_ifRx64Pkts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) HW_MIB_ifTx64Pkts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) HW_MIB_ifRx65To127Pkts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) HW_MIB_ifTx65To127Pkts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) HW_MIB_ifRx128To255Pkts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) HW_MIB_ifTx128To255Pkts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) HW_MIB_ifRx256To511Pkts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) HW_MIB_ifTx256To511Pkts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) HW_MIB_ifRx512To1023Pkts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) HW_MIB_ifTx512To1023Pkts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) HW_MIB_ifRx1024To1518Pkts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) HW_MIB_ifTx1024To1518Pkts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) HW_MIB_ifTxEtherCollisions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) HW_MIB_ifRxPktCRCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) HW_MIB_ifRxJumboPkts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) HW_MIB_ifTxJumboPkts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) HW_MIB_ifRxMacControlFrames,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) HW_MIB_ifTxMacControlFrames,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) HW_MIB_ifRxPktFAE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) HW_MIB_ifRxLongOkPkt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) HW_MIB_ifRxLongPktErrPkt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) HW_MIB_ifTXSQEErrors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) HW_MIB_ifRxNobuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) HW_MIB_ifRxSymbolErrors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) HW_MIB_ifInRangeLengthErrors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) HW_MIB_ifLateCollisions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) HW_MIB_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) enum chip_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) CHIP_TYPE_VT6110 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct velocity_info_tbl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) enum chip_type chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) int txqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define mac_hw_mibs_init(regs) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) BYTE_REG_BITS_ON(MIBCR_MIBFRZ,&((regs)->MIBCR));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) BYTE_REG_BITS_ON(MIBCR_MIBCLR,&((regs)->MIBCR));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) do {}\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) while (BYTE_REG_BITS_IS_ON(MIBCR_MIBCLR,&((regs)->MIBCR)));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) BYTE_REG_BITS_OFF(MIBCR_MIBFRZ,&((regs)->MIBCR));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define mac_read_isr(regs) readl(&((regs)->ISR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #define mac_write_isr(regs, x) writel((x),&((regs)->ISR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define mac_clear_isr(regs) writel(0xffffffffL,&((regs)->ISR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define mac_write_int_mask(mask, regs) writel((mask),&((regs)->IMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define mac_disable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Clr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define mac_enable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Set))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define mac_set_dma_length(regs, n) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) BYTE_REG_BITS_SET((n),0x07,&((regs)->DCFG));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define mac_set_rx_thresh(regs, n) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) BYTE_REG_BITS_SET((n),(MCFG_RFT0|MCFG_RFT1),&((regs)->MCFG));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define mac_rx_queue_run(regs) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) writeb(TRDCSR_RUN, &((regs)->RDCSRSet));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define mac_rx_queue_wake(regs) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) writeb(TRDCSR_WAK, &((regs)->RDCSRSet));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define mac_tx_queue_run(regs, n) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) writew(TRDCSR_RUN<<((n)*4),&((regs)->TDCSRSet));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define mac_tx_queue_wake(regs, n) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) writew(TRDCSR_WAK<<(n*4),&((regs)->TDCSRSet));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static inline void mac_eeprom_reload(struct mac_regs __iomem * regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) int i=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) BYTE_REG_BITS_ON(EECSR_RELOAD,&(regs->EECSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (i++>0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) } while (BYTE_REG_BITS_IS_ON(EECSR_RELOAD,&(regs->EECSR)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * Header for WOL definitions. Used to compute hashes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) typedef u8 MCAM_ADDR[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) struct arp_packet {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) u8 dest_mac[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) u8 src_mac[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) __be16 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) __be16 ar_hrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) __be16 ar_pro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) u8 ar_hln;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) u8 ar_pln;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) __be16 ar_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) u8 ar_sha[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) u8 ar_sip[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) u8 ar_tha[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) u8 ar_tip[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct _magic_packet {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) u8 dest_mac[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) u8 src_mac[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) __be16 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) u8 MAC[16][6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) u8 password[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * Store for chip context when saving and restoring status. Not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * all fields are saved/restored currently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) struct velocity_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) u8 mac_reg[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) MCAM_ADDR cam_addr[MCAM_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) u16 vcam[VCAM_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) u32 cammask[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) u32 patcrc[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) u32 pattern[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * Registers in the MII (offset unit is WORD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) // Marvell 88E1000/88E1000S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define MII_REG_PSCR 0x10 // PHY specific control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) // Bits in the Silicon revision register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define TCSR_ECHODIS 0x2000 //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define AUXCR_MDPPS 0x0004 //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) // Bits in the PLED register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define PLED_LALBE 0x0004 //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) // Marvell 88E1000/88E1000S Bits in the PHY specific control register (10h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define PSCR_ACRSTX 0x0800 // Assert CRS on Transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define PHYID_CICADA_CS8201 0x000FC410UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define PHYID_VT3216_32BIT 0x000FC610UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define PHYID_VT3216_64BIT 0x000FC600UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define PHYID_MARVELL_1000 0x01410C50UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define PHYID_MARVELL_1000S 0x01410C40UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define PHYID_ICPLUS_IP101A 0x02430C54UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define PHYID_REV_ID_MASK 0x0000000FUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #define PHYID_GET_PHY_ID(i) ((i) & ~PHYID_REV_ID_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define MII_REG_BITS_ON(x,i,p) do {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) u16 w;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) velocity_mii_read((p),(i),&(w));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) (w)|=(x);\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) velocity_mii_write((p),(i),(w));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define MII_REG_BITS_OFF(x,i,p) do {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) u16 w;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) velocity_mii_read((p),(i),&(w));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) (w)&=(~(x));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) velocity_mii_write((p),(i),(w));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define MII_REG_BITS_IS_ON(x,i,p) ({\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) u16 w;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) velocity_mii_read((p),(i),&(w));\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) ((int) ((w) & (x)));})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define MII_GET_PHY_ID(p) ({\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) u32 id;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) velocity_mii_read((p),MII_PHYSID2,(u16 *) &id);\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) velocity_mii_read((p),MII_PHYSID1,((u16 *) &id)+1);\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) (id);})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #define VELOCITY_WOL_MAGIC 0x00000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define VELOCITY_WOL_PHY 0x00000001UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define VELOCITY_WOL_ARP 0x00000002UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define VELOCITY_WOL_UCAST 0x00000004UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define VELOCITY_WOL_BCAST 0x00000010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define VELOCITY_WOL_MCAST 0x00000020UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define VELOCITY_WOL_MAGIC_SEC 0x00000040UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) * Flags for options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define VELOCITY_FLAGS_TAGGING 0x00000001UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define VELOCITY_FLAGS_RX_CSUM 0x00000004UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define VELOCITY_FLAGS_IP_ALIGN 0x00000008UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define VELOCITY_FLAGS_VAL_PKT_LEN 0x00000010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define VELOCITY_FLAGS_FLOW_CTRL 0x01000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * Flags for driver status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define VELOCITY_FLAGS_OPENED 0x00010000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define VELOCITY_FLAGS_VMNS_CONNECTED 0x00020000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define VELOCITY_FLAGS_VMNS_COMMITTED 0x00040000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define VELOCITY_FLAGS_WOL_ENABLED 0x00080000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * Flags for MII status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define VELOCITY_LINK_FAIL 0x00000001UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define VELOCITY_SPEED_10 0x00000002UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define VELOCITY_SPEED_100 0x00000004UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define VELOCITY_SPEED_1000 0x00000008UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define VELOCITY_DUPLEX_FULL 0x00000010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define VELOCITY_AUTONEG_ENABLE 0x00000020UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define VELOCITY_FORCED_BY_EEPROM 0x00000040UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * For velocity_set_media_duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define VELOCITY_LINK_CHANGE 0x00000001UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) enum speed_opt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) SPD_DPX_AUTO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) SPD_DPX_100_HALF = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) SPD_DPX_100_FULL = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) SPD_DPX_10_HALF = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) SPD_DPX_10_FULL = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) SPD_DPX_1000_FULL = 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) enum velocity_init_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) VELOCITY_INIT_COLD = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) VELOCITY_INIT_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) VELOCITY_INIT_WOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) enum velocity_flow_cntl_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) FLOW_CNTL_DEFAULT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) FLOW_CNTL_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) FLOW_CNTL_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) FLOW_CNTL_TX_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) FLOW_CNTL_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) struct velocity_opt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) int numrx; /* Number of RX descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) int numtx; /* Number of TX descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) enum speed_opt spd_dpx; /* Media link mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) int DMA_length; /* DMA length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) int rx_thresh; /* RX_THRESH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) int flow_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) int wol_opts; /* Wake on lan options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) int td_int_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) int int_works;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) int rx_bandwidth_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) int rx_bandwidth_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) int rx_bandwidth_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) int rxqueue_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) int txqueue_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) int tx_intsup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) int rx_intsup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #define AVAIL_TD(p,q) ((p)->options.numtx-((p)->tx.used[(q)]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #define GET_RD_BY_IDX(vptr, idx) (vptr->rd_ring[idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) struct velocity_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) int no_eeprom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) u8 ip_addr[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) enum chip_type chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) struct mac_regs __iomem * mac_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) unsigned long memaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) unsigned long ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) struct tx_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) int numq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /* FIXME: the locality of the data seems rather poor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) int used[TX_QUEUE_NO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) int curr[TX_QUEUE_NO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) int tail[TX_QUEUE_NO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) struct tx_desc *rings[TX_QUEUE_NO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) struct velocity_td_info *infos[TX_QUEUE_NO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) dma_addr_t pool_dma[TX_QUEUE_NO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) } tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) struct rx_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) int buf_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) int dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) int curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) u32 filled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) struct rx_desc *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) struct velocity_rd_info *info; /* It's an array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) dma_addr_t pool_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) } rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) u32 mib_counter[MAX_HW_MIB_COUNTER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) struct velocity_opt options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) u32 int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) u32 mii_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) u32 phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) int multicast_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) u8 vCAMmask[(VCAM_SIZE / 8)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) u8 mCAMmask[(MCAM_SIZE / 8)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) int wol_opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) u8 wol_passwd[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) struct velocity_context context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) u32 ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) u32 ethtool_ops_nesting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) u8 rev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) * velocity_get_ip - find an IP address for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) * @vptr: Velocity to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) * Dig out an IP address for this interface so that we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) * configure wakeup with WOL for ARP. If there are multiple IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) * addresses on this chain then we use the first - multi-IP WOL is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) * supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) static inline int velocity_get_ip(struct velocity_info *vptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) struct in_device *in_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) struct in_ifaddr *ifa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) int res = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) rcu_read_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) in_dev = __in_dev_get_rcu(vptr->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) if (in_dev != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) ifa = rcu_dereference(in_dev->ifa_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (ifa != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) memcpy(vptr->ip_addr, &ifa->ifa_address, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) rcu_read_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) * velocity_update_hw_mibs - fetch MIB counters from chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) * @vptr: velocity to update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) * The velocity hardware keeps certain counters in the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) * side. We need to read these when the user asks for statistics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) * or when they overflow (causing an interrupt). The read of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) * statistic clears it, so we keep running master counters in user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) * space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static inline void velocity_update_hw_mibs(struct velocity_info *vptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) BYTE_REG_BITS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) while (BYTE_REG_BITS_IS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) BYTE_REG_BITS_ON(MIBCR_MPTRINI, &(vptr->mac_regs->MIBCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) for (i = 0; i < HW_MIB_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) tmp = readl(&(vptr->mac_regs->MIBData)) & 0x00FFFFFFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) vptr->mib_counter[i] += tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) * init_flow_control_register - set up flow control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) * @vptr: velocity to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) * Configure the flow control registers for this velocity device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static inline void init_flow_control_register(struct velocity_info *vptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) struct mac_regs __iomem * regs = vptr->mac_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) /* Set {XHITH1, XHITH0, XLTH1, XLTH0} in FlowCR1 to {1, 0, 1, 1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) depend on RD=64, and Turn on XNOEN in FlowCR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) writel((CR0_XONEN | CR0_XHITH1 | CR0_XLTH1 | CR0_XLTH0), ®s->CR0Set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) writel((CR0_FDXTFCEN | CR0_FDXRFCEN | CR0_HDXFCEN | CR0_XHITH0), ®s->CR0Clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) /* Set TxPauseTimer to 0xFFFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) writew(0xFFFF, ®s->tx_pause_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) /* Initialize RBRDU to Rx buffer count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) writew(vptr->options.numrx, ®s->RBRDU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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