^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Written 1998-2001 by Donald Becker.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Current Maintainer: Kevin Brace <kevinbrace@bracecomputerlab.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) This software may be used and distributed according to the terms of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) the GNU General Public License (GPL), incorporated herein by reference.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Drivers based on or derived from this code fall under the GPL and must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) retain the authorship, copyright and license notice. This file is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) a complete program and may only be used when the entire operating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) system is licensed under the GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) This driver is designed for the VIA VT86C100A Rhine-I.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) and management NIC 6105M).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) The author may be reached as becker@scyld.com, or C/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Scyld Computing Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 410 Severn Ave., Suite 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Annapolis MD 21403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) This driver contains some changes from the original Donald Becker
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) version. He may or may not be interested in bug reports on this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) code. You can find his versions at:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) http://www.scyld.com/network/via-rhine.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) [link no longer provides useful info -jgarzik]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DRV_NAME "via-rhine"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* A few user-configurable values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) These may be modified when a driver module is loaded. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int debug = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RHINE_MSG_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) (0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) Setting to > 1518 effectively disables this feature. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) defined(CONFIG_SPARC) || defined(__ia64__) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) defined(__sh__) || defined(__mips__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int rx_copybreak = 1518;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int rx_copybreak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Work-around for broken BIOSes: they are unable to get the chip back out of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static bool avoid_D3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * In case you are looking for 'options[]' or 'full_duplex[]', they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * are gone. Use ethtool(8) instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) The Rhine has a 64 element 8390-like hash table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const int multicast_filter_limit = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Operational parameters that are set at compile time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Keep the ring sizes a power of two for compile efficiency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Making the Tx ring too large decreases the effectiveness of channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * bonding and packet priority.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * With BQL support, we can increase TX ring safely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * There are no ill effects from too-large receive rings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TX_RING_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TX_QUEUE_LEN (TX_RING_SIZE - 6) /* Limit ring entries actually used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RX_RING_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Operational parameters that usually are not changed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Time in jiffies before concluding the transmitter is hung. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TX_TIMEOUT (2*HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #include <linux/if_vlan.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #include <asm/processor.h> /* Processor type for cache alignment. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) module_param(debug, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) module_param(rx_copybreak, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) module_param(avoid_D3, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MODULE_PARM_DESC(debug, "VIA Rhine debug message flags");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MCAM_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define VCAM_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) Theory of Operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) I. Board Compatibility
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) II. Board-specific settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) Boards with this chip are functional only in a bus-master PCI slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) Many operational settings are loaded from the EEPROM to the Config word at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) offset 0x78. For most of these settings, this driver assumes that they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) correct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) If this driver is compiled to use PCI memory space operations the EEPROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) must be configured to enable memory ops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) III. Driver operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) IIIa. Ring buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) This driver uses two statically allocated fixed-size descriptor lists
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) formed into rings by a branch from the final descriptor to the beginning of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) IIIb/c. Transmit/Receive Structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) This driver attempts to use a zero-copy receive and transmit scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) Alas, all data buffers are required to start on a 32 bit boundary, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) the driver must often copy transmit packets into bounce buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) The driver allocates full frame size skbuffs for the Rx ring buffers at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) open() time and passes the skb->data field to the chip as receive data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) a fresh skbuff is allocated and the frame is copied to the new skbuff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) When the incoming frame is larger, the skbuff is passed directly up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) protocol stack. Buffers consumed this way are replaced by newly allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) skbuffs in the last phase of rhine_rx().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) The RX_COPYBREAK value is chosen to trade-off the memory wasted by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) using a full-sized skbuff for small frames vs. the copying costs of larger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) frames. New boards are typically used in generously configured machines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) and the underfilled buffers have negligible impact compared to the benefit of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) a single allocation size, so the default value of zero results in never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) copying packets. When copying is done, the cost is usually mitigated by using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) a combined copy/checksum routine. Copying also preloads the cache, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) most useful with small frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) Since the VIA chips are only able to transfer data to buffers on 32 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) boundaries, the IP header at offset 14 in an ethernet frame isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) longword aligned for further processing. Copying these unaligned buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) has the beneficial effect of 16-byte aligning the IP header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) IIId. Synchronization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) The driver runs as two independent, single-threaded flows of control. One
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) is the send-packet routine, which enforces single-threaded use by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) netdev_priv(dev)->lock spinlock. The other thread is the interrupt handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) which is single threaded by the hardware and interrupt handling software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) The send packet thread has partial control over the Tx ring. It locks the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) netdev_priv(dev)->lock whenever it's queuing a Tx packet. If the next slot in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) the ring is not available it stops the transmit queue by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) calling netif_stop_queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) The interrupt handler has exclusive control over the Rx ring and records stats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) from the Tx ring. After reaping the stats, it marks the Tx queue entry as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) empty by incrementing the dirty_tx mark. If at least half of the entries in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) the Rx ring are available the transmit queue is woken up if it was stopped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) IV. Notes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) IVb. References
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) Preliminary VT86C100A manual from http://www.via.com.tw/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) http://www.scyld.com/expert/100mbps.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) http://www.scyld.com/expert/NWay.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) IVc. Errata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) The VT86C100A manual is not reliable information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) The 3043 chip does not handle unaligned transmit or receive buffers, resulting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) in significant performance degradation for bounce buffer copies on transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) and unaligned IP headers on receive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) The chip does not pad to minimum transmit length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* This table drives the PCI probe routines. It's mostly boilerplate in all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) of the drivers, and will likely be provided by some future kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) Note the matching code -- the first table entry matchs all 56** cards but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) second only the 1234 card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) enum rhine_revs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) VT86C100A = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) VTunknown0 = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) VT6102 = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) VT8231 = 0x50, /* Integrated MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) VT8233 = 0x60, /* Integrated MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) VT8235 = 0x74, /* Integrated MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) VT8237 = 0x78, /* Integrated MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) VT8251 = 0x7C, /* Integrated MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) VT6105 = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) VT6105_B0 = 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) VT6105L = 0x8A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) VT6107 = 0x8C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) VTunknown2 = 0x8E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) VT6105M = 0x90, /* Management adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) enum rhine_quirks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) rqWOL = 0x0001, /* Wake-On-LAN support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) rqForceReset = 0x0002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) rqRhineI = 0x0100, /* See comment below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) rqIntPHY = 0x0200, /* Integrated PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) rqMgmt = 0x0400, /* Management adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) rqNeedEnMMIO = 0x0800, /* Whether the core needs to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * switched from PIO mode to MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * (only applies to PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * MMIO as well as for the collision counter and the Tx FIFO underflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Beware of PCI posted writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const struct pci_device_id rhine_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* OpenFirmware identifiers for platform-bus devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * The .data field is currently only used to store quirks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static u32 vt8500_quirks = rqWOL | rqForceReset | rq6patterns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct of_device_id rhine_of_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { .compatible = "via,vt8500-rhine", .data = &vt8500_quirks },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MODULE_DEVICE_TABLE(of, rhine_of_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Offsets to the device registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) enum register_offsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ChipCmd1=0x09, TQWake=0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) IntrStatus=0x0C, IntrEnable=0x0E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MulticastFilter0=0x10, MulticastFilter1=0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E, PCIBusConfig1=0x6F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) StickyHW=0x83, IntrStatus2=0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) CamMask=0x88, CamCon=0x92, CamAddr=0x93,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) WOLcrClr1=0xA6, WOLcgClr=0xA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Bits in ConfigD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) enum backoff_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) BackOptional=0x01, BackModify=0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) BackCaptureEffect=0x04, BackRandom=0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Bits in the TxConfig (TCR) register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) enum tcr_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) TCR_PQEN=0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) TCR_LB0=0x02, /* loopback[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) TCR_LB1=0x04, /* loopback[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) TCR_OFSET=0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) TCR_RTGOPT=0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) TCR_RTFT0=0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) TCR_RTFT1=0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) TCR_RTSF=0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Bits in the CamCon (CAMC) register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) enum camcon_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) CAMC_CAMEN=0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) CAMC_VCAMSL=0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) CAMC_CAMWR=0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) CAMC_CAMRD=0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Bits in the PCIBusConfig1 (BCR1) register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) enum bcr1_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) BCR1_POT0=0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) BCR1_POT1=0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) BCR1_POT2=0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) BCR1_CTFT0=0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) BCR1_CTFT1=0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) BCR1_CTSF=0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) BCR1_TXQNOBK=0x40, /* for VT6105 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) BCR1_VIDFR=0x80, /* for VT6105 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) BCR1_MED0=0x40, /* for VT6102 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) BCR1_MED1=0x80, /* for VT6102 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Registers we check that mmio and reg are the same. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const int mmio_verify_registers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Bits in the interrupt status/mask registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) enum intr_status_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) IntrRxDone = 0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) IntrTxDone = 0x0002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) IntrRxErr = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) IntrTxError = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) IntrRxEmpty = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) IntrPCIErr = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) IntrStatsMax = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) IntrRxEarly = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) IntrTxUnderrun = 0x0210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) IntrRxOverflow = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) IntrRxDropped = 0x0800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) IntrRxNoBuf = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) IntrTxAborted = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) IntrLinkChange = 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) IntrRxWakeUp = 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) IntrTxDescRace = 0x080000, /* mapped from IntrStatus2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) IntrNormalSummary = IntrRxDone | IntrTxDone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) IntrTxErrSummary = IntrTxDescRace | IntrTxAborted | IntrTxError |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) IntrTxUnderrun,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) enum wol_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) WOLucast = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) WOLmagic = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) WOLbmcast = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) WOLlnkon = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) WOLlnkoff = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* The Rx and Tx buffer descriptors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct rx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) __le32 rx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) __le32 desc_length; /* Chain flag, Buffer/frame length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) __le32 next_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct tx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) __le32 tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) __le32 desc_length; /* Chain flag, Tx Config, Frame length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) __le32 next_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define TXDESC 0x00e08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) enum rx_status_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Bits in *_desc.*_status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) enum desc_status_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) DescOwn=0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* Bits in *_desc.*_length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) enum desc_length_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) DescTag=0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Bits in ChipCmd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) enum chip_cmd_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct rhine_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u64 packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u64 bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct u64_stats_sync syncp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct rhine_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* Bit mask for configured VLAN ids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Descriptor rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct rx_desc *rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct tx_desc *tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dma_addr_t rx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dma_addr_t tx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* The addresses of receive-in-place skbuffs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct sk_buff *rx_skbuff[RX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* The saved address of a sent-in-place packet/buffer, for later free(). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct sk_buff *tx_skbuff[TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Tx bounce buffers (Rhine-I only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned char *tx_buf[TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned char *tx_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dma_addr_t tx_bufs_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) long pioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct mutex task_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) bool task_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct work_struct slow_event_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct work_struct reset_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u32 msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Frequently used values: keep some adjacent for cache effect. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u32 quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) unsigned int cur_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned int cur_tx, dirty_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) unsigned int rx_buf_sz; /* Based on MTU+slack. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct rhine_stats rx_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct rhine_stats tx_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u8 wolopts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u8 tx_thresh, rx_thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct mii_if_info mii_if;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define BYTE_REG_BITS_ON(x, p) do { iowrite8((ioread8((p))|(x)), (p)); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define WORD_REG_BITS_ON(x, p) do { iowrite16((ioread16((p))|(x)), (p)); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define DWORD_REG_BITS_ON(x, p) do { iowrite32((ioread32((p))|(x)), (p)); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define BYTE_REG_BITS_IS_ON(x, p) (ioread8((p)) & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define WORD_REG_BITS_IS_ON(x, p) (ioread16((p)) & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define DWORD_REG_BITS_IS_ON(x, p) (ioread32((p)) & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define BYTE_REG_BITS_OFF(x, p) do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define WORD_REG_BITS_OFF(x, p) do { iowrite16(ioread16((p)) & (~(x)), (p)); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define DWORD_REG_BITS_OFF(x, p) do { iowrite32(ioread32((p)) & (~(x)), (p)); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define BYTE_REG_BITS_SET(x, m, p) do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define WORD_REG_BITS_SET(x, m, p) do { iowrite16((ioread16((p)) & (~(m)))|(x), (p)); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define DWORD_REG_BITS_SET(x, m, p) do { iowrite32((ioread32((p)) & (~(m)))|(x), (p)); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int mdio_read(struct net_device *dev, int phy_id, int location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static int rhine_open(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static void rhine_reset_task(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static void rhine_slow_event_task(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static void rhine_tx_timeout(struct net_device *dev, unsigned int txqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static irqreturn_t rhine_interrupt(int irq, void *dev_instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static void rhine_tx(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static int rhine_rx(struct net_device *dev, int limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static void rhine_set_rx_mode(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static void rhine_get_stats64(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct rtnl_link_stats64 *stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static const struct ethtool_ops netdev_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static int rhine_close(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int rhine_vlan_rx_add_vid(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) __be16 proto, u16 vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static int rhine_vlan_rx_kill_vid(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) __be16 proto, u16 vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static void rhine_restart_tx(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static void rhine_wait_bit(struct rhine_private *rp, u8 reg, u8 mask, bool low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) for (i = 0; i < 1024; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) bool has_mask_bits = !!(ioread8(ioaddr + reg) & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (low ^ has_mask_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (i > 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) netif_dbg(rp, hw, rp->dev, "%s bit wait (%02x/%02x) cycle "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) "count: %04d\n", low ? "low" : "high", reg, mask, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static void rhine_wait_bit_high(struct rhine_private *rp, u8 reg, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) rhine_wait_bit(rp, reg, mask, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static void rhine_wait_bit_low(struct rhine_private *rp, u8 reg, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) rhine_wait_bit(rp, reg, mask, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static u32 rhine_get_events(struct rhine_private *rp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 intr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) intr_status = ioread16(ioaddr + IntrStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (rp->quirks & rqStatusWBRace)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return intr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static void rhine_ack_events(struct rhine_private *rp, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (rp->quirks & rqStatusWBRace)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) iowrite8(mask >> 16, ioaddr + IntrStatus2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) iowrite16(mask, ioaddr + IntrStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * Get power related registers into sane state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * Notify user about past WOL event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static void rhine_power_init(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u16 wolstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (rp->quirks & rqWOL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Make sure chip is in power state D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* Disable "force PME-enable" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) iowrite8(0x80, ioaddr + WOLcgClr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Clear power-event config bits (WOL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) iowrite8(0xFF, ioaddr + WOLcrClr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* More recent cards can manage two additional patterns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (rp->quirks & rq6patterns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) iowrite8(0x03, ioaddr + WOLcrClr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* Save power-event status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) wolstat = ioread8(ioaddr + PwrcsrSet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (rp->quirks & rq6patterns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* Clear power-event status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) iowrite8(0xFF, ioaddr + PwrcsrClr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (rp->quirks & rq6patterns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) iowrite8(0x03, ioaddr + PwrcsrClr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (wolstat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) char *reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) switch (wolstat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) case WOLmagic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) reason = "Magic packet";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) case WOLlnkon:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) reason = "Link went up";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) case WOLlnkoff:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) reason = "Link went down";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) case WOLucast:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) reason = "Unicast packet";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) case WOLbmcast:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) reason = "Multicast/broadcast packet";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) reason = "Unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) netdev_info(dev, "Woke system up. Reason: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) reason);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static void rhine_chip_reset(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u8 cmd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) IOSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) netdev_info(dev, "Reset not complete yet. Trying harder.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* Force reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (rp->quirks & rqForceReset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) iowrite8(0x40, ioaddr + MiscCmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* Reset can take somewhat longer (rare) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) rhine_wait_bit_low(rp, ChipCmd1, Cmd1Reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) cmd1 = ioread8(ioaddr + ChipCmd1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) netif_info(rp, hw, dev, "Reset %s\n", (cmd1 & Cmd1Reset) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) "failed" : "succeeded");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static void enable_mmio(long pioaddr, u32 quirks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (quirks & rqNeedEnMMIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (quirks & rqRhineI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* More recent docs say that this bit is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) n = inb(pioaddr + ConfigA) | 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) outb(n, pioaddr + ConfigA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) n = inb(pioaddr + ConfigD) | 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) outb(n, pioaddr + ConfigD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static inline int verify_mmio(struct device *hwdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) long pioaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) void __iomem *ioaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u32 quirks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (quirks & rqNeedEnMMIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* Check that selected MMIO registers match the PIO ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) while (mmio_verify_registers[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int reg = mmio_verify_registers[i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) unsigned char a = inb(pioaddr+reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) unsigned char b = readb(ioaddr+reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (a != b) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_err(hwdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) "MMIO do not match PIO [%02x] (%02x != %02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) reg, a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * (plus 0x6C for Rhine-I/II)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static void rhine_reload_eeprom(long pioaddr, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) outb(0x20, pioaddr + MACRegEEcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) for (i = 0; i < 1024; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (!(inb(pioaddr + MACRegEEcsr) & 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (i > 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) pr_info("%4d cycles used @ %s:%d\n", i, __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * MMIO. If reloading EEPROM was done first this could be avoided, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * it is not known if that still works with the "win98-reboot" problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) enable_mmio(pioaddr, rp->quirks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* Turn off EEPROM-controlled wake-up (magic packet) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (rp->quirks & rqWOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static void rhine_poll(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) const int irq = rp->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) disable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) rhine_interrupt(irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) enable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static void rhine_kick_tx_threshold(struct rhine_private *rp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (rp->tx_thresh < 0xe0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) rp->tx_thresh += 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) BYTE_REG_BITS_SET(rp->tx_thresh, 0x80, ioaddr + TxConfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static void rhine_tx_err(struct rhine_private *rp, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct net_device *dev = rp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (status & IntrTxAborted) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) netif_info(rp, tx_err, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) "Abort %08x, frame dropped\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (status & IntrTxUnderrun) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) rhine_kick_tx_threshold(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) netif_info(rp, tx_err ,dev, "Transmitter underrun, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) "Tx threshold now %02x\n", rp->tx_thresh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (status & IntrTxDescRace)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) netif_info(rp, tx_err, dev, "Tx descriptor write-back race\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if ((status & IntrTxError) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) (status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) rhine_kick_tx_threshold(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) netif_info(rp, tx_err, dev, "Unspecified error. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) "Tx threshold now %02x\n", rp->tx_thresh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) rhine_restart_tx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static void rhine_update_rx_crc_and_missed_errord(struct rhine_private *rp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct net_device_stats *stats = &rp->dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) stats->rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) stats->rx_missed_errors += ioread16(ioaddr + RxMissed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * Clears the "tally counters" for CRC errors and missed frames(?).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * It has been reported that some chips need a write of 0 to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * these, for others the counters are set to 1 when written to and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * instead cleared when read. So we clear them both ways ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) iowrite32(0, ioaddr + RxMissed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ioread16(ioaddr + RxCRCErrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ioread16(ioaddr + RxMissed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define RHINE_EVENT_NAPI_RX (IntrRxDone | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) IntrRxErr | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) IntrRxEmpty | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) IntrRxOverflow | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) IntrRxDropped | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) IntrRxNoBuf | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) IntrRxWakeUp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define RHINE_EVENT_NAPI_TX_ERR (IntrTxError | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) IntrTxAborted | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) IntrTxUnderrun | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) IntrTxDescRace)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define RHINE_EVENT_NAPI_TX (IntrTxDone | RHINE_EVENT_NAPI_TX_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define RHINE_EVENT_NAPI (RHINE_EVENT_NAPI_RX | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) RHINE_EVENT_NAPI_TX | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) IntrStatsMax)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define RHINE_EVENT_SLOW (IntrPCIErr | IntrLinkChange)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define RHINE_EVENT (RHINE_EVENT_NAPI | RHINE_EVENT_SLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static int rhine_napipoll(struct napi_struct *napi, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct rhine_private *rp = container_of(napi, struct rhine_private, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct net_device *dev = rp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u16 enable_mask = RHINE_EVENT & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) int work_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) status = rhine_get_events(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) rhine_ack_events(rp, status & ~RHINE_EVENT_SLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (status & RHINE_EVENT_NAPI_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) work_done += rhine_rx(dev, budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (status & RHINE_EVENT_NAPI_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (status & RHINE_EVENT_NAPI_TX_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* Avoid scavenging before Tx engine turned off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) rhine_wait_bit_low(rp, ChipCmd, CmdTxOn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (ioread8(ioaddr + ChipCmd) & CmdTxOn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) netif_warn(rp, tx_err, dev, "Tx still on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) rhine_tx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (status & RHINE_EVENT_NAPI_TX_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) rhine_tx_err(rp, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (status & IntrStatsMax) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) spin_lock(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) rhine_update_rx_crc_and_missed_errord(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) spin_unlock(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (status & RHINE_EVENT_SLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) enable_mask &= ~RHINE_EVENT_SLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) schedule_work(&rp->slow_event_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (work_done < budget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) napi_complete_done(napi, work_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) iowrite16(enable_mask, ioaddr + IntrEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return work_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static void rhine_hw_init(struct net_device *dev, long pioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* Reset the chip to erase previous misconfiguration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) rhine_chip_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* Rhine-I needs extra time to recuperate before EEPROM reload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (rp->quirks & rqRhineI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* Reload EEPROM controlled bytes cleared by soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (dev_is_pci(dev->dev.parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) rhine_reload_eeprom(pioaddr, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static const struct net_device_ops rhine_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .ndo_open = rhine_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .ndo_stop = rhine_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .ndo_start_xmit = rhine_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .ndo_get_stats64 = rhine_get_stats64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .ndo_set_rx_mode = rhine_set_rx_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .ndo_do_ioctl = netdev_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .ndo_tx_timeout = rhine_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .ndo_vlan_rx_add_vid = rhine_vlan_rx_add_vid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .ndo_vlan_rx_kill_vid = rhine_vlan_rx_kill_vid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .ndo_poll_controller = rhine_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static int rhine_init_one_common(struct device *hwdev, u32 quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) long pioaddr, void __iomem *ioaddr, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct rhine_private *rp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) int i, rc, phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* this should always be supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) rc = dma_set_mask(hwdev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dev_err(hwdev, "32-bit DMA addresses not supported by the card!?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) dev = alloc_etherdev(sizeof(struct rhine_private));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) SET_NETDEV_DEV(dev, hwdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) rp->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) rp->quirks = quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) rp->pioaddr = pioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) rp->base = ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) rp->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) rp->msg_enable = netif_msg_init(debug, RHINE_MSG_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) phy_id = rp->quirks & rqIntPHY ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) u64_stats_init(&rp->tx_stats.syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) u64_stats_init(&rp->rx_stats.syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* Get chip registers into a sane state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) rhine_power_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) rhine_hw_init(dev, pioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (!is_valid_ether_addr(dev->dev_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* Report it and use a random ethernet address instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) netdev_err(dev, "Invalid MAC address: %pM\n", dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) eth_hw_addr_random(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) netdev_info(dev, "Using random MAC address: %pM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* For Rhine-I/II, phy_id is loaded from EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (!phy_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) phy_id = ioread8(ioaddr + 0x6C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) spin_lock_init(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) mutex_init(&rp->task_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) INIT_WORK(&rp->reset_task, rhine_reset_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) INIT_WORK(&rp->slow_event_task, rhine_slow_event_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) rp->mii_if.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) rp->mii_if.mdio_read = mdio_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) rp->mii_if.mdio_write = mdio_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) rp->mii_if.phy_id_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) rp->mii_if.reg_num_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* The chip-specific entries in the device structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) dev->netdev_ops = &rhine_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dev->ethtool_ops = &netdev_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) dev->watchdog_timeo = TX_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) netif_napi_add(dev, &rp->napi, rhine_napipoll, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (rp->quirks & rqRhineI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (rp->quirks & rqMgmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dev->features |= NETIF_F_HW_VLAN_CTAG_TX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) NETIF_F_HW_VLAN_CTAG_RX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) NETIF_F_HW_VLAN_CTAG_FILTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* dev->name not defined before register_netdev()! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) rc = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) goto err_out_free_netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (rp->quirks & rqRhineI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) name = "Rhine";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) else if (rp->quirks & rqStatusWBRace)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) name = "Rhine II";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) else if (rp->quirks & rqMgmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) name = "Rhine III (Management Adapter)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) name = "Rhine III";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) netdev_info(dev, "VIA %s at %p, %pM, IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) name, ioaddr, dev->dev_addr, rp->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) dev_set_drvdata(hwdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) u16 mii_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) int mii_status = mdio_read(dev, phy_id, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (mii_status != 0xffff && mii_status != 0x0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) netdev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) "MII PHY found at address %d, status 0x%04x advertising %04x Link %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) phy_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) mii_status, rp->mii_if.advertising,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) mdio_read(dev, phy_id, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* set IFF_RUNNING */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (mii_status & BMSR_LSTATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) netif_carrier_on(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) netif_carrier_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) rp->mii_if.phy_id = phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (avoid_D3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) netif_info(rp, probe, dev, "No D3 power state at shutdown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) err_out_free_netdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static int rhine_init_one_pci(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct device *hwdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) long pioaddr, memaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) int io_size = pdev->revision < VTunknown0 ? 128 : 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /* This driver was written to use PCI memory space. Some early versions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * of the Rhine may only work correctly with I/O space accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * TODO: determine for which revisions this is true and assign the flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * in code as opposed to this Kconfig option (???)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #ifdef CONFIG_VIA_RHINE_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) u32 quirks = rqNeedEnMMIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) u32 quirks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) rc = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (pdev->revision < VTunknown0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) quirks |= rqRhineI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) } else if (pdev->revision >= VT6102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) quirks |= rqWOL | rqForceReset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (pdev->revision < VT6105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) quirks |= rqStatusWBRace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) quirks |= rqIntPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (pdev->revision >= VT6105_B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) quirks |= rq6patterns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (pdev->revision >= VT6105M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) quirks |= rqMgmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if ((pci_resource_len(pdev, 0) < io_size) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) (pci_resource_len(pdev, 1) < io_size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) dev_err(hwdev, "Insufficient PCI resources, aborting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) goto err_out_pci_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) pioaddr = pci_resource_start(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) memaddr = pci_resource_start(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) rc = pci_request_regions(pdev, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) goto err_out_pci_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ioaddr = pci_iomap(pdev, (quirks & rqNeedEnMMIO ? 1 : 0), io_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (!ioaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) dev_err(hwdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) "ioremap failed for device %s, region 0x%X @ 0x%lX\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) dev_name(hwdev), io_size, memaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) goto err_out_free_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) enable_mmio(pioaddr, quirks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) rc = verify_mmio(hwdev, pioaddr, ioaddr, quirks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) goto err_out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) rc = rhine_init_one_common(&pdev->dev, quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) pioaddr, ioaddr, pdev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) err_out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) pci_iounmap(pdev, ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) err_out_free_res:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) err_out_pci_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static int rhine_init_one_platform(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) const u32 *quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) match = of_match_device(rhine_of_tbl, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ioaddr = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (IS_ERR(ioaddr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return PTR_ERR(ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) quirks = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (!quirks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return rhine_init_one_common(&pdev->dev, *quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) (long)ioaddr, ioaddr, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static int alloc_ring(struct net_device* dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct device *hwdev = dev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) void *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) dma_addr_t ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) ring = dma_alloc_coherent(hwdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) RX_RING_SIZE * sizeof(struct rx_desc) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) TX_RING_SIZE * sizeof(struct tx_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) &ring_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (!ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) netdev_err(dev, "Could not allocate DMA memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (rp->quirks & rqRhineI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) rp->tx_bufs = dma_alloc_coherent(hwdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) PKT_BUF_SZ * TX_RING_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) &rp->tx_bufs_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (rp->tx_bufs == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) dma_free_coherent(hwdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) RX_RING_SIZE * sizeof(struct rx_desc) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) TX_RING_SIZE * sizeof(struct tx_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) ring, ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) rp->rx_ring = ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) rp->rx_ring_dma = ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static void free_ring(struct net_device* dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct device *hwdev = dev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) dma_free_coherent(hwdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) RX_RING_SIZE * sizeof(struct rx_desc) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) TX_RING_SIZE * sizeof(struct tx_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) rp->rx_ring, rp->rx_ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) rp->tx_ring = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (rp->tx_bufs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) dma_free_coherent(hwdev, PKT_BUF_SZ * TX_RING_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) rp->tx_bufs, rp->tx_bufs_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) rp->tx_bufs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct rhine_skb_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) static inline int rhine_skb_dma_init(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) struct rhine_skb_dma *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) struct device *hwdev = dev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) const int size = rp->rx_buf_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) sd->skb = netdev_alloc_skb(dev, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (!sd->skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) sd->dma = dma_map_single(hwdev, sd->skb->data, size, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (unlikely(dma_mapping_error(hwdev, sd->dma))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) netif_err(rp, drv, dev, "Rx DMA mapping failure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) dev_kfree_skb_any(sd->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) static void rhine_reset_rbufs(struct rhine_private *rp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) rp->cur_rx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) for (i = 0; i < RX_RING_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) static inline void rhine_skb_dma_nic_store(struct rhine_private *rp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct rhine_skb_dma *sd, int entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) rp->rx_skbuff_dma[entry] = sd->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) rp->rx_skbuff[entry] = sd->skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) rp->rx_ring[entry].addr = cpu_to_le32(sd->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) dma_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static void free_rbufs(struct net_device* dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) static int alloc_rbufs(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) dma_addr_t next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) int rc, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) next = rp->rx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) /* Init the ring entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) rp->rx_ring[i].rx_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) next += sizeof(struct rx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) rp->rx_ring[i].next_desc = cpu_to_le32(next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) rp->rx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /* Mark the last entry as wrapping the ring. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /* Fill in the Rx buffers. Handle allocation failure gracefully. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) struct rhine_skb_dma sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) rc = rhine_skb_dma_init(dev, &sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) free_rbufs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) rhine_skb_dma_nic_store(rp, &sd, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) rhine_reset_rbufs(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static void free_rbufs(struct net_device* dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct device *hwdev = dev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /* Free all the skbuffs in the Rx queue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) rp->rx_ring[i].rx_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (rp->rx_skbuff[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) dma_unmap_single(hwdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) rp->rx_skbuff_dma[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) rp->rx_buf_sz, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) dev_kfree_skb(rp->rx_skbuff[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) rp->rx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) static void alloc_tbufs(struct net_device* dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) dma_addr_t next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) rp->dirty_tx = rp->cur_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) next = rp->tx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) for (i = 0; i < TX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) rp->tx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) rp->tx_ring[i].tx_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) next += sizeof(struct tx_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) rp->tx_ring[i].next_desc = cpu_to_le32(next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (rp->quirks & rqRhineI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) netdev_reset_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) static void free_tbufs(struct net_device* dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) struct device *hwdev = dev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) for (i = 0; i < TX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) rp->tx_ring[i].tx_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (rp->tx_skbuff[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (rp->tx_skbuff_dma[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) dma_unmap_single(hwdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) rp->tx_skbuff_dma[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) rp->tx_skbuff[i]->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) dev_kfree_skb(rp->tx_skbuff[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) rp->tx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) rp->tx_buf[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static void rhine_check_media(struct net_device *dev, unsigned int init_media)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (!rp->mii_if.force_media)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) mii_check_media(&rp->mii_if, netif_msg_link(rp), init_media);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (rp->mii_if.full_duplex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) ioaddr + ChipCmd1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) ioaddr + ChipCmd1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) netif_info(rp, link, dev, "force_media %d, carrier %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) rp->mii_if.force_media, netif_carrier_ok(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* Called after status of force_media possibly changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) static void rhine_set_carrier(struct mii_if_info *mii)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) struct net_device *dev = mii->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (mii->force_media) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) /* autoneg is off: Link is always assumed to be up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (!netif_carrier_ok(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) netif_carrier_on(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) rhine_check_media(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) netif_info(rp, link, dev, "force_media %d, carrier %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) mii->force_media, netif_carrier_ok(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) * rhine_set_cam - set CAM multicast filters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) * @ioaddr: register block of this Rhine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * @idx: multicast CAM index [0..MCAM_SIZE-1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * @addr: multicast address (6 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * Load addresses into multicast filters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) iowrite8(CAMC_CAMEN, ioaddr + CamCon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) /* Paranoid -- idx out of range should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) idx &= (MCAM_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) iowrite8((u8) idx, ioaddr + CamAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) for (i = 0; i < 6; i++, addr++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) iowrite8(*addr, ioaddr + MulticastFilter0 + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) iowrite8(0, ioaddr + CamCon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) * rhine_set_vlan_cam - set CAM VLAN filters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) * @ioaddr: register block of this Rhine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) * @idx: VLAN CAM index [0..VCAM_SIZE-1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) * @addr: VLAN ID (2 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) * Load addresses into VLAN filters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) /* Paranoid -- idx out of range should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) idx &= (VCAM_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) iowrite8((u8) idx, ioaddr + CamAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) iowrite16(*((u16 *) addr), ioaddr + MulticastFilter0 + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) iowrite8(0, ioaddr + CamCon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) * rhine_set_cam_mask - set multicast CAM mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) * @ioaddr: register block of this Rhine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) * @mask: multicast CAM mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) * Mask sets multicast filters active/inactive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) iowrite8(CAMC_CAMEN, ioaddr + CamCon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) /* write mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) iowrite32(mask, ioaddr + CamMask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) /* disable CAMEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) iowrite8(0, ioaddr + CamCon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) * rhine_set_vlan_cam_mask - set VLAN CAM mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) * @ioaddr: register block of this Rhine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) * @mask: VLAN CAM mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * Mask sets VLAN filters active/inactive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) /* write mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) iowrite32(mask, ioaddr + CamMask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /* disable CAMEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) iowrite8(0, ioaddr + CamCon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) * rhine_init_cam_filter - initialize CAM filters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) * @dev: network device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) * Initialize (disable) hardware VLAN and multicast support on this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) * Rhine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) static void rhine_init_cam_filter(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /* Disable all CAMs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) rhine_set_vlan_cam_mask(ioaddr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) rhine_set_cam_mask(ioaddr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) /* disable hardware VLAN support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) BYTE_REG_BITS_ON(TCR_PQEN, ioaddr + TxConfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) * rhine_update_vcam - update VLAN CAM filters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) * @dev: rhine_private data of this Rhine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) * Update VLAN CAM filters to match configuration change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static void rhine_update_vcam(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) u16 vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) u32 vCAMmask = 0; /* 32 vCAMs (6105M and better) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) unsigned int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) for_each_set_bit(vid, rp->active_vlans, VLAN_N_VID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) rhine_set_vlan_cam(ioaddr, i, (u8 *)&vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) vCAMmask |= 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (++i >= VCAM_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) rhine_set_vlan_cam_mask(ioaddr, vCAMmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) static int rhine_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) spin_lock_bh(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) set_bit(vid, rp->active_vlans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) rhine_update_vcam(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) spin_unlock_bh(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) static int rhine_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) spin_lock_bh(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) clear_bit(vid, rp->active_vlans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) rhine_update_vcam(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) spin_unlock_bh(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) static void init_registers(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) /* Initialize other registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) /* Configure initial FIFO thresholds. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) iowrite8(0x20, ioaddr + TxConfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) rp->tx_thresh = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) rhine_set_rx_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (rp->quirks & rqMgmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) rhine_init_cam_filter(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) napi_enable(&rp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) iowrite16(RHINE_EVENT & 0xffff, ioaddr + IntrEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) ioaddr + ChipCmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) rhine_check_media(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) /* Enable MII link status auto-polling (required for IntrLinkChange) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) static void rhine_enable_linkmon(struct rhine_private *rp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) iowrite8(0, ioaddr + MIICmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) iowrite8(0x80, ioaddr + MIICmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) rhine_wait_bit_high(rp, MIIRegAddr, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) /* Disable MII link status auto-polling (required for MDIO access) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) static void rhine_disable_linkmon(struct rhine_private *rp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) iowrite8(0, ioaddr + MIICmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (rp->quirks & rqRhineI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) /* Can be called from ISR. Evil. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) /* 0x80 must be set immediately before turning it off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) iowrite8(0x80, ioaddr + MIICmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) rhine_wait_bit_high(rp, MIIRegAddr, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) /* Heh. Now clear 0x80 again. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) iowrite8(0, ioaddr + MIICmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) rhine_wait_bit_high(rp, MIIRegAddr, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) /* Read and write over the MII Management Data I/O (MDIO) interface. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) static int mdio_read(struct net_device *dev, int phy_id, int regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) rhine_disable_linkmon(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) /* rhine_disable_linkmon already cleared MIICmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) iowrite8(phy_id, ioaddr + MIIPhyAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) iowrite8(regnum, ioaddr + MIIRegAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) rhine_wait_bit_low(rp, MIICmd, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) result = ioread16(ioaddr + MIIData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) rhine_enable_linkmon(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) rhine_disable_linkmon(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) /* rhine_disable_linkmon already cleared MIICmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) iowrite8(phy_id, ioaddr + MIIPhyAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) iowrite8(regnum, ioaddr + MIIRegAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) iowrite16(value, ioaddr + MIIData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) rhine_wait_bit_low(rp, MIICmd, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) rhine_enable_linkmon(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) static void rhine_task_disable(struct rhine_private *rp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) mutex_lock(&rp->task_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) rp->task_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) mutex_unlock(&rp->task_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) cancel_work_sync(&rp->slow_event_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) cancel_work_sync(&rp->reset_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) static void rhine_task_enable(struct rhine_private *rp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) mutex_lock(&rp->task_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) rp->task_enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) mutex_unlock(&rp->task_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) static int rhine_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) rc = request_irq(rp->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) netif_dbg(rp, ifup, dev, "%s() irq %d\n", __func__, rp->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) rc = alloc_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) goto out_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) rc = alloc_rbufs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) goto out_free_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) alloc_tbufs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) enable_mmio(rp->pioaddr, rp->quirks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) rhine_power_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) rhine_chip_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) rhine_task_enable(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) init_registers(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) netif_dbg(rp, ifup, dev, "%s() Done - status %04x MII status: %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) __func__, ioread16(ioaddr + ChipCmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) out_free_ring:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) free_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) out_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) free_irq(rp->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) static void rhine_reset_task(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) struct rhine_private *rp = container_of(work, struct rhine_private,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) reset_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) struct net_device *dev = rp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) mutex_lock(&rp->task_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) if (!rp->task_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) napi_disable(&rp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) netif_tx_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) spin_lock_bh(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) /* clear all descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) free_tbufs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) alloc_tbufs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) rhine_reset_rbufs(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) /* Reinitialize the hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) rhine_chip_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) init_registers(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) spin_unlock_bh(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) netif_trans_update(dev); /* prevent tx timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) mutex_unlock(&rp->task_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) static void rhine_tx_timeout(struct net_device *dev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) netdev_warn(dev, "Transmit timed out, status %04x, PHY status %04x, resetting...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) ioread16(ioaddr + IntrStatus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) schedule_work(&rp->reset_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) static inline bool rhine_tx_queue_full(struct rhine_private *rp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) return (rp->cur_tx - rp->dirty_tx) >= TX_QUEUE_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) struct device *hwdev = dev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) unsigned entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) /* Caution: the write order is important here, set the field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) with the "ownership" bits last. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) /* Calculate the next Tx descriptor entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) entry = rp->cur_tx % TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) if (skb_padto(skb, ETH_ZLEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) rp->tx_skbuff[entry] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) if ((rp->quirks & rqRhineI) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) /* Must use alignment buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (skb->len > PKT_BUF_SZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) /* packet too long, drop it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) rp->tx_skbuff[entry] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) dev->stats.tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) /* Padding is not copied and so must be redone. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) if (skb->len < ETH_ZLEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) memset(rp->tx_buf[entry] + skb->len, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) ETH_ZLEN - skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) rp->tx_skbuff_dma[entry] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) (rp->tx_buf[entry] -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) rp->tx_bufs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) rp->tx_skbuff_dma[entry] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) dma_map_single(hwdev, skb->data, skb->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (dma_mapping_error(hwdev, rp->tx_skbuff_dma[entry])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) rp->tx_skbuff_dma[entry] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) dev->stats.tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) rp->tx_ring[entry].desc_length =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (unlikely(skb_vlan_tag_present(skb))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) u16 vid_pcp = skb_vlan_tag_get(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) /* drop CFI/DEI bit, register needs VID and PCP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) vid_pcp = (vid_pcp & VLAN_VID_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) ((vid_pcp & VLAN_PRIO_MASK) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) rp->tx_ring[entry].tx_status = cpu_to_le32((vid_pcp) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) /* request tagging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) rp->tx_ring[entry].desc_length |= cpu_to_le32(0x020000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) rp->tx_ring[entry].tx_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) netdev_sent_queue(dev, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /* lock eth irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) dma_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) rp->tx_ring[entry].tx_status |= cpu_to_le32(DescOwn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) rp->cur_tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) * Nobody wants cur_tx write to rot for ages after the NIC will have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) * seen the transmit request, especially as the transmit completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) * handler could miss it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) /* Non-x86 Todo: explicitly flush cache lines here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (skb_vlan_tag_present(skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) /* Tx queues are bits 7-0 (first Tx queue: bit 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) /* Wake the potentially-idle transmit channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) ioaddr + ChipCmd1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) IOSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) /* dirty_tx may be pessimistically out-of-sync. See rhine_tx. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) if (rhine_tx_queue_full(rp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) smp_rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) /* Rejuvenate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (!rhine_tx_queue_full(rp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) netif_dbg(rp, tx_queued, dev, "Transmit frame #%d queued in slot %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) rp->cur_tx - 1, entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) static void rhine_irq_disable(struct rhine_private *rp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) iowrite16(0x0000, rp->base + IntrEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) /* The interrupt handler does all of the Rx thread work and cleans up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) after the Tx thread. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) static irqreturn_t rhine_interrupt(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) struct net_device *dev = dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) status = rhine_get_events(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) netif_dbg(rp, intr, dev, "Interrupt, status %08x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) if (status & RHINE_EVENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) rhine_irq_disable(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) napi_schedule(&rp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) if (status & ~(IntrLinkChange | IntrStatsMax | RHINE_EVENT_NAPI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) netif_err(rp, intr, dev, "Something Wicked happened! %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) /* This routine is logically part of the interrupt handler, but isolated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) for clarity. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) static void rhine_tx(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) struct device *hwdev = dev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) unsigned int pkts_compl = 0, bytes_compl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) unsigned int dirty_tx = rp->dirty_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) unsigned int cur_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) * The race with rhine_start_tx does not matter here as long as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) * driver enforces a value of cur_tx that was relevant when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) * packet was scheduled to the network chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) * Executive summary: smp_rmb() balances smp_wmb() in rhine_start_tx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) smp_rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) cur_tx = rp->cur_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) /* find and cleanup dirty tx descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) while (dirty_tx != cur_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) unsigned int entry = dirty_tx % TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) u32 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) netif_dbg(rp, tx_done, dev, "Tx scavenge %d status %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) entry, txstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) if (txstatus & DescOwn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) skb = rp->tx_skbuff[entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) if (txstatus & 0x8000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) netif_dbg(rp, tx_done, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) "Transmit error, Tx status %08x\n", txstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) if (txstatus & 0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) dev->stats.tx_carrier_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) if (txstatus & 0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) dev->stats.tx_window_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) if (txstatus & 0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) dev->stats.tx_aborted_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) if (txstatus & 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) dev->stats.tx_heartbeat_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) (txstatus & 0x0800) || (txstatus & 0x1000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) dev->stats.tx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) break; /* Keep the skb - we try again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) /* Transmitter restarted in 'abnormal' handler. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) if (rp->quirks & rqRhineI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) dev->stats.collisions += (txstatus >> 3) & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) dev->stats.collisions += txstatus & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) netif_dbg(rp, tx_done, dev, "collisions: %1.1x:%1.1x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) (txstatus >> 3) & 0xF, txstatus & 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) u64_stats_update_begin(&rp->tx_stats.syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) rp->tx_stats.bytes += skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) rp->tx_stats.packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) u64_stats_update_end(&rp->tx_stats.syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) /* Free the original skb. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) if (rp->tx_skbuff_dma[entry]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) dma_unmap_single(hwdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) rp->tx_skbuff_dma[entry],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) skb->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) bytes_compl += skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) pkts_compl++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) dev_consume_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) rp->tx_skbuff[entry] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) dirty_tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) rp->dirty_tx = dirty_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) /* Pity we can't rely on the nearby BQL completion implicit barrier. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) netdev_completed_queue(dev, pkts_compl, bytes_compl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) /* cur_tx may be optimistically out-of-sync. See rhine_start_tx. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) if (!rhine_tx_queue_full(rp) && netif_queue_stopped(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) smp_rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) /* Rejuvenate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) if (rhine_tx_queue_full(rp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) * rhine_get_vlan_tci - extract TCI from Rx data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) * @skb: pointer to sk_buff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) * @data_size: used data area of the buffer including CRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) * If hardware VLAN tag extraction is enabled and the chip indicates a 802.1Q
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) * packet, the extracted 802.1Q header (2 bytes TPID + 2 bytes TCI) is 4-byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) * aligned following the CRC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) static inline u16 rhine_get_vlan_tci(struct sk_buff *skb, int data_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) u8 *trailer = (u8 *)skb->data + ((data_size + 3) & ~3) + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) return be16_to_cpup((__be16 *)trailer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) static inline void rhine_rx_vlan_tag(struct sk_buff *skb, struct rx_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) int data_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) dma_rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) if (unlikely(desc->desc_length & cpu_to_le32(DescTag))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) u16 vlan_tci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) vlan_tci = rhine_get_vlan_tci(skb, data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) /* Process up to limit frames from receive ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) static int rhine_rx(struct net_device *dev, int limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) struct device *hwdev = dev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) int entry = rp->cur_rx % RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) netif_dbg(rp, rx_status, dev, "%s(), entry %d status %08x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) entry, le32_to_cpu(rp->rx_ring[entry].rx_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) /* If EOP is set on the next entry, it's a new packet. Send it up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) for (count = 0; count < limit; ++count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) struct rx_desc *desc = rp->rx_ring + entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) u32 desc_status = le32_to_cpu(desc->rx_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) int data_size = desc_status >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) if (desc_status & DescOwn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) netif_dbg(rp, rx_status, dev, "%s() status %08x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) desc_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) if ((desc_status & RxWholePkt) != RxWholePkt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) netdev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) "Oversized Ethernet frame spanned multiple buffers, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) "entry %#x length %d status %08x!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) entry, data_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) desc_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) } else if (desc_status & RxErr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) /* There was a error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) netif_dbg(rp, rx_err, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) "%s() Rx error %08x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) desc_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) if (desc_status & 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) if (desc_status & 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) dev->stats.rx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) if (desc_status & 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) if (desc_status & 0x0002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) /* this can also be updated outside the interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) spin_lock(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) spin_unlock(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) /* Length should omit the CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) int pkt_len = data_size - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) /* Check if the packet is long enough to accept without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) copying to a minimally-sized skbuff. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) if (pkt_len < rx_copybreak) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) skb = netdev_alloc_skb_ip_align(dev, pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) if (unlikely(!skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) goto drop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) dma_sync_single_for_cpu(hwdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) rp->rx_skbuff_dma[entry],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) rp->rx_buf_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) skb_copy_to_linear_data(skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) rp->rx_skbuff[entry]->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) dma_sync_single_for_device(hwdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) rp->rx_skbuff_dma[entry],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) rp->rx_buf_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) struct rhine_skb_dma sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) if (unlikely(rhine_skb_dma_init(dev, &sd) < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) goto drop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) skb = rp->rx_skbuff[entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) dma_unmap_single(hwdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) rp->rx_skbuff_dma[entry],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) rp->rx_buf_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) rhine_skb_dma_nic_store(rp, &sd, entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) skb_put(skb, pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) rhine_rx_vlan_tag(skb, desc, data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) netif_receive_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) u64_stats_update_begin(&rp->rx_stats.syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) rp->rx_stats.bytes += pkt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) rp->rx_stats.packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) u64_stats_update_end(&rp->rx_stats.syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) give_descriptor_to_nic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) desc->rx_status = cpu_to_le32(DescOwn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) entry = (++rp->cur_rx) % RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) drop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) goto give_descriptor_to_nic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) static void rhine_restart_tx(struct net_device *dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) int entry = rp->dirty_tx % TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) u32 intr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) * If new errors occurred, we need to sort them out before doing Tx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) * In that case the ISR will be back here RSN anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) intr_status = rhine_get_events(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) if ((intr_status & IntrTxErrSummary) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) /* We know better than the chip where it should continue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) ioaddr + TxRingPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) ioaddr + ChipCmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) if (rp->tx_ring[entry].desc_length & cpu_to_le32(0x020000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) /* Tx queues are bits 7-0 (first Tx queue: bit 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) ioaddr + ChipCmd1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) IOSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) /* This should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) netif_warn(rp, tx_err, dev, "another error occurred %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) static void rhine_slow_event_task(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) struct rhine_private *rp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) container_of(work, struct rhine_private, slow_event_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) struct net_device *dev = rp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) u32 intr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) mutex_lock(&rp->task_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) if (!rp->task_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) intr_status = rhine_get_events(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) rhine_ack_events(rp, intr_status & RHINE_EVENT_SLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) if (intr_status & IntrLinkChange)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) rhine_check_media(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) if (intr_status & IntrPCIErr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) netif_warn(rp, hw, dev, "PCI error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) iowrite16(RHINE_EVENT & 0xffff, rp->base + IntrEnable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) mutex_unlock(&rp->task_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) rhine_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) unsigned int start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) spin_lock_bh(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) rhine_update_rx_crc_and_missed_errord(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) spin_unlock_bh(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) netdev_stats_to_stats64(stats, &dev->stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) start = u64_stats_fetch_begin_irq(&rp->rx_stats.syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) stats->rx_packets = rp->rx_stats.packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) stats->rx_bytes = rp->rx_stats.bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) } while (u64_stats_fetch_retry_irq(&rp->rx_stats.syncp, start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) start = u64_stats_fetch_begin_irq(&rp->tx_stats.syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) stats->tx_packets = rp->tx_stats.packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) stats->tx_bytes = rp->tx_stats.bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) } while (u64_stats_fetch_retry_irq(&rp->tx_stats.syncp, start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) static void rhine_set_rx_mode(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) u32 mc_filter[2]; /* Multicast hash filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) u8 rx_mode = 0x0C; /* Note: 0x02=accept runt, 0x01=accept errs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) rx_mode = 0x1C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) iowrite32(0xffffffff, ioaddr + MulticastFilter0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) iowrite32(0xffffffff, ioaddr + MulticastFilter1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) (dev->flags & IFF_ALLMULTI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) /* Too many to match, or accept all multicasts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) iowrite32(0xffffffff, ioaddr + MulticastFilter0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) iowrite32(0xffffffff, ioaddr + MulticastFilter1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) } else if (rp->quirks & rqMgmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) u32 mCAMmask = 0; /* 32 mCAMs (6105M and better) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) netdev_for_each_mc_addr(ha, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) if (i == MCAM_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) rhine_set_cam(ioaddr, i, ha->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) mCAMmask |= 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) rhine_set_cam_mask(ioaddr, mCAMmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) memset(mc_filter, 0, sizeof(mc_filter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) netdev_for_each_mc_addr(ha, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) /* enable/disable VLAN receive filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) if (rp->quirks & rqMgmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) if (dev->flags & IFF_PROMISC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) BYTE_REG_BITS_ON(BCR1_VIDFR, ioaddr + PCIBusConfig1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) BYTE_REG_BITS_ON(rx_mode, ioaddr + RxConfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) struct device *hwdev = dev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) strlcpy(info->bus_info, dev_name(hwdev), sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) static int netdev_get_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) mutex_lock(&rp->task_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) mii_ethtool_get_link_ksettings(&rp->mii_if, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) mutex_unlock(&rp->task_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) static int netdev_set_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) const struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) mutex_lock(&rp->task_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) rc = mii_ethtool_set_link_ksettings(&rp->mii_if, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) rhine_set_carrier(&rp->mii_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) mutex_unlock(&rp->task_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) static int netdev_nway_reset(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) return mii_nway_restart(&rp->mii_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) static u32 netdev_get_link(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) return mii_link_ok(&rp->mii_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) static u32 netdev_get_msglevel(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) return rp->msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) static void netdev_set_msglevel(struct net_device *dev, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) rp->msg_enable = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) if (!(rp->quirks & rqWOL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) spin_lock_irq(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) wol->supported = WAKE_PHY | WAKE_MAGIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) wol->wolopts = rp->wolopts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) spin_unlock_irq(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) u32 support = WAKE_PHY | WAKE_MAGIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) if (!(rp->quirks & rqWOL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) if (wol->wolopts & ~support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) spin_lock_irq(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) rp->wolopts = wol->wolopts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) spin_unlock_irq(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) static const struct ethtool_ops netdev_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .get_drvinfo = netdev_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .nway_reset = netdev_nway_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .get_link = netdev_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .get_msglevel = netdev_get_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .set_msglevel = netdev_set_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .get_wol = rhine_get_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .set_wol = rhine_set_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .get_link_ksettings = netdev_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .set_link_ksettings = netdev_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) mutex_lock(&rp->task_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) rhine_set_carrier(&rp->mii_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) mutex_unlock(&rp->task_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) static int rhine_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) rhine_task_disable(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) napi_disable(&rp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) netif_dbg(rp, ifdown, dev, "Shutting down ethercard, status was %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) ioread16(ioaddr + ChipCmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) /* Switch to loopback mode to avoid hardware races. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) rhine_irq_disable(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) /* Stop the chip's Tx and Rx processes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) iowrite16(CmdStop, ioaddr + ChipCmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) free_irq(rp->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) free_rbufs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) free_tbufs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) free_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) static void rhine_remove_one_pci(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) struct net_device *dev = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) pci_iounmap(pdev, rp->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) static int rhine_remove_one_platform(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) struct net_device *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) iounmap(rp->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) static void rhine_shutdown_pci(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) struct net_device *dev = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) void __iomem *ioaddr = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) if (!(rp->quirks & rqWOL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) return; /* Nothing to do for non-WOL adapters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) rhine_power_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) /* Make sure we use pattern 0, 1 and not 4, 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) if (rp->quirks & rq6patterns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) iowrite8(0x04, ioaddr + WOLcgClr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) spin_lock(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) if (rp->wolopts & WAKE_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) iowrite8(WOLmagic, ioaddr + WOLcrSet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) * Turn EEPROM-controlled wake-up back on -- some hardware may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) * not cooperate otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) iowrite8(WOLbmcast, ioaddr + WOLcgSet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) if (rp->wolopts & WAKE_PHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) if (rp->wolopts & WAKE_UCAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) iowrite8(WOLucast, ioaddr + WOLcrSet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) if (rp->wolopts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) /* Enable legacy WOL (for old motherboards) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) iowrite8(0x01, ioaddr + PwcfgSet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) spin_unlock(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) if (system_state == SYSTEM_POWER_OFF && !avoid_D3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) pci_wake_from_d3(pdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) pci_set_power_state(pdev, PCI_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) static int rhine_suspend(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) struct net_device *dev = dev_get_drvdata(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) rhine_task_disable(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) rhine_irq_disable(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) napi_disable(&rp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) netif_device_detach(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) if (dev_is_pci(device))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) rhine_shutdown_pci(to_pci_dev(device));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) static int rhine_resume(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) struct net_device *dev = dev_get_drvdata(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) struct rhine_private *rp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) enable_mmio(rp->pioaddr, rp->quirks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) rhine_power_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) free_tbufs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) alloc_tbufs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) rhine_reset_rbufs(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) rhine_task_enable(rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) spin_lock_bh(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) init_registers(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) spin_unlock_bh(&rp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) netif_device_attach(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) static SIMPLE_DEV_PM_OPS(rhine_pm_ops, rhine_suspend, rhine_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) #define RHINE_PM_OPS (&rhine_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) #define RHINE_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) #endif /* !CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) static struct pci_driver rhine_driver_pci = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) .id_table = rhine_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) .probe = rhine_init_one_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) .remove = rhine_remove_one_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) .shutdown = rhine_shutdown_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) .driver.pm = RHINE_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) static struct platform_driver rhine_driver_platform = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) .probe = rhine_init_one_platform,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) .remove = rhine_remove_one_platform,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) .of_match_table = rhine_of_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .pm = RHINE_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) static const struct dmi_system_id rhine_dmi_table[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) .ident = "EPIA-M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) .ident = "KV7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) { NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) static int __init rhine_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) int ret_pci, ret_platform;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) /* when a module, this is printed whether or not devices are found in probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) if (dmi_check_system(rhine_dmi_table)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) /* these BIOSes fail at PXE boot if chip is in D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) avoid_D3 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) pr_warn("Broken BIOS detected, avoid_D3 enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) else if (avoid_D3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) pr_info("avoid_D3 set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) ret_pci = pci_register_driver(&rhine_driver_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) ret_platform = platform_driver_register(&rhine_driver_platform);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) if ((ret_pci < 0) && (ret_platform < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) return ret_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) static void __exit rhine_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) platform_driver_unregister(&rhine_driver_platform);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) pci_unregister_driver(&rhine_driver_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) module_init(rhine_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) module_exit(rhine_cleanup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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