^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Tehuti Networks(R) Network Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * ethtool interface implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * RX HW/SW interaction overview
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * There are 2 types of RX communication channels between driver and NIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * info about buffer's location, size and ID. An ID field is used to identify a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * buffer when it's returned with data via RXD Fifo (see below)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * filled by HW and is readen by SW. Each descriptor holds status and ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * via dma moves it into host memory, builds new RXD descriptor with same ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * pushes it into RXD Fifo and raises interrupt to indicate new RX data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Current NIC configuration (registers + firmware) makes NIC use 2 RXF Fifos.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * One holds 1.5K packets and another - 26K packets. Depending on incoming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * filled with data, HW builds new RXD descriptor for it and push it into single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * RXD Fifo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * RX SW Data Structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * ~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * skb db - used to keep track of all skbs owned by SW and their dma addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * For RX case, ownership lasts from allocating new empty skb for RXF until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * accepting full skb from RXD and passing it to OS. Each RXF Fifo has its own
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * skb db. Implemented as array with bitmask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * fifo - keeps info about fifo's size and location, relevant HW registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Implemented as simple struct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * RX SW Execution Flow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * ~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Upon initialization (ifconfig up) driver creates RX fifos and initializes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * relevant registers. At the end of init phase, driver enables interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * NIC sees that there is no RXF buffers and raises
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * RD_INTR interrupt, isr fills skbs and Rx begins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Driver has two receive operation modes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * NAPI - interrupt-driven mixed with polling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * interrupt-driven only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Interrupt-driven only flow is following. When buffer is ready, HW raises
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * interrupt and isr is called. isr collects all available packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * (bdx_rx_receive), refills skbs (bdx_rx_alloc_skbs) and exit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Rx buffer allocation note
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * ~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Driver cares to feed such amount of RxF descriptors that respective amount of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * RxD descriptors can not fill entire RxD fifo. The main reason is lack of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * overflow check in Bordeaux for RxD fifo free/used size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * FIXME: this is NOT fully implemented, more work should be done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include "tehuti.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const struct pci_device_id bdx_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { PCI_VDEVICE(TEHUTI, 0x3009), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { PCI_VDEVICE(TEHUTI, 0x3010), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { PCI_VDEVICE(TEHUTI, 0x3014), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MODULE_DEVICE_TABLE(pci, bdx_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Definitions needed by ISR or NAPI functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static void bdx_tx_cleanup(struct bdx_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Definitions needed by FW loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Definitions needed by hw_start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int bdx_tx_init(struct bdx_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int bdx_rx_init(struct bdx_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Definitions needed by bdx_close */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void bdx_rx_free(struct bdx_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void bdx_tx_free(struct bdx_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Definitions needed by bdx_probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void bdx_set_ethtool_ops(struct net_device *netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Print Info *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static void print_hw_id(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct pci_nic *nic = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u16 pci_link_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u16 pci_ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pci_read_config_word(pdev, PCI_LINK_STATUS_REG, &pci_link_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) pci_read_config_word(pdev, PCI_DEV_CTRL_REG, &pci_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) pr_info("%s%s\n", BDX_NIC_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) nic->port_num == 1 ? "" : ", 2-Port");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pr_info("srom 0x%x fpga %d build %u lane# %d max_pl 0x%x mrrs 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) readl(nic->regs + FPGA_SEED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) GET_LINK_STATUS_LANES(pci_link_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void print_fw_id(struct pci_nic *nic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pr_info("fw 0x%x\n", readl(nic->regs + FW_VER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void print_eth_id(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) netdev_info(ndev, "%s, Port %c\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) BDX_NIC_NAME, (ndev->if_port == 0) ? 'A' : 'B');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Code *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define bdx_enable_interrupts(priv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define bdx_disable_interrupts(priv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) do { WRITE_REG(priv, regIMR, 0); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * bdx_fifo_init - create TX/RX descriptor fifo for host-NIC communication.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @priv: NIC private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @f: fifo to initialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @fsz_type: fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @reg_CFG0: offsets of registers relative to base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @reg_CFG1: offsets of registers relative to base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @reg_RPTR: offsets of registers relative to base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @reg_WPTR: offsets of registers relative to base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * 1K extra space is allocated at the end of the fifo to simplify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * processing of descriptors that wraps around fifo's end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Returns 0 on success, negative value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u16 memsz = FIFO_SIZE * (1 << fsz_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) memset(f, 0, sizeof(struct fifo));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* dma_alloc_coherent gives us 4k-aligned memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) f->va = dma_alloc_coherent(&priv->pdev->dev, memsz + FIFO_EXTRA_SPACE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) &f->da, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (!f->va) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pr_err("dma_alloc_coherent failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) RET(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) f->reg_CFG0 = reg_CFG0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) f->reg_CFG1 = reg_CFG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) f->reg_RPTR = reg_RPTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) f->reg_WPTR = reg_WPTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) f->rptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) f->wptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) f->memsz = memsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) f->size_mask = memsz - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) WRITE_REG(priv, reg_CFG1, H32_64(f->da));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) RET(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * bdx_fifo_free - free all resources used by fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @priv: NIC private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @f: fifo to release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (f->va) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dma_free_coherent(&priv->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) f->memsz + FIFO_EXTRA_SPACE, f->va, f->da);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) f->va = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) RET();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * bdx_link_changed - notifies OS about hw link state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * @priv: hw adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void bdx_link_changed(struct bdx_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!link) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (netif_carrier_ok(priv->ndev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) netif_stop_queue(priv->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) netif_carrier_off(priv->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) netdev_err(priv->ndev, "Link Down\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (!netif_carrier_ok(priv->ndev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) netif_wake_queue(priv->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) netif_carrier_on(priv->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) netdev_err(priv->ndev, "Link Up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static void bdx_isr_extra(struct bdx_priv *priv, u32 isr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (isr & IR_RX_FREE_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) DBG("RX_FREE_0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (isr & IR_LNKCHG0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) bdx_link_changed(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (isr & IR_PCIE_LINK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) netdev_err(priv->ndev, "PCI-E Link Fault\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (isr & IR_PCIE_TOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) netdev_err(priv->ndev, "PCI-E Time Out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * bdx_isr_napi - Interrupt Service Routine for Bordeaux NIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * @irq: interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * @dev: network device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * Return IRQ_NONE if it was not our interrupt, IRQ_HANDLED - otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * It reads ISR register to know interrupt reasons, and proceed them one by one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * Reasons of interest are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * RX_DESC - new packet has arrived and RXD fifo holds its descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * RX_FREE - number of free Rx buffers in RXF fifo gets low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * TX_FREE - packet was transmited and RXF fifo holds its descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static irqreturn_t bdx_isr_napi(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct net_device *ndev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct bdx_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) isr = (READ_REG(priv, regISR) & IR_RUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (unlikely(!isr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) bdx_enable_interrupts(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return IRQ_NONE; /* Not our interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (isr & IR_EXTRA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) bdx_isr_extra(priv, isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (isr & (IR_RX_DESC_0 | IR_TX_FREE_0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (likely(napi_schedule_prep(&priv->napi))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) __napi_schedule(&priv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) RET(IRQ_HANDLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* NOTE: we get here if intr has slipped into window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * between these lines in bdx_poll:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * bdx_enable_interrupts(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * currently intrs are disabled (since we read ISR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * and we have failed to register next poll.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * so we read the regs to trigger chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * and allow further interupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) READ_REG(priv, regTXF_WPTR_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) READ_REG(priv, regRXD_WPTR_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) bdx_enable_interrupts(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) RET(IRQ_HANDLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int bdx_poll(struct napi_struct *napi, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct bdx_priv *priv = container_of(napi, struct bdx_priv, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int work_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) bdx_tx_cleanup(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) work_done = bdx_rx_receive(priv, &priv->rxd_fifo0, budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if ((work_done < budget) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) (priv->napi_stop++ >= 30)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) DBG("rx poll is done. backing to isr-driven\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* from time to time we exit to let NAPI layer release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * device lock and allow waiting tasks (eg rmmod) to advance) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) priv->napi_stop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) napi_complete_done(napi, work_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) bdx_enable_interrupts(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return work_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * bdx_fw_load - loads firmware to NIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * @priv: NIC private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * Firmware is loaded via TXD fifo, so it must be initialized first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Firware must be loaded once per NIC not per PCI device provided by NIC (NIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * can have few of them). So all drivers use semaphore register to choose one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * that will actually load FW to NIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int bdx_fw_load(struct bdx_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) const struct firmware *fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int master, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) master = READ_REG(priv, regINIT_SEMAPHORE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (!READ_REG(priv, regINIT_STATUS) && master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) rc = request_firmware(&fw, "tehuti/bdx.bin", &priv->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) bdx_tx_push_desc_safe(priv, (char *)fw->data, fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) for (i = 0; i < 200; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (READ_REG(priv, regINIT_STATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) mdelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) WRITE_REG(priv, regINIT_SEMAPHORE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) netdev_err(priv->ndev, "firmware loading failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (rc == -EIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) READ_REG(priv, regVPC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) READ_REG(priv, regVIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) READ_REG(priv, regINIT_STATUS), i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) RET(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) DBG("%s: firmware loading success\n", priv->ndev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) RET(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static void bdx_restore_mac(struct net_device *ndev, struct bdx_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) DBG("mac0=%x mac1=%x mac2=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) READ_REG(priv, regUNC_MAC0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) WRITE_REG(priv, regUNC_MAC2_A, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) WRITE_REG(priv, regUNC_MAC1_A, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) WRITE_REG(priv, regUNC_MAC0_A, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) DBG("mac0=%x mac1=%x mac2=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) READ_REG(priv, regUNC_MAC0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) RET();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * bdx_hw_start - inits registers and starts HW's Rx and Tx engines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * @priv: NIC private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int bdx_hw_start(struct bdx_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct net_device *ndev = priv->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) bdx_link_changed(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* 10G overall max length (vlan, eth&ip header, ip payload, crc) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) WRITE_REG(priv, regFRM_LENGTH, 0X3FE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) WRITE_REG(priv, regPAUSE_QUANT, 0x96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) WRITE_REG(priv, regRX_FULLNESS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) WRITE_REG(priv, regTX_FULLNESS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) WRITE_REG(priv, regCTRLST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) regCTRLST_BASE | regCTRLST_RX_ENA | regCTRLST_TX_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) WRITE_REG(priv, regVGLB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) WRITE_REG(priv, regMAX_FRAME_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) priv->rxf_fifo0.m.pktsz & MAX_FRAME_AB_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) DBG("RDINTCM=%08x\n", priv->rdintcm); /*NOTE: test script uses this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) WRITE_REG(priv, regRDINTCM0, priv->rdintcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) WRITE_REG(priv, regRDINTCM2, 0); /*cpu_to_le32(rcm.val)); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) DBG("TDINTCM=%08x\n", priv->tdintcm); /*NOTE: test script uses this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) WRITE_REG(priv, regTDINTCM0, priv->tdintcm); /* old val = 0x300064 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Enable timer interrupt once in 2 secs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /*WRITE_REG(priv, regGTMR0, ((GTMR_SEC * 2) & GTMR_DATA)); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) bdx_restore_mac(priv->ndev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define BDX_IRQ_TYPE ((priv->nic->irq_type == IRQ_MSI) ? 0 : IRQF_SHARED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) rc = request_irq(priv->pdev->irq, bdx_isr_napi, BDX_IRQ_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ndev->name, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) bdx_enable_interrupts(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) RET(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) err_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) RET(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static void bdx_hw_stop(struct bdx_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) bdx_disable_interrupts(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) free_irq(priv->pdev->irq, priv->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) netif_carrier_off(priv->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) netif_stop_queue(priv->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) RET();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int bdx_hw_reset_direct(void __iomem *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u32 val, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* reset sequences: read, write 1, read, write 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) val = readl(regs + regCLKPLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) val = readl(regs + regCLKPLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* check that the PLLs are locked and reset ended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) for (i = 0; i < 70; i++, mdelay(10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if ((readl(regs + regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* do any PCI-E read transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) readl(regs + regRXD_CFG0_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pr_err("HW reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 1; /* failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int bdx_hw_reset(struct bdx_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u32 val, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (priv->port == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* reset sequences: read, write 1, read, write 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) val = READ_REG(priv, regCLKPLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) val = READ_REG(priv, regCLKPLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* check that the PLLs are locked and reset ended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) for (i = 0; i < 70; i++, mdelay(10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* do any PCI-E read transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) READ_REG(priv, regRXD_CFG0_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) pr_err("HW reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return 1; /* failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static int bdx_sw_reset(struct bdx_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* 1. load MAC (obsolete) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* 2. disable Rx (and Tx) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) WRITE_REG(priv, regGMAC_RXF_A, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* 3. disable port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) WRITE_REG(priv, regDIS_PORT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* 4. disable queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) WRITE_REG(priv, regDIS_QU, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* 5. wait until hw is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) for (i = 0; i < 50; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (READ_REG(priv, regRST_PORT) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (i == 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) netdev_err(priv->ndev, "SW reset timeout. continuing anyway\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* 6. disable intrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) WRITE_REG(priv, regRDINTCM0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) WRITE_REG(priv, regTDINTCM0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) WRITE_REG(priv, regIMR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) READ_REG(priv, regISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* 7. reset queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) WRITE_REG(priv, regRST_QU, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* 8. reset port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) WRITE_REG(priv, regRST_PORT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* 9. zero all read and write pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) WRITE_REG(priv, i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* 10. unseet port disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) WRITE_REG(priv, regDIS_PORT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* 11. unset queue disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) WRITE_REG(priv, regDIS_QU, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* 12. unset queue reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) WRITE_REG(priv, regRST_QU, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* 13. unset port reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) WRITE_REG(priv, regRST_PORT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* 14. enable Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* skiped. will be done later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* 15. save MAC (obsolete) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) RET(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* bdx_reset - performs right type of reset depending on hw type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int bdx_reset(struct bdx_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) RET((priv->pdev->device == 0x3009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ? bdx_hw_reset(priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) : bdx_sw_reset(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * bdx_close - Disables a network interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * @ndev: network interface device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * Returns 0, this is not allowed to fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * The close entry point is called when an interface is de-activated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * by the OS. The hardware is still under the drivers control, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * needs to be disabled. A global MAC reset is issued to stop the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * hardware, and all transmit and receive resources are freed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static int bdx_close(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct bdx_priv *priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) napi_disable(&priv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) bdx_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) bdx_hw_stop(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) bdx_rx_free(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) bdx_tx_free(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) RET(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * bdx_open - Called when a network interface is made active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * @ndev: network interface device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * Returns 0 on success, negative value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * The open entry point is called when a network interface is made
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * active by the system (IFF_UP). At this point all resources needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * for transmit and receive operations are allocated, the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * handler is registered with the OS, the watchdog timer is started,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * and the stack is notified that the interface is ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static int bdx_open(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct bdx_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) bdx_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (netif_running(ndev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) netif_stop_queue(priv->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if ((rc = bdx_tx_init(priv)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) (rc = bdx_rx_init(priv)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) (rc = bdx_fw_load(priv)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) rc = bdx_hw_start(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) napi_enable(&priv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) print_fw_id(priv->nic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) RET(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) bdx_close(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) RET(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static int bdx_range_check(struct bdx_priv *priv, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return (offset > (u32) (BDX_REGS_SIZE / priv->nic->port_num)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) -EINVAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int bdx_ioctl_priv(struct net_device *ndev, struct ifreq *ifr, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct bdx_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u32 data[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) DBG("jiffies=%ld cmd=%d\n", jiffies, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (cmd != SIOCDEVPRIVATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) error = copy_from_user(data, ifr->ifr_data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) pr_err("can't copy from user\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) RET(-EFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) DBG("%d 0x%x 0x%x\n", data[0], data[1], data[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (!capable(CAP_SYS_RAWIO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) switch (data[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) case BDX_OP_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) error = bdx_range_check(priv, data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) data[2] = READ_REG(priv, data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) DBG("read_reg(0x%x)=0x%x (dec %d)\n", data[1], data[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) data[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) error = copy_to_user(ifr->ifr_data, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) RET(-EFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) case BDX_OP_WRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) error = bdx_range_check(priv, data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) WRITE_REG(priv, data[1], data[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) RET(-EOPNOTSUPP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static int bdx_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (cmd >= SIOCDEVPRIVATE && cmd <= (SIOCDEVPRIVATE + 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) RET(bdx_ioctl_priv(ndev, ifr, cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) RET(-EOPNOTSUPP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * __bdx_vlan_rx_vid - private helper for adding/killing VLAN vid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * @ndev: network device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * @vid: VLAN vid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * @enable: enable or disable vlan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * Passes VLAN filter table to hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static void __bdx_vlan_rx_vid(struct net_device *ndev, uint16_t vid, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct bdx_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u32 reg, bit, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) DBG2("vid=%d value=%d\n", (int)vid, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (unlikely(vid >= 4096)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) pr_err("invalid VID: %u (> 4096)\n", vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) RET();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) reg = regVLAN_0 + (vid / 32) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) bit = 1 << vid % 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) val = READ_REG(priv, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) val |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) val &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) DBG2("new val %x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) WRITE_REG(priv, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) RET();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * bdx_vlan_rx_add_vid - kernel hook for adding VLAN vid to hw filtering table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * @ndev: network device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * @proto: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * @vid: VLAN vid to add
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static int bdx_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) __bdx_vlan_rx_vid(ndev, vid, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * bdx_vlan_rx_kill_vid - kernel hook for killing VLAN vid in hw filtering table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * @ndev: network device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * @proto: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * @vid: VLAN vid to kill
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static int bdx_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) __bdx_vlan_rx_vid(ndev, vid, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * bdx_change_mtu - Change the Maximum Transfer Unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * @ndev: network interface device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * @new_mtu: new value for maximum frame size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * Returns 0 on success, negative on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static int bdx_change_mtu(struct net_device *ndev, int new_mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ndev->mtu = new_mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (netif_running(ndev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) bdx_close(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) bdx_open(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) RET(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static void bdx_setmulti(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct bdx_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) u32 rxf_val =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB | GMAC_RX_FILTER_OSEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* IMF - imperfect (hash) rx multicat filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* PMF - perfect rx multicat filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* FIXME: RXE(OFF) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (ndev->flags & IFF_PROMISC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) rxf_val |= GMAC_RX_FILTER_PRM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) } else if (ndev->flags & IFF_ALLMULTI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* set IMF to accept all multicast frmaes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) for (i = 0; i < MAC_MCST_HASH_NUM; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) } else if (!netdev_mc_empty(ndev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) u8 hash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u32 reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* set IMF to deny all multicast frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) for (i = 0; i < MAC_MCST_HASH_NUM; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* set PMF to deny all multicast frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) for (i = 0; i < MAC_MCST_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* use PMF to accept first MAC_MCST_NUM (15) addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* TBD: sort addresses and write them in ascending order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * into RX_MAC_MCST regs. we skip this phase now and accept ALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * multicast frames throu IMF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* accept the rest of addresses throu IMF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) netdev_for_each_mc_addr(ha, ndev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) hash = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) for (i = 0; i < ETH_ALEN; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) hash ^= ha->addr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) reg = regRX_MCST_HASH0 + ((hash >> 5) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) val = READ_REG(priv, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) val |= (1 << (hash % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) WRITE_REG(priv, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) DBG("only own mac %d\n", netdev_mc_count(ndev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) rxf_val |= GMAC_RX_FILTER_AB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) WRITE_REG(priv, regGMAC_RXF_A, rxf_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* enable RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* FIXME: RXE(ON) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) RET();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static int bdx_set_mac(struct net_device *ndev, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct bdx_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct sockaddr *addr = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return -EBUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) bdx_restore_mac(ndev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) RET(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static int bdx_read_mac(struct bdx_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) u16 macAddress[3], i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) priv->ndev->dev_addr[i * 2 + 1] = macAddress[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) priv->ndev->dev_addr[i * 2] = macAddress[i] >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) RET(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) val = READ_REG(priv, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) val |= ((u64) READ_REG(priv, reg + 8)) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /*Do the statistics-update work*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static void bdx_update_stats(struct bdx_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct bdx_stats *stats = &priv->hw_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) u64 *stats_vector = (u64 *) stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /*Fill HW structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) addr = 0x7200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /*First 12 statistics - 0x7200 - 0x72B0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) for (i = 0; i < 12; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) stats_vector[i] = bdx_read_l2stat(priv, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) addr += 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) BDX_ASSERT(addr != 0x72C0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* 0x72C0-0x72E0 RSRV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) addr = 0x72F0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) for (; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) stats_vector[i] = bdx_read_l2stat(priv, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) addr += 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) BDX_ASSERT(addr != 0x7330);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* 0x7330-0x7360 RSRV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) addr = 0x7370;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) for (; i < 19; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) stats_vector[i] = bdx_read_l2stat(priv, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) addr += 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) BDX_ASSERT(addr != 0x73A0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* 0x73A0-0x73B0 RSRV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) addr = 0x73C0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) for (; i < 23; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) stats_vector[i] = bdx_read_l2stat(priv, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) addr += 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) BDX_ASSERT(addr != 0x7400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) BDX_ASSERT((sizeof(struct bdx_stats) / sizeof(u64)) != i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) u16 rxd_vlan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static void print_rxfd(struct rxf_desc *rxfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * Rx DB *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) *************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static void bdx_rxdb_destroy(struct rxdb *db)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) vfree(db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static struct rxdb *bdx_rxdb_create(int nelem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct rxdb *db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) db = vmalloc(sizeof(struct rxdb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) + (nelem * sizeof(int))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) + (nelem * sizeof(struct rx_map)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (likely(db != NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) db->stack = (int *)(db + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) db->elems = (void *)(db->stack + nelem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) db->nelem = nelem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) db->top = nelem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) for (i = 0; i < nelem; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) db->stack[i] = nelem - i - 1; /* to make first allocs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) close to db struct*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static inline int bdx_rxdb_alloc_elem(struct rxdb *db)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) BDX_ASSERT(db->top <= 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return db->stack[--(db->top)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static inline void *bdx_rxdb_addr_elem(struct rxdb *db, int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) BDX_ASSERT((n < 0) || (n >= db->nelem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return db->elems + n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static inline int bdx_rxdb_available(struct rxdb *db)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return db->top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static inline void bdx_rxdb_free_elem(struct rxdb *db, int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) BDX_ASSERT((n >= db->nelem) || (n < 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) db->stack[(db->top)++] = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * Rx Init *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) *************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * bdx_rx_init - initialize RX all related HW and SW resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * @priv: NIC private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * Returns 0 on success, negative value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * It creates rxf and rxd fifos, update relevant HW registers, preallocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * skb for rx. It assumes that Rx is desabled in HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * funcs are grouped for better cache usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * RxD fifo is smaller than RxF fifo by design. Upon high load, RxD will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * filled and packets will be dropped by nic without getting into host or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * cousing interrupt. Anyway, in that condition, host has no chance to process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* TBD: ensure proper packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static int bdx_rx_init(struct bdx_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (bdx_fifo_init(priv, &priv->rxd_fifo0.m, priv->rxd_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) regRXD_CFG0_0, regRXD_CFG1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) regRXD_RPTR_0, regRXD_WPTR_0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (bdx_fifo_init(priv, &priv->rxf_fifo0.m, priv->rxf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) regRXF_CFG0_0, regRXF_CFG1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) regRXF_RPTR_0, regRXF_WPTR_0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) priv->rxdb = bdx_rxdb_create(priv->rxf_fifo0.m.memsz /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) sizeof(struct rxf_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (!priv->rxdb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) priv->rxf_fifo0.m.pktsz = priv->ndev->mtu + VLAN_ETH_HLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) err_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) netdev_err(priv->ndev, "Rx init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * bdx_rx_free_skbs - frees and unmaps all skbs allocated for the fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * @priv: NIC private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * @f: RXF fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static void bdx_rx_free_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct rx_map *dm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) struct rxdb *db = priv->rxdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) u16 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) DBG("total=%d free=%d busy=%d\n", db->nelem, bdx_rxdb_available(db),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) db->nelem - bdx_rxdb_available(db));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) while (bdx_rxdb_available(db) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) i = bdx_rxdb_alloc_elem(db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) dm = bdx_rxdb_addr_elem(db, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) dm->dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) for (i = 0; i < db->nelem; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) dm = bdx_rxdb_addr_elem(db, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (dm->dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) dma_unmap_single(&priv->pdev->dev, dm->dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) f->m.pktsz, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) dev_kfree_skb(dm->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * bdx_rx_free - release all Rx resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * @priv: NIC private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * It assumes that Rx is desabled in HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static void bdx_rx_free(struct bdx_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if (priv->rxdb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) bdx_rx_free_skbs(priv, &priv->rxf_fifo0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) bdx_rxdb_destroy(priv->rxdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) priv->rxdb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) bdx_fifo_free(priv, &priv->rxf_fifo0.m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) bdx_fifo_free(priv, &priv->rxd_fifo0.m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) RET();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * Rx Engine *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) *************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * bdx_rx_alloc_skbs - fill rxf fifo with new skbs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * @priv: nic's private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * @f: RXF fifo that needs skbs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * It allocates skbs, build rxf descs and push it (rxf descr) into rxf fifo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * skb's virtual and physical addresses are stored in skb db.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * To calculate free space, func uses cached values of RPTR and WPTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * When needed, it also updates RPTR and WPTR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /* TBD: do not update WPTR if no desc were written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct rxf_desc *rxfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct rx_map *dm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) int dno, delta, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct rxdb *db = priv->rxdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) dno = bdx_rxdb_available(db) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) while (dno > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) skb = netdev_alloc_skb(priv->ndev, f->m.pktsz + NET_IP_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) skb_reserve(skb, NET_IP_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) idx = bdx_rxdb_alloc_elem(db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) dm = bdx_rxdb_addr_elem(db, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) dm->dma = dma_map_single(&priv->pdev->dev, skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) f->m.pktsz, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) dm->skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) rxfd->va_lo = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) print_rxfd(rxfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) f->m.wptr += sizeof(struct rxf_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) delta = f->m.wptr - f->m.memsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (unlikely(delta >= 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) f->m.wptr = delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (delta > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) memcpy(f->m.va, f->m.va + f->m.memsz, delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) DBG("wrapped descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) dno--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /*TBD: to do - delayed rxf wptr like in txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) RET();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) NETIF_RX_MUX(struct bdx_priv *priv, u32 rxd_val1, u16 rxd_vlan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) DBG("rxdd->flags.bits.vtag=%d\n", GET_RXD_VTAG(rxd_val1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (GET_RXD_VTAG(rxd_val1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) DBG("%s: vlan rcv vlan '%x' vtag '%x'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) priv->ndev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) GET_RXD_VLAN_ID(rxd_vlan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) GET_RXD_VTAG(rxd_val1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), GET_RXD_VLAN_TCI(rxd_vlan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) netif_receive_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static void bdx_recycle_skb(struct bdx_priv *priv, struct rxd_desc *rxdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct rxf_desc *rxfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct rx_map *dm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct rxf_fifo *f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) struct rxdb *db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) int delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) DBG("priv=%p rxdd=%p\n", priv, rxdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) f = &priv->rxf_fifo0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) db = priv->rxdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) DBG("db=%p f=%p\n", db, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) DBG("dm=%p\n", dm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) rxfd->va_lo = rxdd->va_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) print_rxfd(rxfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) f->m.wptr += sizeof(struct rxf_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) delta = f->m.wptr - f->m.memsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (unlikely(delta >= 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) f->m.wptr = delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (delta > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) memcpy(f->m.va, f->m.va + f->m.memsz, delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) DBG("wrapped descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) RET();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * bdx_rx_receive - receives full packets from RXD fifo and pass them to OS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) * NOTE: a special treatment is given to non-continuous descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) * that start near the end, wraps around and continue at the beginning. a second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * part is copied right after the first, and then descriptor is interpreted as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * normal. fifo has an extra space to allow such operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * @priv: nic's private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * @f: RXF fifo that needs skbs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * @budget: maximum number of packets to receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /* TBD: replace memcpy func call by explicite inline asm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) struct net_device *ndev = priv->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct sk_buff *skb, *skb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct rxd_desc *rxdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct rx_map *dm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct rxf_fifo *rxf_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) int tmp_len, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) int done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) int max_done = BDX_MAX_RX_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) struct rxdb *db = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* Unmarshalled descriptor - copy of descriptor in host order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) u32 rxd_val1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) u16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) u16 rxd_vlan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) max_done = budget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) size = f->m.wptr - f->m.rptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (size < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) size = f->m.memsz + size; /* size is negative :-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) while (size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) rxd_val1 = CPU_CHIP_SWAP32(rxdd->rxd_val1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) len = CPU_CHIP_SWAP16(rxdd->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) rxd_vlan = CPU_CHIP_SWAP16(rxdd->rxd_vlan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) print_rxdd(rxdd, rxd_val1, len, rxd_vlan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) tmp_len = GET_RXD_BC(rxd_val1) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) BDX_ASSERT(tmp_len <= 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) size -= tmp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (size < 0) /* test for partially arrived descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) f->m.rptr += tmp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) tmp_len = f->m.rptr - f->m.memsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (unlikely(tmp_len >= 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) f->m.rptr = tmp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (tmp_len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) DBG("wrapped desc rptr=%d tmp_len=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) f->m.rptr, tmp_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (unlikely(GET_RXD_ERR(rxd_val1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) ndev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) bdx_recycle_skb(priv, rxdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) rxf_fifo = &priv->rxf_fifo0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) db = priv->rxdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) skb = dm->skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (len < BDX_COPYBREAK &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) (skb2 = netdev_alloc_skb(priv->ndev, len + NET_IP_ALIGN))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) skb_reserve(skb2, NET_IP_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /*skb_put(skb2, len); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) dma_sync_single_for_cpu(&priv->pdev->dev, dm->dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) rxf_fifo->m.pktsz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) memcpy(skb2->data, skb->data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) bdx_recycle_skb(priv, rxdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) skb = skb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) dma_unmap_single(&priv->pdev->dev, dm->dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) rxf_fifo->m.pktsz, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) bdx_rxdb_free_elem(db, rxdd->va_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) ndev->stats.rx_bytes += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) skb_put(skb, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) skb->protocol = eth_type_trans(skb, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) /* Non-IP packets aren't checksum-offloaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (GET_RXD_PKT_ID(rxd_val1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) skb_checksum_none_assert(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) skb->ip_summed = CHECKSUM_UNNECESSARY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) NETIF_RX_MUX(priv, rxd_val1, rxd_vlan, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (++done >= max_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ndev->stats.rx_packets += done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /* FIXME: do smth to minimize pci accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) RET(done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) * Debug / Temprorary Code *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) *************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) u16 rxd_vlan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) DBG("ERROR: rxdd bc %d rxfq %d to %d type %d err %d rxp %d pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d va_lo %d va_hi %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) GET_RXD_BC(rxd_val1), GET_RXD_RXFQ(rxd_val1), GET_RXD_TO(rxd_val1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) GET_RXD_TYPE(rxd_val1), GET_RXD_ERR(rxd_val1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) GET_RXD_RXP(rxd_val1), GET_RXD_PKT_ID(rxd_val1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) GET_RXD_VTAG(rxd_val1), len, GET_RXD_VLAN_ID(rxd_vlan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) GET_RXD_CFI(rxd_vlan), GET_RXD_PRIO(rxd_vlan), rxdd->va_lo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) rxdd->va_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) static void print_rxfd(struct rxf_desc *rxfd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) DBG("=== RxF desc CHIP ORDER/ENDIANNESS =============\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) rxfd->info, rxfd->va_lo, rxfd->pa_lo, rxfd->pa_hi, rxfd->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * TX HW/SW interaction overview
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * There are 2 types of TX communication channels between driver and NIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * 1) TX Free Fifo - TXF - holds ack descriptors for sent packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * 2) TX Data Fifo - TXD - holds descriptors of full buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) * Currently NIC supports TSO, checksuming and gather DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) * UFO and IP fragmentation is on the way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * RX SW Data Structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * ~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * txdb - used to keep track of all skbs owned by SW and their dma addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * For TX case, ownership lasts from geting packet via hard_xmit and until HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * acknowledges sent by TXF descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * Implemented as cyclic buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) * fifo - keeps info about fifo's size and location, relevant HW registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * Implemented as simple struct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * TX SW Execution Flow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * ~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * OS calls driver's hard_xmit method with packet to sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) * Driver creates DMA mappings, builds TXD descriptors and kicks HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) * by updating TXD WPTR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) * When packet is sent, HW write us TXF descriptor and SW frees original skb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) * To prevent TXD fifo overflow without reading HW registers every time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) * SW deploys "tx level" technique.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) * Upon strart up, tx level is initialized to TXD fifo length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) * For every sent packet, SW gets its TXD descriptor sizei
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) * (from precalculated array) and substructs it from tx level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) * The size is also stored in txdb. When TXF ack arrives, SW fetch size of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) * original TXD descriptor from txdb and adds it to tx level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) * When Tx level drops under some predefined treshhold, the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * stops the TX queue. When TX level rises above that level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * the tx queue is enabled again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) * This technique avoids eccessive reading of RPTR and WPTR registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) * As our benchmarks shows, it adds 1.5 Gbit/sec to NIS's throuput.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * __bdx_tx_db_ptr_next - helper function, increment read/write pointer + wrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) * @db: tx data base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) * @pptr: read or write pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) static inline void __bdx_tx_db_ptr_next(struct txdb *db, struct tx_map **pptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) BDX_ASSERT(db == NULL || pptr == NULL); /* sanity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) BDX_ASSERT(*pptr != db->rptr && /* expect either read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) *pptr != db->wptr); /* or write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) BDX_ASSERT(*pptr < db->start || /* pointer has to be */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) *pptr >= db->end); /* in range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) ++*pptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (unlikely(*pptr == db->end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) *pptr = db->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) * bdx_tx_db_inc_rptr - increment read pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) * @db: tx data base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) static inline void bdx_tx_db_inc_rptr(struct txdb *db)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) __bdx_tx_db_ptr_next(db, &db->rptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * bdx_tx_db_inc_wptr - increment write pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * @db: tx data base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) static inline void bdx_tx_db_inc_wptr(struct txdb *db)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) __bdx_tx_db_ptr_next(db, &db->wptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) a result of write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) * bdx_tx_db_init - creates and initializes tx db
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) * @d: tx data base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) * @sz_type: size of tx fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) * Returns 0 on success, error code otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) static int bdx_tx_db_init(struct txdb *d, int sz_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) int memsz = FIFO_SIZE * (1 << (sz_type + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) d->start = vmalloc(memsz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (!d->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) * In order to differentiate between db is empty and db is full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) * states at least one element should always be empty in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) * avoid rptr == wptr which means db is empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) d->size = memsz / sizeof(struct tx_map) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) d->end = d->start + d->size + 1; /* just after last element */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) /* all dbs are created equally empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) d->rptr = d->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) d->wptr = d->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) * bdx_tx_db_close - closes tx db and frees all memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) * @d: tx data base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) static void bdx_tx_db_close(struct txdb *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) BDX_ASSERT(d == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) vfree(d->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) d->start = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) * Tx Engine *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) *************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /* sizes of tx desc (including padding if needed) as function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) * of skb's frag number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) u16 bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) u16 qwords; /* qword = 64 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) } txd_sizes[MAX_SKB_FRAGS + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) * bdx_tx_map_skb - creates and stores dma mappings for skb's data blocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * @priv: NIC private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) * @skb: socket buffer to map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) * @txdd: TX descriptor to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) * It makes dma mappings for skb's data blocks and writes them to PBL of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) * new tx descriptor. It also stores them in the tx db, so they could be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) * unmaped after data was sent. It is reponsibility of a caller to make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * sure that there is enough space in the tx db. Last element holds pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) * to skb itself and marked with zero length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) bdx_tx_map_skb(struct bdx_priv *priv, struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) struct txd_desc *txdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) struct txdb *db = &priv->txdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) struct pbl *pbl = &txdd->pbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) int nr_frags = skb_shinfo(skb)->nr_frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) db->wptr->len = skb_headlen(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) db->wptr->addr.dma = dma_map_single(&priv->pdev->dev, skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) db->wptr->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) DBG("=== pbl len: 0x%x ================\n", pbl->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) DBG("=== pbl pa_lo: 0x%x ================\n", pbl->pa_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) DBG("=== pbl pa_hi: 0x%x ================\n", pbl->pa_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) bdx_tx_db_inc_wptr(db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) for (i = 0; i < nr_frags; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) const skb_frag_t *frag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) frag = &skb_shinfo(skb)->frags[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) db->wptr->len = skb_frag_size(frag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) db->wptr->addr.dma = skb_frag_dma_map(&priv->pdev->dev, frag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) 0, skb_frag_size(frag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) pbl++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) bdx_tx_db_inc_wptr(db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) /* add skb clean up info. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) db->wptr->len = -txd_sizes[nr_frags].bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) db->wptr->addr.skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) bdx_tx_db_inc_wptr(db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) /* init_txd_sizes - precalculate sizes of descriptors for skbs up to 16 frags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) * number of frags is used as index to fetch correct descriptors size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) * instead of calculating it each time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static void __init init_txd_sizes(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) int i, lwords;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* 7 - is number of lwords in txd with one phys buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) * 3 - is number of lwords used for every additional phys buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) for (i = 0; i < MAX_SKB_FRAGS + 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) lwords = 7 + (i * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (lwords & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) lwords++; /* pad it with 1 lword */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) txd_sizes[i].qwords = lwords >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) txd_sizes[i].bytes = lwords << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) /* bdx_tx_init - initialize all Tx related stuff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) * Namely, TXD and TXF fifos, database etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static int bdx_tx_init(struct bdx_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (bdx_fifo_init(priv, &priv->txd_fifo0.m, priv->txd_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) regTXD_CFG0_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) regTXD_CFG1_0, regTXD_RPTR_0, regTXD_WPTR_0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (bdx_fifo_init(priv, &priv->txf_fifo0.m, priv->txf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) regTXF_CFG0_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) regTXF_CFG1_0, regTXF_RPTR_0, regTXF_WPTR_0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) /* The TX db has to keep mappings for all packets sent (on TxD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) * and not yet reclaimed (on TxF) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) if (bdx_tx_db_init(&priv->txdb, max(priv->txd_size, priv->txf_size)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) priv->tx_level = BDX_MAX_TX_LEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) #ifdef BDX_DELAY_WPTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) priv->tx_update_mark = priv->tx_level - 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) err_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) netdev_err(priv->ndev, "Tx init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) * bdx_tx_space - calculates available space in TX fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) * @priv: NIC private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) * Returns available space in TX fifo in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) static inline int bdx_tx_space(struct bdx_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) struct txd_fifo *f = &priv->txd_fifo0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) int fsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) fsize = f->m.rptr - f->m.wptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) if (fsize <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) fsize = f->m.memsz + fsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) return fsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) * bdx_tx_transmit - send packet to NIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) * @skb: packet to send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) * @ndev: network device assigned to NIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) * Return codes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) * o NETDEV_TX_OK everything ok.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) * o NETDEV_TX_BUSY Cannot transmit packet, try later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) * Usually a bug, means queue start/stop flow control is broken in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) * the driver. Note: the driver must NOT put the skb in its DMA ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) static netdev_tx_t bdx_tx_transmit(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) struct bdx_priv *priv = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) struct txd_fifo *f = &priv->txd_fifo0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) int txd_checksum = 7; /* full checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) int txd_lgsnd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) int txd_vlan_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) int txd_vtag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) int txd_mss = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) int nr_frags = skb_shinfo(skb)->nr_frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) struct txd_desc *txdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) spin_lock(&priv->tx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) /* build tx descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) txdd = (struct txd_desc *)(f->m.va + f->m.wptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) txd_checksum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) if (skb_shinfo(skb)->gso_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) txd_mss = skb_shinfo(skb)->gso_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) txd_lgsnd = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) DBG("skb %p skb len %d gso size = %d\n", skb, skb->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) txd_mss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (skb_vlan_tag_present(skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) /*Cut VLAN ID to 12 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) txd_vlan_id = skb_vlan_tag_get(skb) & BITS_MASK(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) txd_vtag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) txdd->length = CPU_CHIP_SWAP16(skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) txdd->mss = CPU_CHIP_SWAP16(txd_mss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) txdd->txd_val1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) CPU_CHIP_SWAP32(TXD_W1_VAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) (txd_sizes[nr_frags].qwords, txd_checksum, txd_vtag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) txd_lgsnd, txd_vlan_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) DBG("=== TxD desc =====================\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) DBG("=== w1: 0x%x ================\n", txdd->txd_val1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) DBG("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) bdx_tx_map_skb(priv, skb, txdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) /* increment TXD write pointer. In case of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) fifo wrapping copy reminder of the descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) to the beginning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) f->m.wptr += txd_sizes[nr_frags].bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) len = f->m.wptr - f->m.memsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) if (unlikely(len >= 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) f->m.wptr = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) if (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) BDX_ASSERT(len > f->m.memsz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) memcpy(f->m.va, f->m.va + f->m.memsz, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) priv->tx_level -= txd_sizes[nr_frags].bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) #ifdef BDX_DELAY_WPTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) if (priv->tx_level > priv->tx_update_mark) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) /* Force memory writes to complete before letting h/w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) know there are new descriptors to fetch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) (might be needed on platforms like IA64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) wmb(); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (priv->tx_noupd++ > BDX_NO_UPD_PACKETS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) priv->tx_noupd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) WRITE_REG(priv, f->m.reg_WPTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) f->m.wptr & TXF_WPTR_WR_PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) /* Force memory writes to complete before letting h/w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) know there are new descriptors to fetch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) (might be needed on platforms like IA64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) wmb(); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) #ifdef BDX_LLTX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) netif_trans_update(ndev); /* NETIF_F_LLTX driver :( */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) ndev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) ndev->stats.tx_bytes += skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) if (priv->tx_level < BDX_MIN_TX_LEVEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) DBG("%s: %s: TX Q STOP level %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) BDX_DRV_NAME, ndev->name, priv->tx_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) netif_stop_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) spin_unlock_irqrestore(&priv->tx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) * bdx_tx_cleanup - clean TXF fifo, run in the context of IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) * @priv: bdx adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) * It scans TXF fifo for descriptors, frees DMA mappings and reports to OS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) * that those packets were sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) static void bdx_tx_cleanup(struct bdx_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) struct txf_fifo *f = &priv->txf_fifo0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) struct txdb *db = &priv->txdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) int tx_level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) BDX_ASSERT(f->m.rptr >= f->m.memsz); /* started with valid rptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) while (f->m.wptr != f->m.rptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) f->m.rptr += BDX_TXF_DESC_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) f->m.rptr &= f->m.size_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) /* unmap all the fragments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) /* first has to come tx_maps containing dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) BDX_ASSERT(db->rptr->len == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) BDX_ASSERT(db->rptr->addr.dma == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) dma_unmap_page(&priv->pdev->dev, db->rptr->addr.dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) db->rptr->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) bdx_tx_db_inc_rptr(db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) } while (db->rptr->len > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) tx_level -= db->rptr->len; /* '-' koz len is negative */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) /* now should come skb pointer - free it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) dev_consume_skb_irq(db->rptr->addr.skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) bdx_tx_db_inc_rptr(db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) /* let h/w know which TXF descriptors were cleaned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) /* We reclaimed resources, so in case the Q is stopped by xmit callback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) * we resume the transmission and use tx_lock to synchronize with xmit.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) spin_lock(&priv->tx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) priv->tx_level += tx_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) #ifdef BDX_DELAY_WPTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) if (priv->tx_noupd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) priv->tx_noupd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) if (unlikely(netif_queue_stopped(priv->ndev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) netif_carrier_ok(priv->ndev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) (priv->tx_level >= BDX_MIN_TX_LEVEL))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) DBG("%s: %s: TX Q WAKE level %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) BDX_DRV_NAME, priv->ndev->name, priv->tx_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) netif_wake_queue(priv->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) spin_unlock(&priv->tx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) * bdx_tx_free_skbs - frees all skbs from TXD fifo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) * @priv: NIC private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) * It gets called when OS stops this dev, eg upon "ifconfig down" or rmmod
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) static void bdx_tx_free_skbs(struct bdx_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) struct txdb *db = &priv->txdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) while (db->rptr != db->wptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) if (likely(db->rptr->len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) dma_unmap_page(&priv->pdev->dev, db->rptr->addr.dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) db->rptr->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) dev_kfree_skb(db->rptr->addr.skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) bdx_tx_db_inc_rptr(db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) RET();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) /* bdx_tx_free - frees all Tx resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) static void bdx_tx_free(struct bdx_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) bdx_tx_free_skbs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) bdx_fifo_free(priv, &priv->txd_fifo0.m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) bdx_fifo_free(priv, &priv->txf_fifo0.m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) bdx_tx_db_close(&priv->txdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) * bdx_tx_push_desc - push descriptor to TxD fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) * @priv: NIC private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) * @data: desc's data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) * @size: desc's size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) * Pushes desc to TxD fifo and overlaps it if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) * NOTE: this func does not check for available space. this is responsibility
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) * of the caller. Neither does it check that data size is smaller than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) * fifo size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) struct txd_fifo *f = &priv->txd_fifo0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) int i = f->m.memsz - f->m.wptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) if (size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) if (i > size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) memcpy(f->m.va + f->m.wptr, data, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) f->m.wptr += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) memcpy(f->m.va + f->m.wptr, data, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) f->m.wptr = size - i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) memcpy(f->m.va, data + i, f->m.wptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) * bdx_tx_push_desc_safe - push descriptor to TxD fifo in a safe way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) * @priv: NIC private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) * @data: desc's data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) * @size: desc's size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) * NOTE: this func does check for available space and, if necessary, waits for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) * NIC to read existing data before writing new one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) int timer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) while (size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) /* we substruct 8 because when fifo is full rptr == wptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) which also means that fifo is empty, we can understand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) the difference, but could hw do the same ??? :) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) int avail = bdx_tx_space(priv) - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) if (avail <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) if (timer++ > 300) { /* prevent endless loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) DBG("timeout while writing desc to TxD fifo\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) udelay(50); /* give hw a chance to clean fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) avail = min(avail, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) DBG("about to push %d bytes starting %p size %d\n", avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) data, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) bdx_tx_push_desc(priv, data, avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) size -= avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) data += avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) RET();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) static const struct net_device_ops bdx_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .ndo_open = bdx_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .ndo_stop = bdx_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .ndo_start_xmit = bdx_tx_transmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .ndo_do_ioctl = bdx_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .ndo_set_rx_mode = bdx_setmulti,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .ndo_change_mtu = bdx_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .ndo_set_mac_address = bdx_set_mac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .ndo_vlan_rx_add_vid = bdx_vlan_rx_add_vid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .ndo_vlan_rx_kill_vid = bdx_vlan_rx_kill_vid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) * bdx_probe - Device Initialization Routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) * @pdev: PCI device information struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) * @ent: entry in bdx_pci_tbl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) * Returns 0 on success, negative on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) * bdx_probe initializes an adapter identified by a pci_dev structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) * The OS initialization, configuring of the adapter private structure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) * and a hardware reset occur.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) * functions and their order used as explained in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) * /usr/src/linux/Documentation/DMA-{API,mapping}.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) /* TBD: netif_msg should be checked and implemented. I disable it for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) bdx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) struct net_device *ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) struct bdx_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) int err, pci_using_dac, port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) unsigned long pciaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) u32 regionSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) struct pci_nic *nic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) nic = vmalloc(sizeof(*nic));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) if (!nic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) RET(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) /************** pci *****************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) err = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) if (err) /* it triggers interrupt, dunno why. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) goto err_pci; /* it's not a problem though */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) if (!(err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) !(err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) pci_using_dac = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) if ((err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) (err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) pr_err("No usable DMA configuration, aborting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) goto err_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) pci_using_dac = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) err = pci_request_regions(pdev, BDX_DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) goto err_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) pciaddr = pci_resource_start(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) if (!pciaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) pr_err("no MMIO resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) goto err_out_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) regionSize = pci_resource_len(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) if (regionSize < BDX_REGS_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) pr_err("MMIO resource (%x) too small\n", regionSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) goto err_out_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) nic->regs = ioremap(pciaddr, regionSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) if (!nic->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) pr_err("ioremap failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) goto err_out_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) if (pdev->irq < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) pr_err("invalid irq (%d)\n", pdev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) goto err_out_iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) pci_set_drvdata(pdev, nic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) if (pdev->device == 0x3014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) nic->port_num = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) nic->port_num = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) print_hw_id(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) bdx_hw_reset_direct(nic->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) nic->irq_type = IRQ_INTX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) #ifdef BDX_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) if ((readl(nic->regs + FPGA_VER) & 0xFFF) >= 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) err = pci_enable_msi(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) pr_err("Can't enable msi. error is %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) nic->irq_type = IRQ_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) DBG("HW does not support MSI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) /************** netdev **************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) for (port = 0; port < nic->port_num; port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) ndev = alloc_etherdev(sizeof(struct bdx_priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) if (!ndev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) goto err_out_iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) ndev->netdev_ops = &bdx_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) ndev->tx_queue_len = BDX_NDEV_TXQ_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) bdx_set_ethtool_ops(ndev); /* ethtool interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) /* these fields are used for info purposes only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) * so we can have them same for all ports of the board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) ndev->if_port = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXCSUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) NETIF_F_TSO | NETIF_F_HW_VLAN_CTAG_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) if (pci_using_dac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) ndev->features |= NETIF_F_HIGHDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) /************** priv ****************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) priv = nic->priv[port] = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) priv->pBdxRegs = nic->regs + port * 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) priv->port = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) priv->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) priv->ndev = ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) priv->nic = nic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) priv->msg_enable = BDX_DEF_MSG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) netif_napi_add(ndev, &priv->napi, bdx_poll, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) if ((readl(nic->regs + FPGA_VER) & 0xFFF) == 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) DBG("HW statistics not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) priv->stats_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) priv->stats_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) /* Initialize fifo sizes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) priv->txd_size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) priv->txf_size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) priv->rxd_size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) priv->rxf_size = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) /* Initialize the initial coalescing registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) /* ndev->xmit_lock spinlock is not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) * Private priv->tx_lock is used for synchronization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) * between transmit and TX irq cleanup. In addition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) * set multicast list callback has to use priv->tx_lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) #ifdef BDX_LLTX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) ndev->features |= NETIF_F_LLTX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) /* MTU range: 60 - 16384 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) ndev->min_mtu = ETH_ZLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) ndev->max_mtu = BDX_MAX_MTU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) spin_lock_init(&priv->tx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) /*bdx_hw_reset(priv); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) if (bdx_read_mac(priv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) pr_err("load MAC address failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) err = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) goto err_out_iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) SET_NETDEV_DEV(ndev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) err = register_netdev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) pr_err("register_netdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) goto err_out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) netif_carrier_off(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) netif_stop_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) print_eth_id(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) RET(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) err_out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) free_netdev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) err_out_iomap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) iounmap(nic->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) err_out_res:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) err_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) err_pci:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) vfree(nic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) RET(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) /****************** Ethtool interface *********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) /* get strings for statistics counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) static const char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) bdx_stat_names[][ETH_GSTRING_LEN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) "InUCast", /* 0x7200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) "InMCast", /* 0x7210 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) "InBCast", /* 0x7220 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) "InPkts", /* 0x7230 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) "InErrors", /* 0x7240 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) "InDropped", /* 0x7250 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) "FrameTooLong", /* 0x7260 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) "FrameSequenceErrors", /* 0x7270 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) "InVLAN", /* 0x7280 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) "InDroppedDFE", /* 0x7290 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) "InDroppedIntFull", /* 0x72A0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) "InFrameAlignErrors", /* 0x72B0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) /* 0x72C0-0x72E0 RSRV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) "OutUCast", /* 0x72F0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) "OutMCast", /* 0x7300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) "OutBCast", /* 0x7310 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) "OutPkts", /* 0x7320 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) /* 0x7330-0x7360 RSRV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) "OutVLAN", /* 0x7370 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) "InUCastOctects", /* 0x7380 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) "OutUCastOctects", /* 0x7390 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) /* 0x73A0-0x73B0 RSRV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) "InBCastOctects", /* 0x73C0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) "OutBCastOctects", /* 0x73D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) "InOctects", /* 0x73E0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) "OutOctects", /* 0x73F0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) * bdx_get_link_ksettings - get device-specific settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) * @netdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) * @ecmd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) static int bdx_get_link_ksettings(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) struct ethtool_link_ksettings *ecmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) ethtool_link_ksettings_zero_link_mode(ecmd, supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) ethtool_link_ksettings_add_link_mode(ecmd, supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) 10000baseT_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) ethtool_link_ksettings_add_link_mode(ecmd, supported, FIBRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) ethtool_link_ksettings_zero_link_mode(ecmd, advertising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) ethtool_link_ksettings_add_link_mode(ecmd, advertising,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) 10000baseT_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) ethtool_link_ksettings_add_link_mode(ecmd, advertising, FIBRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) ecmd->base.speed = SPEED_10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) ecmd->base.duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) ecmd->base.port = PORT_FIBRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) ecmd->base.autoneg = AUTONEG_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) * bdx_get_drvinfo - report driver information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) * @netdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) * @drvinfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) bdx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) struct bdx_priv *priv = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) strlcpy(drvinfo->driver, BDX_DRV_NAME, sizeof(drvinfo->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) strlcpy(drvinfo->version, BDX_DRV_VERSION, sizeof(drvinfo->version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) strlcpy(drvinfo->bus_info, pci_name(priv->pdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) sizeof(drvinfo->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) * bdx_get_coalesce - get interrupt coalescing parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) * @netdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) * @ecoal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) bdx_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) u32 rdintcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) u32 tdintcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) struct bdx_priv *priv = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) rdintcm = priv->rdintcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) tdintcm = priv->tdintcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) /* PCK_TH measures in multiples of FIFO bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) We translate to packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) ecoal->rx_coalesce_usecs = GET_INT_COAL(rdintcm) * INT_COAL_MULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) ecoal->rx_max_coalesced_frames =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) ecoal->tx_coalesce_usecs = GET_INT_COAL(tdintcm) * INT_COAL_MULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) ecoal->tx_max_coalesced_frames =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) /* adaptive parameters ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) * bdx_set_coalesce - set interrupt coalescing parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) * @netdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) * @ecoal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) bdx_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) u32 rdintcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) u32 tdintcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) struct bdx_priv *priv = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) int rx_coal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) int tx_coal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) int rx_max_coal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) int tx_max_coal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) /* Check for valid input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) rx_coal = ecoal->rx_coalesce_usecs / INT_COAL_MULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) tx_coal = ecoal->tx_coalesce_usecs / INT_COAL_MULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) rx_max_coal = ecoal->rx_max_coalesced_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) tx_max_coal = ecoal->tx_max_coalesced_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) /* Translate from packets to multiples of FIFO bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) rx_max_coal =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) (((rx_max_coal * sizeof(struct rxf_desc)) + PCK_TH_MULT - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) / PCK_TH_MULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) tx_max_coal =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) (((tx_max_coal * BDX_TXF_DESC_SZ) + PCK_TH_MULT - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) / PCK_TH_MULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) if ((rx_coal > 0x7FFF) || (tx_coal > 0x7FFF) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) (rx_max_coal > 0xF) || (tx_max_coal > 0xF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) rdintcm = INT_REG_VAL(rx_coal, GET_INT_COAL_RC(priv->rdintcm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) GET_RXF_TH(priv->rdintcm), rx_max_coal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) tdintcm = INT_REG_VAL(tx_coal, GET_INT_COAL_RC(priv->tdintcm), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) tx_max_coal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) priv->rdintcm = rdintcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) priv->tdintcm = tdintcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) WRITE_REG(priv, regRDINTCM0, rdintcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) WRITE_REG(priv, regTDINTCM0, tdintcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) /* Convert RX fifo size to number of pending packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) static inline int bdx_rx_fifo_size_to_packets(int rx_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) return (FIFO_SIZE * (1 << rx_size)) / sizeof(struct rxf_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) /* Convert TX fifo size to number of pending packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) static inline int bdx_tx_fifo_size_to_packets(int tx_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) return (FIFO_SIZE * (1 << tx_size)) / BDX_TXF_DESC_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) * bdx_get_ringparam - report ring sizes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) * @netdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) * @ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) bdx_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) struct bdx_priv *priv = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) /*max_pending - the maximum-sized FIFO we allow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) ring->rx_max_pending = bdx_rx_fifo_size_to_packets(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) ring->tx_max_pending = bdx_tx_fifo_size_to_packets(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) ring->rx_pending = bdx_rx_fifo_size_to_packets(priv->rxf_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) ring->tx_pending = bdx_tx_fifo_size_to_packets(priv->txd_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) * bdx_set_ringparam - set ring sizes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) * @netdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) * @ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) bdx_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) struct bdx_priv *priv = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) int rx_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) int tx_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) for (; rx_size < 4; rx_size++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) if (bdx_rx_fifo_size_to_packets(rx_size) >= ring->rx_pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) if (rx_size == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) rx_size = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) for (; tx_size < 4; tx_size++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) if (bdx_tx_fifo_size_to_packets(tx_size) >= ring->tx_pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) if (tx_size == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) tx_size = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) /*Is there anything to do? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) if ((rx_size == priv->rxf_size) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) (tx_size == priv->txd_size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) priv->rxf_size = rx_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) if (rx_size > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) priv->rxd_size = rx_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) priv->rxd_size = rx_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) priv->txf_size = priv->txd_size = tx_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) if (netif_running(netdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) bdx_close(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) bdx_open(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) * bdx_get_strings - return a set of strings that describe the requested objects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) * @netdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) * @data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) static void bdx_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) switch (stringset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) case ETH_SS_STATS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) memcpy(data, *bdx_stat_names, sizeof(bdx_stat_names));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) * bdx_get_sset_count - return number of statistics or tests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) * @netdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) static int bdx_get_sset_count(struct net_device *netdev, int stringset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) struct bdx_priv *priv = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) switch (stringset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) case ETH_SS_STATS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) BDX_ASSERT(ARRAY_SIZE(bdx_stat_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) != sizeof(struct bdx_stats) / sizeof(u64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) return (priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) * bdx_get_ethtool_stats - return device's hardware L2 statistics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) * @netdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) * @stats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) * @data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) static void bdx_get_ethtool_stats(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) struct ethtool_stats *stats, u64 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) struct bdx_priv *priv = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) if (priv->stats_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) /* Update stats from HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) bdx_update_stats(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) /* Copy data to user buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) memcpy(data, &priv->hw_stats, sizeof(priv->hw_stats));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) * bdx_set_ethtool_ops - ethtool interface implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) * @netdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) static void bdx_set_ethtool_ops(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) static const struct ethtool_ops bdx_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) ETHTOOL_COALESCE_MAX_FRAMES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) .get_drvinfo = bdx_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) .get_link = ethtool_op_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .get_coalesce = bdx_get_coalesce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .set_coalesce = bdx_set_coalesce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .get_ringparam = bdx_get_ringparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .set_ringparam = bdx_set_ringparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .get_strings = bdx_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .get_sset_count = bdx_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .get_ethtool_stats = bdx_get_ethtool_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .get_link_ksettings = bdx_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) netdev->ethtool_ops = &bdx_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) * bdx_remove - Device Removal Routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) * @pdev: PCI device information struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) * bdx_remove is called by the PCI subsystem to alert the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) * that it should release a PCI device. The could be caused by a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) * Hot-Plug event, or because the driver is going to be removed from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) * memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) static void bdx_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) struct pci_nic *nic = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) struct net_device *ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) for (port = 0; port < nic->port_num; port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) ndev = nic->priv[port]->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) unregister_netdev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) free_netdev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) /*bdx_hw_reset_direct(nic->regs); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) #ifdef BDX_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) if (nic->irq_type == IRQ_MSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) pci_disable_msi(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) iounmap(nic->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) vfree(nic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) RET();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) static struct pci_driver bdx_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .name = BDX_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .id_table = bdx_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .probe = bdx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) .remove = bdx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) * print_driver_id - print parameters of the driver build
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) static void __init print_driver_id(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) pr_info("%s, %s\n", BDX_DRV_DESC, BDX_DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) pr_info("Options: hw_csum %s\n", BDX_MSI_STRING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) static int __init bdx_module_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) init_txd_sizes();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) print_driver_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) RET(pci_register_driver(&bdx_pci_driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) module_init(bdx_module_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) static void __exit bdx_module_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) ENTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) pci_unregister_driver(&bdx_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) RET();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) module_exit(bdx_module_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) MODULE_AUTHOR(DRIVER_AUTHOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) MODULE_DESCRIPTION(BDX_DRV_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) MODULE_FIRMWARE("tehuti/bdx.bin");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags